WO2023217277A1 - Package structure, processor chip, pop package assembly and electronic device - Google Patents

Package structure, processor chip, pop package assembly and electronic device Download PDF

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Publication number
WO2023217277A1
WO2023217277A1 PCT/CN2023/093966 CN2023093966W WO2023217277A1 WO 2023217277 A1 WO2023217277 A1 WO 2023217277A1 CN 2023093966 W CN2023093966 W CN 2023093966W WO 2023217277 A1 WO2023217277 A1 WO 2023217277A1
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WO
WIPO (PCT)
Prior art keywords
data input
holes
output terminal
terminal signal
signal
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PCT/CN2023/093966
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French (fr)
Chinese (zh)
Inventor
周子翔
黄成�
褚雯
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哲库科技(上海)有限公司
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Publication of WO2023217277A1 publication Critical patent/WO2023217277A1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits

Definitions

  • This application relates to the field of chip technology, specifically to packaging structures, processor chips, POP packaging components and electronic equipment.
  • LPDDR Low Power Double Rate Synchronous Dynamic Random Access Memory
  • JEDEC Solid State Circuit Technology Association
  • 496ball POP vertical stacked package pinmap
  • DRAM chip dynamic random access memory chip
  • the DRAM package sizes corresponding to these three pinmaps are 15mm. *15mm, 14mm*14mm and 14mm*12.4mm.
  • these three pinmaps only provide 4 DRAM channels, and can only support a maximum data bandwidth of 64bits.
  • the present application provides a packaging structure.
  • the packaging structure includes: a substrate having a peripheral area, the peripheral area including a first side area, a second side area, a third side area and a fourth side area connected in sequence, the first side area being The side area, the second side area, the third side area and the fourth side area have signal through holes arranged in multiple rows and columns, and copper pillars are provided in the signal through holes.
  • the present application provides a processor chip.
  • the processor chip includes a packaging structure.
  • the packaging structure includes: a substrate, the substrate has a peripheral area, the peripheral area includes a first side area, a second side area, a third side area and a fourth side area connected in sequence, the first side area, the second side area
  • the side area, the third side area and the fourth side area have signal through holes arranged in multiple rows and columns, and copper pillars are provided in the signal through holes.
  • the present application provides a POP packaging component.
  • the POP package component includes: a processor chip and a first chip that is vertically stacked and packaged with the processor chip.
  • the processor chip includes a package structure.
  • the packaging structure includes: a substrate, the substrate has a peripheral area, the peripheral area includes a first side area, a second side area, a third side area and a fourth side area connected in sequence, the first side area, the second side area
  • the side area, the third side area and the fourth side area have signal through holes arranged in multiple rows and columns, and copper pillars are provided in the signal through holes.
  • the present application provides an electronic device.
  • the electronic device includes the aforementioned processor chip.
  • the processor chip includes a package structure.
  • the packaging structure includes: a substrate, the substrate has a peripheral area, the peripheral area includes a first side area, a second side area, a third side area and a fourth side area connected in sequence, the first side area, the second side area
  • the side area, the third side area and the fourth side area have signal through holes arranged in multiple rows and columns, and copper pillars are provided in the signal through holes.
  • Figure 1 is a schematic diagram of the packaging structure in one embodiment of the present application.
  • Figure 2 is a schematic diagram of a packaging structure in another embodiment of the present application.
  • Figure 3 is a schematic diagram of the packaging structure in yet another embodiment of the present application.
  • Figure 4 is a schematic diagram of the packaging structure in yet another embodiment of the present application.
  • Figure 5 is a schematic diagram of a processor chip in another embodiment of the present application.
  • Figure 6 is a schematic diagram of a POP packaging component in yet another embodiment of the present application.
  • the present application provides a packaging structure.
  • the packaging structure includes: a substrate 10, the substrate 10 has a peripheral area, and the peripheral area includes a first side area 11, a second side area 12, and a third side area that are connected in sequence. 13 and the fourth side area 14, the first side area 11, the second side area 12, the third side area 13 and the fourth side area 14 have signal via holes 20 arranged in multiple rows and columns, and conductors are arranged in the signal via holes 20.
  • the conductors may be copper posts, or other conductive materials known in the art.
  • the packaging structure can meet the outlet requirements of more signals by arranging multiple rows and columns of signal through holes 20 in the peripheral areas on all four sides of the substrate 10 , thereby doubling the memory access bandwidth of the chip.
  • the memory access bandwidth of a chip using this packaging structure can reach 128 bits.
  • the chip (such as application processor AP chip) package is connected to the pins of the DRAM chip (dynamic random access memory chip) through the through-hole (TIV) array of the package structure for data input and output.
  • the AP chip package structure has A plurality of data channels are used to transmit data, and each data channel includes a plurality of through holes arranged in an array. Taking an AP chip with a 64-bit data channel as an example, each channel includes 16 data signals TIV + 7 CA signals (address signals) TIV, that is, a total of 23 TIVs. Different channels transmit data in the same form, but the transmitted data signals are different. For example, when transmitting data in parallel, one channel transmits the data in the first data packet, and the second channel transmits the data in the second data packet. .
  • the signal vias 20 located in the second side area 12 and the fourth side area 14 are arranged in three rows (there is no special requirement for the specific number of columns. Those skilled in the art can determine the number of columns according to the number of the chip. The size and other actual conditions can be flexibly selected, and there are no restrictions here.)
  • the signal through holes 20 located in the first side area 11 and the third side area 13 are arranged in at least two columns (there are no special requirements for the specific number of rows, and those skilled in the art can Flexible selection is made according to the actual situation such as the size of the chip, and there are no restrictions here).
  • the signal vias 20 located in the first side area 11 and the third side area 13 are arranged in three columns. In this way, the higher memory access bandwidth requirements of the chip can be achieved and the outlet requirements of more signals can be met; if more rows of signal vias are set in the first side area and the third side area, signal via holes will be correspondingly formed. The waste will also occupy more area of the substrate, affecting the routing of the chip substrate and signals; if there are less than three columns, it will be relatively difficult to meet the routing requirements of the signal through holes, which is not conducive to the realization of the chip for higher memory. Access bandwidth requirements.
  • the signal via 20 includes a data input and output terminal signal via (DQ) 21 , wherein two adjacent data input and output terminal signal vias (DQ) located in the same row or column are There is at least one non-data input and output signal through hole between the holes 21 (that is, other signal through holes except the data input and output signal through holes 21).
  • DQ data input and output terminal signal via
  • the data input and output signal through holes 21 in this arrangement can be located at the junction of two adjacent side areas (ie, the junction of the first side area 11 and the second side area 12, the junction of the second side area 12 and the third side area 13,
  • the data input and output signal through holes 21 are arranged at intervals at the junction of the third side area 13 and the fourth side area 14 and at the junction of the fourth side area 14 and the first side area 11 , and may also be located in a certain side area (i.e., the first side area).
  • Area 11, second side area 12, third side area 13 and/or fourth side area 14) in the middle i.e. at the junction of two non-adjacent side areas
  • the input and output signal through holes 21 are located in the middle of a certain side area (i.e., the first side area 11, the second side area 12, the third side area 13 and/or the fourth side area 14) (only the second side area 12 is taken as an example in Figure 1 ).
  • At least one non-data input and output terminal signal through hole (such as a ground terminal) can be provided between two adjacent data input and output terminal signal through holes 21
  • the signal vias (VSS) 22) separate them to avoid crosstalk when transmitting signals between the signal vias 21 of different data input and output terminals that are relatively close to each other.
  • VSS signal vias
  • the junction of the first side area 11 and the second side area 12 includes a plurality of data input and output terminal signal through holes 21 , and the plurality of data input and output terminal signal through holes 21 are spaced apart.
  • Setting that is, there is at least one (take 1 in the figure as an example) non-data input and output signal through hole, such as grounding, between two adjacent data input and output signal through holes 21 located in the same row or column.
  • the junction of the second side area 12 and the third side area 13 includes a plurality of data input and output terminal signal via holes 21, and the plurality of data input and output terminal signal via holes 21 are arranged at intervals, that is, located here There is at least one (one is taken as an example in the figure) non-data input and output signal through holes 21 between two adjacent data input and output signal through holes 21 in the same row or column, such as a ground signal through hole (VSS). )22;
  • the junction of the third side area 13 and the fourth side area 14 includes a plurality of data input and output terminal signal through holes 21.
  • the plurality of data input and output terminal signal through holes 21 are arranged at intervals, that is, the ones located in the same row or the same column are here.
  • non-data input and output signal through hole there is at least one non-data input and output signal through hole (one in the figure is taken as an example) between two adjacent data input and output signal through holes 21, such as a ground signal through hole (VSS) 22; the fourth side area
  • the junction between 14 and the first side area 11 includes a plurality of data input and output signal through holes 21.
  • the plurality of data input and output signal through holes 21 are arranged at intervals, that is, two adjacent data holes 21 are located in the same row or column.
  • non-data input and output signal through hole one is taken as an example in the figure between the input and output signal through holes 21 , such as a ground signal through hole (VSS) 22 .
  • the above non-data input and output terminal signal through holes are arranged in a manner that separates two adjacent data input and output terminal signal through holes 21 located in the same row or the same column, which can effectively reduce the risk of different data input and output at the junction.
  • the signal via 20 includes at least one group of data input and output signal vias S1 , and at least one group of data input and output signal vias S1 includes three adjacent rows and three columns. And there are four data input and output terminal signal through holes 21 arranged in a diamond-shaped structure or a diamond-like structure. Therefore, the above-mentioned setting method is simple and easy to arrange, and can set up a relatively large number of data input and output signal through holes in a small area, effectively realizing more signal outgoing requirements, which in turn helps to exponentially increase the memory of the chip.
  • At least one group of data input and output signal through holes S1 can be located at the edge of the side area, that is, at the junction of two side areas (as shown in Figures 1 to 4), or can be arranged in a certain side area (i.e., the first side area).
  • At least one group of data input and output signal through holes S1 in any side area can be arranged near the middle of the first side area 11; or at least one group of data input and output signal through holes in all side areas.
  • Holes S1 are all set at the junction of two adjacent side areas (as shown in Figures 1 to 3); or at least one group of data input and output signal through holes in any one side area, any two side areas, or any three side areas.
  • S1 is set near the middle, and at least one group of data input and output signal through holes S1 in the remaining side areas is located at the junction of two adjacent side areas.
  • at least one group of data input ports in the second side area 12 The output signal through hole S1 is located in the middle of the side area, and at least one set of data input and output signal through holes S1 in the other three side areas is located at the junction of two adjacent side areas.
  • the signal through holes include a first group of data input and output terminal signal through holes and a second group of data input and output terminal signal through holes.
  • the first group of data input and output terminal signal through holes The data signals used for transmission and the second group of data input and output terminal signal through holes are used for transmitting data signals of different data channels.
  • the first group of data input and output terminal signal through holes include the first data input and output terminal signal through holes 211 and the third data input and output terminal signal through holes.
  • the first data input and output terminal signal through holes 211 and the third data input and output terminal signal through holes 213 are located in the same row, and the second data input and output terminal signal through holes 212 and the fourth data input and output terminal signal through holes 214 are located in the same column.
  • the second data input and output terminal signal through holes 212 and the first data input and output terminal signal through holes 211 are not in the same row, and the second data input and output terminal signal through holes 212 and the third data input and output terminal signal through holes 213 are not in the same row. .
  • the fourth data input and output terminal signal through holes 214 and the first data input and output terminal signal through holes 211 are not in the same row, and the fourth data input and output terminal signal through holes 214 and the third data input and output terminal signal through holes 213 are not in the same row.
  • the second group of data input and output terminal signal through holes includes the fifth data input and output terminal signal through hole 215, the sixth data input and output terminal signal through hole 216, the seventh data input and output terminal signal through hole 217 and the eighth data input and output terminal. Signal via 218.
  • the fifth data input and output terminal signal through hole 215 and the seventh data input and output terminal signal through hole 217 are located in the same row, and the sixth data input and output terminal signal through hole 216 and the eighth data input and output terminal signal through hole 218 are located in the same column.
  • the sixth data input and output terminal signal through hole 216 and the fifth data input and output terminal signal through hole 215 are not in the same row, and the sixth data input and output terminal signal through hole 216 and the seventh data input and output terminal signal through hole 217 are not in the same row. .
  • the eighth data input and output terminal signal through hole 218 and the fifth data input and output terminal signal through hole 215 are not in the same row, and the eighth data input and output terminal signal through hole 218 and the seventh data input and output terminal signal through hole 217 are not in the same row.
  • the above setting method is simple and easy to arrange. It can set up a relatively large number of data input and output signal through holes in a small area, and effectively enlarge the size of two adjacent ones (including two adjacent ones in the same row and the same column). The spacing between two adjacent or diagonally adjacent two data input and output terminal signal through holes 21 can effectively reduce the crosstalk between different data input and output terminal signal through holes 21 at the junction. .
  • the first group of data input and output terminal signal through holes are used to transmit data signals and the second group of data input and output terminal signal through holes are used to transmit data signals of different data channels, that is, the first group of data input terminals is used to transmit data signals.
  • the output signal through holes and the second group of data input and output signal through holes are located in different signal channels.
  • the data input and output signal through holes 214 are located in the same signal channel and can be used to transmit the same data signal or different data signals.
  • the second group Among the data input and output terminal signal through holes, the fifth data input and output terminal signal through hole 215, the sixth data input and output terminal signal through hole 216, the seventh data input and output terminal signal through hole 217 and the eighth data input and output terminal signal through hole.
  • the same signal channel of hole 218 can be used to transmit the same data signal or different data signals.
  • Those skilled in the art can flexibly choose according to the actual situation.
  • the data input and output terminal signal through holes 214 are distributed in three adjacent rows and three columns. In this way, the first data input and output terminal signal through holes 211, the second data input and output terminal signal through holes 212, and the third data input and output terminal signal through holes 214.
  • the connection between the hole 213 and the fourth data input and output terminal signal through hole 214 can form a diamond-shaped structure or a diamond-like structure.
  • the first data input and output terminal signal through hole 211 and the second data input and output terminal The signal through hole 212, the third data input and output terminal signal through hole 213 and the fourth data input and output terminal signal through hole 214 can be arranged counterclockwise or clockwise (counterclockwise is used as an example in the drawing); the fifth data The input and output terminal signal through holes 215, the sixth data input and output terminal signal through holes 216, the seventh data input and output terminal signal through holes 217 and the eighth data input and output terminal signal through holes 218 are distributed in three adjacent rows and three columns.
  • connection of the fifth data input and output terminal signal through hole 215, the sixth data input and output terminal signal through hole 216, the seventh data input and output terminal signal through hole 217 and the eighth data input and output terminal signal through hole 218 can be formed.
  • the data input and output signal through holes 218 can be arranged counterclockwise or clockwise (counterclockwise is used as an example in the figure).
  • the above-mentioned arrangement of multiple data input and output terminal signal through holes can provide a relatively large number of data input and output terminal signal through holes in a small area, and effectively increase the size of two adjacent ones (including the same two rows). Two adjacent ones, two adjacent ones in the same column or two adjacent ones diagonally)
  • This makes the arrangement of signal vias have certain rules, which is easy to set up and identify.
  • the above-mentioned first group of data input and output terminal signal through holes and the second group of data input and output terminal signal through holes are located at the junction of two adjacent side areas, that is, located on the first side.
  • the junction of area 11 and the second side area 12 the junction of the second side area 12 and the third side area 13, the junction of the third side area 13 and the fourth side area 14, and the junction of the fourth side area 14 and the first side area 11
  • the arrangement of the plurality of data input and output signal through holes in the first group of data input and output signal through holes and the second group of data input and output signal through holes can be smaller.
  • a relatively large number of data input and output signal through holes are provided within the area, and two adjacent ones (including two adjacent ones in the same two rows, two adjacent ones in the same column, or two adjacent ones diagonally opposite) are effectively enlarged. Three situations)
  • the spacing between the data input and output terminal signal through holes 21 can effectively reduce the crosstalk of signals. Therefore, when the above-mentioned first group of data input and output terminal signal through holes and the second group of data input and output terminal signal through holes are located At the junction of two adjacent side areas, not only can the crosstalk of signals at the junction of two adjacent side areas be effectively reduced, but a larger number of data input and output signal through holes 21 can also be provided in a limited area to meet more needs.
  • the signals are routed out, which in turn helps to exponentially increase the memory access bandwidth of the chip.
  • the first data input and output terminal signal through hole 211 the second data input and output terminal signal through hole 212, the third data input and output terminal signal through hole 213 and the fourth data input and output terminal signal through hole 211.
  • a ground signal through hole (VSS) 22 is provided in the middle of the data input and output terminal signal through hole 214.
  • the connection between the third data input and output terminal signal through hole 213 and the fourth data input and output terminal signal through hole 214 can form a diamond-shaped structure or a diamond-like structure, and the center of the diamond structure or diamond-like structure has a ground signal through hole ( VSS) 22.
  • VSS ground signal through hole
  • the ground signal through hole (VSS) 22 is provided here, which can effectively reduce the size of the first data input and output terminal signal through hole 211, the second data input and output terminal signal through hole 212, and the third data input and output port.
  • a ground signal through hole (VSS) 22 is provided in the middle of the terminal signal through hole 217 and the eighth data input and output terminal signal through hole 218. That is, as mentioned above, the fifth data input and output terminal signal through hole 215, the sixth data input and output terminal signal through hole 215 and the sixth data input and output terminal signal through hole 218.
  • connection of the input and output terminal signal through holes 216, the seventh data input and output terminal signal through holes 217 and the eighth data input and output terminal signal through holes 218 can form a rhombus structure or a rhombus-like structure, and the center of the rhombus structure or rhombus-like structure There is a ground signal through hole (VSS) 22.
  • the ground signal through hole (VSS) 22 provided here is used for grounding, which is equivalent to setting up signal isolation between the two data input and output signal through holes 21.
  • the structure can better isolate the signals transmitted by the signal through holes 21 of the two data input and output terminals that are close to each other to avoid signal crosstalk, that is, it can effectively reduce the signal through holes 215 of the first and fifth data input and output terminals.
  • the signal through holes at the junction of two adjacent side areas in the packaging structure can be arranged as follows:
  • the first group of data input and output signal through holes are located in the first side area 11 and the third side area 13 (that is, the first side area 11 and the third side area 13 are both provided with There is at least one first group of data input and output terminal signal through holes.
  • Two are taken as an example in Figure 2.
  • a first group of data input and output terminal signals are respectively provided at both ends of the first side area 11 and both ends of the third side area 13.
  • through holes the second group of data input and output terminal signal through holes are located in the second side area 12 and the fourth side area 14 (that is to say, the second side area 12 and the fourth side area 14 are both provided with at least one second group of data input and output terminal signals.
  • Through holes two are taken as an example in Figure 2.
  • a second group of data input and output signal through holes are respectively provided at both ends of the second side area 12 and both ends of the fourth side area 14), wherein the first data input and output The terminal signal through hole 211, the third data input and output terminal signal through hole 213 and the eighth data input and output terminal signal through hole 218 are located in the same row, and the second data input and output terminal signal through hole 212 and the fifth data input and output terminal signal through hole 212 are arranged in the same row.
  • the through holes 215 and the seventh data input and output terminal signal through holes 217 are located in the same row. Any one of the data input and output terminal signal through holes 21 in the first group of data input and output terminal signal through holes is the same as the second group of data input and output terminal signal through holes.
  • two ground signal through holes (VSS) 22 are provided between the second data input and output terminal signal through hole 212 and the fifth data input and output terminal signal through hole 215, and the third data input and output terminal signal through hole 213 is connected to the third data input and output terminal signal through hole 213.
  • Two power supply signal through holes (VDD) 24 are provided between the eight data input and output terminal signal through holes 218.
  • the ground terminal signal through hole (VSS) 22 provided here is used for grounding, which is equivalent to providing a signal isolation structure between the two data input and output terminal signal through holes 21, which can better isolate the two data input and output terminals.
  • the signals transmitted by the data input and output terminal signal through holes 21 are isolated to avoid signal crosstalk, that is, the number of signals in the first group of data input and output terminal signal through holes and the second group of data input and output terminal signal through holes can be further effectively reduced.
  • Crosstalk of signals between the data input and output terminal signal through holes 21; the setting of the power supply terminal signal through hole (VDD) 24 can connect the third data input and output terminal signal through hole 213 and the eighth data input and output terminal signal through hole 218 The distance between them is increased to avoid the undesirable phenomenon of signal crosstalk when transmitting signals.
  • the first row of the first side area 11 (that is, the row where the sixth data input and output terminal signal through hole 216 is located)
  • Three ground signal vias (VSS) 22 may also be provided in the row where the sixth data input and output terminal signal vias 216 are located, and there are also between the sixth data input and output terminal signal vias 216 and the first side area 11
  • Two ground signal through holes (VSS) 22 can also be further provided. In this way, the ground signal through holes (VSS) 22 are used for grounding, which is equivalent to setting up signal isolation between the two data input and output signal through holes 21.
  • the structure can better isolate the signals transmitted by the signal through holes 21 of the two data input and output terminals that are close to each other, and can further effectively reduce the crosstalk of the signals between the signal through holes 21 of the multiple data input and output terminals.
  • the junctions of other two adjacent side areas can also be arranged as described above, in order to better reduce the crosstalk of signals between the multiple data input and output terminal signal through holes 21. The specific details are not too many. description of.
  • the first group of data input and output signal through holes are located in the first side area 11 and the third side area 13 (that is, the first side area 11 and the third side area 13 are both At least one first group of data input and output terminal signal through holes are provided.
  • Two are taken as an example in Figure 3.
  • One first group of data input and output ports are respectively provided at both ends of the first side area 11 and both ends of the third side area 13. terminal signal through holes)
  • the second group of data input and output terminal signal through holes are located in the second side area 12 and the fourth side area 14 (that is to say, the second side area 12 and the fourth side area 14 are both provided with at least one second group of data input Output signal through holes, two are taken as an example in Figure 3.
  • a second set of data input and output signal through holes are respectively provided at both ends of the second side area 12 and both ends of the fourth side area 14), wherein the second The data input and output terminal signal through holes 212 and the eighth data input and output terminal signal through holes 218 are located in the same row. Any data input and output terminal signal through holes 21 in the first group of data input and output terminal signal through holes are in the same row as the second group of data input and output terminal signal through holes 218 . None of the data input and output signal through holes 21 belongs to the same column, and the fifth data input and output signal through hole 215 and the third data input and output signal through hole 213 are located adjacent to each other.
  • VDD power supply signal through holes
  • the power terminal signal through hole (VDD) 24 provided here can widen the distance between the third data input and output terminal signal through hole 213 and the eighth data input and output terminal signal through hole 218, thereby preventing their transmission.
  • the undesirable phenomenon of signal crosstalk occurs when the signal is transmitted, that is to say, the setting of the power supply signal through hole (VDD) 24 can further effectively reduce the signal through holes of the first group of data input and output terminals and the signal of the second group of data input and output terminals. Crosstalk of signals between multiple data input and output terminal signal through holes 21 in the through holes.
  • the first row of the first side area 11 (that is, the row where the sixth data input and output terminal signal through hole 216 is located) and the second row (that is, the row where the fifth data input and output terminal signal through holes 216 are located) can also be provided with three ground signal through holes (VSS) 22 respectively, and the row where the sixth data input and output terminal signal through holes 216 are located, Moreover, a ground signal through hole (VSS) 22 can also be further provided between the sixth data input and output terminal signal through hole 216 and the first side area 11. In this way, the above ground signal through hole (VSS) 22 is provided to ground.
  • the terminal signal through hole (VSS) 22 is used for grounding, which is equivalent to setting a signal isolation structure between the two data input and output terminal signal through holes 21, which can better connect the signals of the two data input and output terminals that are close to each other.
  • the signals transmitted by the holes 21 are isolated, which can further effectively reduce the crosstalk of signals between the multiple data input and output terminal signal through holes 21 .
  • the junctions of other two adjacent side areas can also be arranged as described above, in order to better reduce the crosstalk of signals between the multiple data input and output terminal signal through holes 21. The specific details are not too many. description of.
  • the first group of data input and output signal through holes are located in the first side area 11 and the third side area 13 (that is, the first side area 11 and the third side area 13 are both At least one first group of data input and output terminal signal through holes are provided.
  • Two are taken as an example in Figure 4.
  • One first group of data input and output ports are respectively provided at both ends of the first side area 11 and both ends of the third side area 13.
  • the fifth data input and output end signal through hole 215 in the second group of data input and output end signal through holes is located in the second side area 12 and the fourth side area 14, and the second group of data input and output end signal through holes
  • the sixth data input and output terminal signal through hole 216, the seventh data input and output terminal signal through hole 217 and the eighth data input and output terminal signal through hole 218 are located in the second side area 12 and the fourth side area 14, wherein the third data input The output signal through hole 213 and the fifth data input and output signal through hole 215 are located in the same column.
  • Any data input and output signal through hole 21 in the first group of data input and output signal through holes is in the same row as the second group of data input and output signal through holes.
  • the signals transmitted by the data input and output terminal signal through holes 21 are isolated to avoid signal crosstalk, that is, the number of signals in the first group of data input and output terminal signal through holes and the second group of data input and output terminal signal through holes can be further effectively reduced.
  • Crosstalk of signals between the data input and output terminal signal through holes 21; the setting of the power supply terminal signal through hole (VDD) 24 can connect the third data input and output terminal signal through hole 213 and the eighth data input and output terminal signal through hole 218 The distance between them is increased to avoid the undesirable phenomenon of signal crosstalk when transmitting signals.
  • the second data input and output terminal signal through hole 212 is located in the column and above it.
  • Three ground signal through holes (VSS) 22 are provided, as well as the column where the first data input and output signal through hole 211 is located, and three ground signal through holes (VSS) 22 can be provided above it, as well as a fifth data input and output.
  • a ground signal through hole (VSS) 22 can be provided in the column where the terminal signal through hole 215 is located and above it. In this way, the above ground terminal signal through hole (VSS) 22 is used for grounding, which is equivalent to two data input and output terminals.
  • a signal isolation structure is set up between the signal through holes 21, which can better isolate the signals transmitted by the two data input and output terminal signal through holes 21 that are close to each other and avoid signal crosstalk, that is, the ground signal through hole (VSS)
  • the arrangement of 22 can further effectively reduce the crosstalk of signals between the multiple data input and output terminal signal through holes 21 .
  • the junctions of other two adjacent side areas can also be arranged as described above, in order to better reduce the crosstalk of signals between the multiple data input and output terminal signal through holes 21. The specific details are not too many. description of.
  • the arrangement of signal through holes of the data input and output terminals in the three specific embodiments listed above can be set in the same packaging structure, that is, at the junction of the first side area 11 and the second side area 12
  • the arrangement of the input and output signal through holes 21 and the arrangement of the data input and output signal through holes 21 at the junction of the fourth side area 14 and the first side area 11 can be the same (as shown in Figure 2 to Figure 4), or they can be different.
  • the present application provides a processor chip.
  • the processor chip 1000 includes the previously described packaging structure 1100 .
  • the processor chip further includes a surface disposed on the surface of the packaging structure 1100
  • the plurality of storage particles 1200 and the plastic sealing layer 1300 located on the side of the storage particles 1200 away from the packaging structure 1100 can provide good protection for the storage particles 1200 and the packaging structure 1100 .
  • the processor chip can achieve exponentially increased memory access bandwidth.
  • the memory access bandwidth of a processor chip using this packaging structure can reach 128 bits.
  • the above-mentioned plastic sealing layer 1300 may be epoxy resin or other plastic sealing materials suitable for chip packaging.
  • the processor chip is an application processor chip (AP chip).
  • the present application provides a POP packaging component.
  • the POP package component 1 includes: the aforementioned processor chip 1000; and a first chip 2000 vertically stacked and packaged with the processor chip 1000.
  • the POP package component has a front processor chip and can achieve exponentially increased memory access bandwidth.
  • the memory access bandwidth of a processor chip using this packaging structure can reach 128 bits.
  • the above-mentioned first chip may be a DRAM chip (dynamic random access memory chip), and the processor chip and the DRAM chip are vertically stacked and packaged to form a POP package component.
  • DRAM chip dynamic random access memory chip
  • the processor chip and the DRAM chip are vertically stacked and packaged to form a POP package component.
  • the present application provides an electronic device.
  • the electronic device includes the aforementioned processor chip. As a result, the electronic device has better performance.
  • the specific types of electronic devices include but are not limited to mobile phones, iPads, computers, TVs and other electronic devices that can apply processor chips. .
  • first and second in this article are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of this application, “plurality” means two or more than two, unless otherwise explicitly and specifically limited.
  • references to the terms “one embodiment,” “some embodiments,” “an example,” “specific examples,” or “some examples” or the like means that specific features are described in connection with the embodiment or example. , structures, materials or features are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine different embodiments or examples and features of different embodiments or examples described in this specification unless they are inconsistent with each other.

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Abstract

A package structure, a processor chip, a POP package assembly and an electronic device. The package structure comprises a substrate, wherein the substrate has a peripheral area, which comprises first through fourth peripheral areas that are sequentially connected; signal through holes arranged in multiple rows and multiple columns are distributed in each of the first through fourth peripheral areas; and conductors are provided in the signal through holes. Signal through holes arranged in multiple rows and multiple columns are provided in each peripheral area of a substrate, such that more signal lines are led out, thereby being conducive to multiplying the data access bandwidth for a processor.

Description

封装结构、处理器芯片、POP封装组件和电子设备Packaging structures, processor chips, POP packaging components and electronic equipment
优先权信息priority information
[根据细则91更正 13.06.2023]
本申请请求2022年05月12日向中国国家知识产权局提交的、专利申请号为2022105210246的专利申请以及2023年05月11日向中国国家知识产权局提交的、专利申请号为202310533654X的专利申请的优先权和权益,并且通过参照将其全文并入此处。
[Correction 13.06.2023 under Rule 91]
This application requests priority for the patent application with patent application number 2022105210246 submitted to the State Intellectual Property Office of China on May 12, 2022, and the patent application with patent application number 202310533654X submitted to the State Intellectual Property Office of China on May 11, 2023. rights and interests, and is incorporated herein by reference in its entirety.
技术领域Technical field
本申请涉及芯片技术领域,具体的,涉及封装结构、处理器芯片、POP封装组件和电子设备。This application relates to the field of chip technology, specifically to packaging structures, processor chips, POP packaging components and electronic equipment.
背景技术Background technique
低功耗双倍速率同步动态随机存储器(Low Power Double Data Rate SDRAM,LPDDR)已被广泛应用于各类电子设备中,尤其是电源受限的移动设备中。用于LPDDR传统的JEDEC(固态电路技术协会)496ball POP(垂直堆叠式封装)pinmap(芯片引脚图)只能在DRAM芯片(动态随机存储器芯片)的封装上提供4个访问通道。例如,LPDDR芯片现有的针对POP类型封装的pinmap总共有3种,分别是针对LPDDR4的MO-273、MO-317A以及针对LPDDR5的MO-344,这3种pinmap对应的DRAM封装尺寸分别是15mm*15mm、14mm*14mm以及14mm*12.4mm。可是这3种pinmap均只提供了4个DRAM通道,最高也仅仅能支持64bits的数据带宽。Low Power Double Rate Synchronous Dynamic Random Access Memory (LPDDR) has been widely used in various electronic devices, especially in power-constrained mobile devices. The traditional JEDEC (Solid State Circuit Technology Association) 496ball POP (vertically stacked package) pinmap (chip pinmap) for LPDDR can only provide 4 access channels on the package of DRAM chip (dynamic random access memory chip). For example, there are currently three pinmaps for LPDDR chips for POP type packaging, namely MO-273 and MO-317A for LPDDR4 and MO-344 for LPDDR5. The DRAM package sizes corresponding to these three pinmaps are 15mm. *15mm, 14mm*14mm and 14mm*12.4mm. However, these three pinmaps only provide 4 DRAM channels, and can only support a maximum data bandwidth of 64bits.
发明内容Contents of the invention
在本申请的一方面,本申请提供了一种封装结构。根据本申请的实施例,该封装结构包括:基板,所述基板具有周边区,所述周边区包括依次相连的第一边区、第二边区、第三边区和第四边区,所述第一边区、所述第二边区、所述第三边区和所述第四边区具有呈多行多列设置的信号通孔,所述信号通孔中设置有铜柱。In one aspect of the present application, the present application provides a packaging structure. According to an embodiment of the present application, the packaging structure includes: a substrate having a peripheral area, the peripheral area including a first side area, a second side area, a third side area and a fourth side area connected in sequence, the first side area being The side area, the second side area, the third side area and the fourth side area have signal through holes arranged in multiple rows and columns, and copper pillars are provided in the signal through holes.
在本申请的另一方面,本申请提供了一种处理器芯片。根据本申请的实施例,该处理器芯片包括封装结构。该封装结构包括:基板,所述基板具有周边区,所述周边区包括依次相连的第一边区、第二边区、第三边区和第四边区,所述第一边区、所述第二边区、所述第三边区和所述第四边区具有呈多行多列设置的信号通孔,所述信号通孔中设置有铜柱。In another aspect of the present application, the present application provides a processor chip. According to an embodiment of the present application, the processor chip includes a packaging structure. The packaging structure includes: a substrate, the substrate has a peripheral area, the peripheral area includes a first side area, a second side area, a third side area and a fourth side area connected in sequence, the first side area, the second side area The side area, the third side area and the fourth side area have signal through holes arranged in multiple rows and columns, and copper pillars are provided in the signal through holes.
在本申请的另一方面,本申请提供了一种POP封装组件。根据本申请的实施例,该POP封装组件包括:处理器芯片以及与所述处理器芯片垂直堆叠封装的第一芯片。该处理器芯片包括封装结构。该封装结构包括:基板,所述基板具有周边区,所述周边区包括依次相连的第一边区、第二边区、第三边区和第四边区,所述第一边区、所述第二边区、所述第三边区和所述第四边区具有呈多行多列设置的信号通孔,所述信号通孔中设置有铜柱。In another aspect of the present application, the present application provides a POP packaging component. According to an embodiment of the present application, the POP package component includes: a processor chip and a first chip that is vertically stacked and packaged with the processor chip. The processor chip includes a package structure. The packaging structure includes: a substrate, the substrate has a peripheral area, the peripheral area includes a first side area, a second side area, a third side area and a fourth side area connected in sequence, the first side area, the second side area The side area, the third side area and the fourth side area have signal through holes arranged in multiple rows and columns, and copper pillars are provided in the signal through holes.
在本申请的另一方面,本申请提供了一种电子设备。根据本申请的实施例,该电子设备包括前面所述的处理器芯片。该处理器芯片包括封装结构。该封装结构包括:基板,所述基板具有周边区,所述周边区包括依次相连的第一边区、第二边区、第三边区和第四边区,所述第一边区、所述第二边区、所述第三边区和所述第四边区具有呈多行多列设置的信号通孔,所述信号通孔中设置有铜柱。In another aspect of the present application, the present application provides an electronic device. According to an embodiment of the present application, the electronic device includes the aforementioned processor chip. The processor chip includes a package structure. The packaging structure includes: a substrate, the substrate has a peripheral area, the peripheral area includes a first side area, a second side area, a third side area and a fourth side area connected in sequence, the first side area, the second side area The side area, the third side area and the fourth side area have signal through holes arranged in multiple rows and columns, and copper pillars are provided in the signal through holes.
附图说明Description of the drawings
本申请的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解,其中:The above and/or additional aspects and advantages of the present application will become apparent and readily understood from the description of the embodiments in conjunction with the following drawings, in which:
图1是本申请一个实施例中封装结构的示意图;Figure 1 is a schematic diagram of the packaging structure in one embodiment of the present application;
图2是本申请另一个实施例中封装结构的示意图;Figure 2 is a schematic diagram of a packaging structure in another embodiment of the present application;
图3是本申请又一个实施例中封装结构的示意图;Figure 3 is a schematic diagram of the packaging structure in yet another embodiment of the present application;
图4是本申请又一个实施例中封装结构的示意图;Figure 4 is a schematic diagram of the packaging structure in yet another embodiment of the present application;
图5是本申请又一个实施例中处理器芯片的示意图;Figure 5 is a schematic diagram of a processor chip in another embodiment of the present application;
图6是本申请又一个实施例中POP封装组件的示意图。Figure 6 is a schematic diagram of a POP packaging component in yet another embodiment of the present application.
具体实施方式Detailed ways
下面将结合实施例对本申请的方案进行解释。本领域技术人员将会理解,下面的实施例仅用于说明本申请,而不应视为限定本申请的范围。实施例中未注明具体技术或条件的,按照本领域内的文献所描述的技术或条件或者按照产品说明书进行。The solution of the present application will be explained below with reference to examples. Those skilled in the art will understand that the following examples are only used to illustrate the present application and should not be regarded as limiting the scope of the present application. If specific techniques or conditions are not specified in the examples, the techniques or conditions described in literature in the field or product instructions will be followed.
下面参考具体实施例,对本申请进行描述,需要说明的是,这些实施例仅仅是描述性的,而不以任何方式限制本申请。The present application will be described below with reference to specific embodiments. It should be noted that these embodiments are only descriptive and do not limit the present application in any way.
在本申请的一方面,本申请提供了一种封装结构。根据本申请的实施例,参照图1至图4,该封装结构包括:基板10,所述基板10具有周边区,周边区包括依次相连的第一边区11、第二边区12、第三边区13和第四边区14,第一边区11、第二边区12、第三边区13和第四边区14具有呈多行多列设置的信号通孔20,信号通孔20中设置有导体。在一个实施例中,导体可以是铜柱,或本领域已知的其它导体材料。由此,封装结构通过在基板10四边的周边区均设置多行多列的信号通孔20,从而可以满足更多信号的出线要求,进而有助于成倍提升芯片的存储器访问带宽。作为一个非限制性示例,采用该封装结构的芯片的存储器访问带宽可达到128bits。In one aspect of the present application, the present application provides a packaging structure. According to an embodiment of the present application, with reference to Figures 1 to 4, the packaging structure includes: a substrate 10, the substrate 10 has a peripheral area, and the peripheral area includes a first side area 11, a second side area 12, and a third side area that are connected in sequence. 13 and the fourth side area 14, the first side area 11, the second side area 12, the third side area 13 and the fourth side area 14 have signal via holes 20 arranged in multiple rows and columns, and conductors are arranged in the signal via holes 20. In one embodiment, the conductors may be copper posts, or other conductive materials known in the art. Therefore, the packaging structure can meet the outlet requirements of more signals by arranging multiple rows and columns of signal through holes 20 in the peripheral areas on all four sides of the substrate 10 , thereby doubling the memory access bandwidth of the chip. As a non-limiting example, the memory access bandwidth of a chip using this packaging structure can reach 128 bits.
需要说明的是,芯片(比如应用处理器AP芯片)封装通过封装结构的通孔(TIV)阵列连接到DRAM芯片(动态随机存储芯片)的管脚以进行数据输入和输出,AP芯片封装结构具有多个用于传输数据的数据通道,每个数据通道包括以阵列设置的多个通孔。以具有64bit的数据通道的AP芯片为例,每个通道包括16个数据信号TIV+7个CA信号(地址信号)TIV,即,共计23个TIV。不同的通道传输的数据的形式一样,但是传输的数据信号不同,比如,当并行传输数据时,一个通道传输第一个数据包中的数据,第二个通道传输第二个数据包中的数据。It should be noted that the chip (such as application processor AP chip) package is connected to the pins of the DRAM chip (dynamic random access memory chip) through the through-hole (TIV) array of the package structure for data input and output. The AP chip package structure has A plurality of data channels are used to transmit data, and each data channel includes a plurality of through holes arranged in an array. Taking an AP chip with a 64-bit data channel as an example, each channel includes 16 data signals TIV + 7 CA signals (address signals) TIV, that is, a total of 23 TIVs. Different channels transmit data in the same form, but the transmitted data signals are different. For example, when transmitting data in parallel, one channel transmits the data in the first data packet, and the second channel transmits the data in the second data packet. .
根据本申请的实施例,参照图1至图4,位于第二边区12和第四边区14的信号通孔20呈三行排布(具体列数没有特殊要求,本领域技术人员可以根据芯片的尺寸大小等实际情况灵活选择,在此不作限制要求),位于第一边区11和第三边区13的信号通孔20呈至少两列排布(具体行数没有特殊要求,本领域技术人员可以根据芯片的尺寸大小等实际情况灵活选择,在此不作限制要求)。在一些优选具体实施例中,位于第一边区11和第三边区13的信号通孔20呈三列排布。如此,即可以实现芯片的更高存储器访问带宽的要求,满足更多信号的出线要求;若是在第一边区和第三边区设置更多列的信号通孔,则会相应的造成信号通孔的浪费,同时也会侵占基板的更多面积,影响芯片基板与信号的出线;若是少于三列,则会相对的较难满足信号通孔的出线要求,不利于实现芯片的对于更高存储器访问带宽的要求。According to the embodiment of the present application, with reference to FIGS. 1 to 4 , the signal vias 20 located in the second side area 12 and the fourth side area 14 are arranged in three rows (there is no special requirement for the specific number of columns. Those skilled in the art can determine the number of columns according to the number of the chip. The size and other actual conditions can be flexibly selected, and there are no restrictions here.) The signal through holes 20 located in the first side area 11 and the third side area 13 are arranged in at least two columns (there are no special requirements for the specific number of rows, and those skilled in the art can Flexible selection is made according to the actual situation such as the size of the chip, and there are no restrictions here). In some preferred embodiments, the signal vias 20 located in the first side area 11 and the third side area 13 are arranged in three columns. In this way, the higher memory access bandwidth requirements of the chip can be achieved and the outlet requirements of more signals can be met; if more rows of signal vias are set in the first side area and the third side area, signal via holes will be correspondingly formed. The waste will also occupy more area of the substrate, affecting the routing of the chip substrate and signals; if there are less than three columns, it will be relatively difficult to meet the routing requirements of the signal through holes, which is not conducive to the realization of the chip for higher memory. Access bandwidth requirements.
根据本申请的实施例,参照图1至图4,信号通孔20包括数据输入输出端信号通孔(DQ)21,其中,位于同一行或同一列的相邻两个数据输入输出端信号通孔21之间具有至少一个非数据输入输出端信号通孔(即除了据输入输出端信号通孔21的其他信号通孔)。According to an embodiment of the present application, referring to FIGS. 1 to 4 , the signal via 20 includes a data input and output terminal signal via (DQ) 21 , wherein two adjacent data input and output terminal signal vias (DQ) located in the same row or column are There is at least one non-data input and output signal through hole between the holes 21 (that is, other signal through holes except the data input and output signal through holes 21).
进一步的,在一些实施例中,参照图1~图4,上述位于同一行或同一列的相邻两个数据输入输出端信号通孔21之间具有至少一个非数据输入输出端信号通孔,该设置方式的数据输入输出端信号通孔21可以位于相邻两个边区交界处(即第一边区11与第二边区12的交界处、第二边区12与第三边区13的交界处、第三边区13与第四边区14的交界处以及第四边区14与第一边区11的交界处)的数据输入输出端信号通孔21间隔设置,也可以位于某一边区(即第一边区11、第二边区12、第三边区13和/或第四边区14)中间位置(即非相邻两个边区交界处),具体的如下:Further, in some embodiments, referring to Figures 1 to 4, there is at least one non-data input and output signal through hole between the two adjacent data input and output signal through holes 21 located in the same row or column, The data input and output signal through holes 21 in this arrangement can be located at the junction of two adjacent side areas (ie, the junction of the first side area 11 and the second side area 12, the junction of the second side area 12 and the third side area 13, The data input and output signal through holes 21 are arranged at intervals at the junction of the third side area 13 and the fourth side area 14 and at the junction of the fourth side area 14 and the first side area 11 , and may also be located in a certain side area (i.e., the first side area). Area 11, second side area 12, third side area 13 and/or fourth side area 14) in the middle (i.e. at the junction of two non-adjacent side areas), the details are as follows:
在一些具体实施例中,参照图1,上述位于同一行或同一列的相邻两个数据输入输出端信号通孔21之间具有至少一个非数据输入输出端信号通孔,该设置方式的数据输入输出端信号通孔21位于某一边区(即第一边区11、第二边区12、第三边区13和/或第四边区14)中间位置(图1中仅仅以第二边区12为例)。由此,无论数据输入输出端信号通孔21位于什么位置,均可以通过在相邻两个数据输入输出端信号通孔21之间设置至少一个非数据输入输出端信号通孔(比如为接地端信号通孔(VSS)22)将其进行隔开,进而避免距离较近的不同数据输入输出端信号通孔21之间传输信号时的串扰。本领域技术人员可以理解,图4中仅仅以上述设置方式的数据输入输出端信号通孔21位于第二边区12中间某位置为例,第一边区11、第三边区13和第四边区14中的上述设置方式的至少部分数据输入输出端信号通孔21位于相邻两个边区的交界处。当然,本领域技术人员可以选择将所有的上述设置要求的数据输入输出端信号通孔21均设置在第一边区11的中间位置、第二边区12的中间位置、第三边区13的中间位置以及第四边区14的中间位置,或者其中一个边区、任两个边区或任三个边区的中间位置。In some specific embodiments, referring to FIG. 1 , there is at least one non-data input and output signal through hole between the two adjacent data input and output signal through holes 21 located in the same row or column. The data in this arrangement is The input and output signal through holes 21 are located in the middle of a certain side area (i.e., the first side area 11, the second side area 12, the third side area 13 and/or the fourth side area 14) (only the second side area 12 is taken as an example in Figure 1 ). Therefore, no matter where the data input and output terminal signal through holes 21 are located, at least one non-data input and output terminal signal through hole (such as a ground terminal) can be provided between two adjacent data input and output terminal signal through holes 21 The signal vias (VSS) 22) separate them to avoid crosstalk when transmitting signals between the signal vias 21 of different data input and output terminals that are relatively close to each other. Those skilled in the art can understand that in FIG. 4 , only the data input and output terminal signal through hole 21 in the above arrangement is located somewhere in the middle of the second side area 12 as an example. The first side area 11 , the third side area 13 and the fourth side area 14 In the above arrangement, at least part of the data input and output signal through holes 21 are located at the junction of two adjacent side areas. Of course, those skilled in the art can choose to arrange all the data input and output signal through holes 21 required by the above settings at the middle position of the first side area 11 , the middle position of the second side area 12 , and the middle position of the third side area 13 And the middle position of the fourth side area 14, or the middle position of one side area, any two side areas, or any three side areas.
在另一些具体实施例中,如图2所示,第一边区11与第二边区12的交界处包括多个数据输入输出端信号通孔21,多个数据输入输出端信号通孔21间隔设置,即此处位于同一行或同一列的相邻两个数据输入输出端信号通孔21之间具有至少一个(图中以1个为例)非数据输入输出端信号通孔,比如为接地端信号通孔(VSS)22;第二边区12与第三边区13的交界处包括多个数据输入输出端信号通孔21,多个数据输入输出端信号通孔21间隔设置,即此处位于同一行或同一列的相邻两个数据输入输出端信号通孔21之间具有至少一个(图中以1个为例)非数据输入输出端信号通孔,比如为接地端信号通孔(VSS)22;第三边区13与第四边区14的交界处包括多个数据输入输出端信号通孔21,多个数据输入输出端信号通孔21间隔设置,即此处位于同一行或同一列的相邻两个数据输入输出端信号通孔21之间具有至少一个(图中以1个为例)非数据输入输出端信号通孔,比如为接地端信号通孔(VSS)22;第四边区14与第一边区11的交界处包括多个数据输入输出端信号通孔21,多个数据输入输出端信号通孔21间隔设置,即此处位于同一行或同一列的相邻两个数据输入输出端信号通孔21之间具有至少一个(图中以1个为例)非数据输入输出端信号通孔,比如为接地端信号通孔(VSS)22。由此,上述非数据输入输出端信号通孔的设置方式可以将位于同一行或同一列的相邻两个数据输入输出端信号通孔21隔开,可以有效的降低在交界处不同数据输入输出端信号通孔21之间的串扰。In other specific embodiments, as shown in FIG. 2 , the junction of the first side area 11 and the second side area 12 includes a plurality of data input and output terminal signal through holes 21 , and the plurality of data input and output terminal signal through holes 21 are spaced apart. Setting, that is, there is at least one (take 1 in the figure as an example) non-data input and output signal through hole, such as grounding, between two adjacent data input and output signal through holes 21 located in the same row or column. terminal signal via (VSS) 22; the junction of the second side area 12 and the third side area 13 includes a plurality of data input and output terminal signal via holes 21, and the plurality of data input and output terminal signal via holes 21 are arranged at intervals, that is, located here There is at least one (one is taken as an example in the figure) non-data input and output signal through holes 21 between two adjacent data input and output signal through holes 21 in the same row or column, such as a ground signal through hole (VSS). )22; The junction of the third side area 13 and the fourth side area 14 includes a plurality of data input and output terminal signal through holes 21. The plurality of data input and output terminal signal through holes 21 are arranged at intervals, that is, the ones located in the same row or the same column are here. There is at least one non-data input and output signal through hole (one in the figure is taken as an example) between two adjacent data input and output signal through holes 21, such as a ground signal through hole (VSS) 22; the fourth side area The junction between 14 and the first side area 11 includes a plurality of data input and output signal through holes 21. The plurality of data input and output signal through holes 21 are arranged at intervals, that is, two adjacent data holes 21 are located in the same row or column. There is at least one non-data input and output signal through hole (one is taken as an example in the figure) between the input and output signal through holes 21 , such as a ground signal through hole (VSS) 22 . Therefore, the above non-data input and output terminal signal through holes are arranged in a manner that separates two adjacent data input and output terminal signal through holes 21 located in the same row or the same column, which can effectively reduce the risk of different data input and output at the junction. Crosstalk between terminal signal vias 21.
根据本发明的实施例,参照图1,信号通孔20包括至少一组数据输入输出端信号通孔S1,至少一组数据输入输出端信号通孔S1包括分布在相邻的三行和三列且呈菱形结构或似菱形结构排布的四个数据输入输出端信号通孔21。由此,上述设置方式简单易排布,且可以在较小的面积内设置相对较多的数据输入输出端信号通孔,有效实现更多信号出线要求,进而有助于成倍提升芯片的存储器访问带宽,同时有效加大相邻两个(包括同两行的相邻两个、同列的相邻两个或斜对角的相邻两个三种情况)数据输入输出端信号通孔21之间的间距,进而可以更有效的降低在交界处不同数据输入输出端信号通孔21之间的串扰。其中,至少一组的数据输入输出端信号通孔S1可以位于边区的边缘处,即相连两个边区的交界处(如图1~图4),也可以设置在某一边区(即第一边区11、第二边区12、第三边区13和/或第四边区14)中间位置(如图1中的第二边区12),本领域技术人员根据实际需求灵活设置即可。换句话说:任一边区中的至少一组的数据输入输出端信号通孔S1均可设置在第一边区11的靠近中间的位置;或者所有边区中的至少一组数据输入输出端信号通孔S1均设置在位于相邻两个边区的交界处(如图1至图3);或者其中任一个边区、任两个边区或任三个边区中的至少一组数据输入输出端信号通孔S1设置在靠近中间的位置,其余边区中的至少一组数据输入输出端信号通孔S1位于相邻两个边区的交界处,以图1为例,第二边区12中的至少一组数据输入输出端信号通孔S1位于边区中间位置,其他三个边区中的至少一组数据输入输出端信号通孔S1位于相邻两个边区的交界处。According to an embodiment of the present invention, referring to FIG. 1 , the signal via 20 includes at least one group of data input and output signal vias S1 , and at least one group of data input and output signal vias S1 includes three adjacent rows and three columns. And there are four data input and output terminal signal through holes 21 arranged in a diamond-shaped structure or a diamond-like structure. Therefore, the above-mentioned setting method is simple and easy to arrange, and can set up a relatively large number of data input and output signal through holes in a small area, effectively realizing more signal outgoing requirements, which in turn helps to exponentially increase the memory of the chip. Access bandwidth, while effectively increasing the signal through holes 21 between two adjacent data input and output ends (including two adjacent ones in the same row, two adjacent ones in the same column, or two adjacent ones diagonally). The spacing between them can more effectively reduce the crosstalk between the signal through holes 21 of different data input and output terminals at the junction. Among them, at least one group of data input and output signal through holes S1 can be located at the edge of the side area, that is, at the junction of two side areas (as shown in Figures 1 to 4), or can be arranged in a certain side area (i.e., the first side area). area 11, the second side area 12, the third side area 13 and/or the fourth side area 14) in the middle position (the second side area 12 in Figure 1), those skilled in the art can flexibly set it according to actual needs. In other words: at least one group of data input and output signal through holes S1 in any side area can be arranged near the middle of the first side area 11; or at least one group of data input and output signal through holes in all side areas. Holes S1 are all set at the junction of two adjacent side areas (as shown in Figures 1 to 3); or at least one group of data input and output signal through holes in any one side area, any two side areas, or any three side areas. S1 is set near the middle, and at least one group of data input and output signal through holes S1 in the remaining side areas is located at the junction of two adjacent side areas. Taking Figure 1 as an example, at least one group of data input ports in the second side area 12 The output signal through hole S1 is located in the middle of the side area, and at least one set of data input and output signal through holes S1 in the other three side areas is located at the junction of two adjacent side areas.
根据本申请的实施例,参照图1至图4,信号通孔包括第一组数据输入输出端信号通孔和第二组数据输入输出端信号通孔,第一组数据输入输出端信号通孔用于传输的数据信号和第二组数据输入输出端信号通孔用于传输不同数据通道的数据信号,第一组数据输入输出端信号通孔包括第一数据输入输出端信号通孔211、第二数据输入输出端信号通孔212、第三数据输入输出端信号通孔213和第四数据输入输出端信号通孔214。第一数据输入输出端信号通孔211和第三数据输入输出端信号通孔213位于同一行,第二数据输入输出端信号通孔212和第四数据输入输出端信号通孔214位于同一列。第二数据输入输出端信号通孔212与第一数据输入输出端信号通孔211不在同一行,第二数据输入输出端信号通孔212与第三数据输入输出端信号通孔213也不在同一行。第四数据输入输出端信号通孔214与第一数据输入输出端信号通孔211不在同一行,第四数据输入输出端信号通孔214与第三数据输入输出端信号通孔213也不在同一行。第二组数据输入输出端信号通孔包括第五数据输入输出端信号通孔215、第六数据输入输出端信号通孔216、第七数据输入输出端信号通孔217和第八数据输入输出端信号通孔218。第五数据输入输出端信号通孔215和第七数据输入输出端信号通孔217位于同一行,第六数据输入输出端信号通孔216和第八数据输入输出端信号通孔218位于同一列。第六数据输入输出端信号通孔216与第五数据输入输出端信号通孔215不在同一行,第六数据输入输出端信号通孔216与第七数据输入输出端信号通孔217也不在同一行。第八数据输入输出端信号通孔218与第五数据输入输出端信号通孔215不在同一行,第八数据输入输出端信号通孔218与第七数据输入输出端信号通孔217也不在同一行。上述设置方式简单易排布,可以在较小的面积内设置相对较多的数据输入输出端信号通孔,且有效加大相邻两个(包括同两行的相邻两个、同列的相邻两个或斜对角的相邻两个三种情况)数据输入输出端信号通孔21之间的间距,进而可以有效地降低在交界处不同数据输入输出端信号通孔21之间的串扰。According to an embodiment of the present application, with reference to Figures 1 to 4, the signal through holes include a first group of data input and output terminal signal through holes and a second group of data input and output terminal signal through holes. The first group of data input and output terminal signal through holes The data signals used for transmission and the second group of data input and output terminal signal through holes are used for transmitting data signals of different data channels. The first group of data input and output terminal signal through holes include the first data input and output terminal signal through holes 211 and the third data input and output terminal signal through holes. The second data input and output terminal signal through hole 212, the third data input and output terminal signal through hole 213 and the fourth data input and output terminal signal through hole 214. The first data input and output terminal signal through holes 211 and the third data input and output terminal signal through holes 213 are located in the same row, and the second data input and output terminal signal through holes 212 and the fourth data input and output terminal signal through holes 214 are located in the same column. The second data input and output terminal signal through holes 212 and the first data input and output terminal signal through holes 211 are not in the same row, and the second data input and output terminal signal through holes 212 and the third data input and output terminal signal through holes 213 are not in the same row. . The fourth data input and output terminal signal through holes 214 and the first data input and output terminal signal through holes 211 are not in the same row, and the fourth data input and output terminal signal through holes 214 and the third data input and output terminal signal through holes 213 are not in the same row. . The second group of data input and output terminal signal through holes includes the fifth data input and output terminal signal through hole 215, the sixth data input and output terminal signal through hole 216, the seventh data input and output terminal signal through hole 217 and the eighth data input and output terminal. Signal via 218. The fifth data input and output terminal signal through hole 215 and the seventh data input and output terminal signal through hole 217 are located in the same row, and the sixth data input and output terminal signal through hole 216 and the eighth data input and output terminal signal through hole 218 are located in the same column. The sixth data input and output terminal signal through hole 216 and the fifth data input and output terminal signal through hole 215 are not in the same row, and the sixth data input and output terminal signal through hole 216 and the seventh data input and output terminal signal through hole 217 are not in the same row. . The eighth data input and output terminal signal through hole 218 and the fifth data input and output terminal signal through hole 215 are not in the same row, and the eighth data input and output terminal signal through hole 218 and the seventh data input and output terminal signal through hole 217 are not in the same row. . The above setting method is simple and easy to arrange. It can set up a relatively large number of data input and output signal through holes in a small area, and effectively enlarge the size of two adjacent ones (including two adjacent ones in the same row and the same column). The spacing between two adjacent or diagonally adjacent two data input and output terminal signal through holes 21 can effectively reduce the crosstalk between different data input and output terminal signal through holes 21 at the junction. .
其中,如上述所述,第一组数据输入输出端信号通孔用于传输的数据信号和第二组数据输入输出端信号通孔用于传输不同数据通道的数据信号,即第一组数据输入输出端信号通孔和第二组数据输入输出端信号通孔位于不同的信号通道。进一步的,第一组数据输入输出端信号通孔中的第一数据输入输出端信号通孔211、第二数据输入输出端信号通孔212、第三数据输入输出端信号通孔213和第四数据输入输出端信号通孔214位于同一个信号通道,可以用于传输相同的数据信号,也可以用于传输不同的数据信号,本领域技术人员可以根据实际情况灵活选择;同理,第二组数据输入输出端信号通孔中的第五数据输入输出端信号通孔215、第六数据输入输出端信号通孔216、第七数据输入输出端信号通孔217和第八数据输入输出端信号通孔218同一个信号通道,可以用于传输相同的数据信号,也可以用于传输不同的数据信号,本领域技术人员可以根据实际情况灵活选择。Among them, as mentioned above, the first group of data input and output terminal signal through holes are used to transmit data signals and the second group of data input and output terminal signal through holes are used to transmit data signals of different data channels, that is, the first group of data input terminals is used to transmit data signals. The output signal through holes and the second group of data input and output signal through holes are located in different signal channels. Further, the first data input and output terminal signal through holes 211, the second data input and output terminal signal through holes 212, the third data input and output terminal signal through holes 213 and the fourth data input and output terminal signal through holes in the first group of data input and output terminal signal through holes. The data input and output signal through holes 214 are located in the same signal channel and can be used to transmit the same data signal or different data signals. Those skilled in the art can flexibly choose according to the actual situation; similarly, the second group Among the data input and output terminal signal through holes, the fifth data input and output terminal signal through hole 215, the sixth data input and output terminal signal through hole 216, the seventh data input and output terminal signal through hole 217 and the eighth data input and output terminal signal through hole. The same signal channel of hole 218 can be used to transmit the same data signal or different data signals. Those skilled in the art can flexibly choose according to the actual situation.
根据本申请的一些实施例,参照图1至图4,第一数据输入输出端信号通孔211、第二数据输入输出端信号通孔212、第三数据输入输出端信号通孔213和第四数据输入输出端信号通孔214分布在相邻的三行三列,如此,第一数据输入输出端信号通孔211、第二数据输入输出端信号通孔212、第三数据输入输出端信号通孔213和第四数据输入输出端信号通孔214的连线可以构成一个菱形结构或似菱形结构,在一些具体实施例中,第一数据输入输出端信号通孔211、第二数据输入输出端信号通孔212、第三数据输入输出端信号通孔213和第四数据输入输出端信号通孔214可呈逆时针或顺时针依次排布(附图中以逆时针为例);第五数据输入输出端信号通孔215、第六数据输入输出端信号通孔216、第七数据输入输出端信号通孔217和第八数据输入输出端信号通孔218分布在相邻的三行三列,如此,第五数据输入输出端信号通孔215、第六数据输入输出端信号通孔216、第七数据输入输出端信号通孔217和第八数据输入输出端信号通孔218的连线可以构成一个菱形结构或似菱形结构,在一些具体实施例中,第五数据输入输出端信号通孔215、第六数据输入输出端信号通孔216、第七数据输入输出端信号通孔217和第八数据输入输出端信号通孔218可呈逆时针或顺时针依次排布(附图中以逆时针为例)。如此,上述多个数据输入输出端信号通孔的排布方式,可以在较小的面积内设置相对较多的数据输入输出端信号通孔,且有效加大相邻两个(包括同两行的相邻两个、同列的相邻两个或斜对角的相邻两个三种情况)数据输入输出端信号通孔21之间的间距,进而有效降低信号的串扰,同时在此的基础上,使得信号通孔的排布有一定的规则,既便于设置,也便于辨别。According to some embodiments of the present application, with reference to Figures 1 to 4, the first data input and output terminal signal through hole 211, the second data input and output terminal signal through hole 212, the third data input and output terminal signal through hole 213 and the fourth data input and output terminal signal through hole 211. The data input and output terminal signal through holes 214 are distributed in three adjacent rows and three columns. In this way, the first data input and output terminal signal through holes 211, the second data input and output terminal signal through holes 212, and the third data input and output terminal signal through holes 214. The connection between the hole 213 and the fourth data input and output terminal signal through hole 214 can form a diamond-shaped structure or a diamond-like structure. In some specific embodiments, the first data input and output terminal signal through hole 211 and the second data input and output terminal The signal through hole 212, the third data input and output terminal signal through hole 213 and the fourth data input and output terminal signal through hole 214 can be arranged counterclockwise or clockwise (counterclockwise is used as an example in the drawing); the fifth data The input and output terminal signal through holes 215, the sixth data input and output terminal signal through holes 216, the seventh data input and output terminal signal through holes 217 and the eighth data input and output terminal signal through holes 218 are distributed in three adjacent rows and three columns. In this way, the connection of the fifth data input and output terminal signal through hole 215, the sixth data input and output terminal signal through hole 216, the seventh data input and output terminal signal through hole 217 and the eighth data input and output terminal signal through hole 218 can be formed. A diamond-shaped structure or a diamond-like structure. In some specific embodiments, the fifth data input and output terminal signal through hole 215, the sixth data input and output terminal signal through hole 216, the seventh data input and output terminal signal through hole 217 and the eighth data input and output terminal signal through hole 217. The data input and output signal through holes 218 can be arranged counterclockwise or clockwise (counterclockwise is used as an example in the figure). In this way, the above-mentioned arrangement of multiple data input and output terminal signal through holes can provide a relatively large number of data input and output terminal signal through holes in a small area, and effectively increase the size of two adjacent ones (including the same two rows). Two adjacent ones, two adjacent ones in the same column or two adjacent ones diagonally) The spacing between the signal through holes 21 at the data input and output ends, thereby effectively reducing the crosstalk of the signals, and at the same time, on this basis This makes the arrangement of signal vias have certain rules, which is easy to set up and identify.
在一些实施例中,如图2至图4,上述的第一组数据输入输出端信号通孔和第二组数据输入输出端信号通孔位于相邻两个边区交界处,即位于第一边区11与第二边区12的交界处、第二边区12与第三边区13的交界处、第三边区13与第四边区14的交界处以及第四边区14与第一边区11的交界处,如此,如前所述,上述第一组数据输入输出端信号通孔和第二组数据输入输出端信号通孔中的多个数据输入输出端信号通孔的排布方式,可以在较小的面积内设置相对较多的数据输入输出端信号通孔,且有效加大相邻两个(包括同两行的相邻两个、同列的相邻两个或斜对角的相邻两个三种情况)数据输入输出端信号通孔21之间的间距,进而有效降低信号的串扰,所以当上述的第一组数据输入输出端信号通孔和第二组数据输入输出端信号通孔位于相邻两个边区交界处时,则不仅可有效降低相邻两个边区交界处信号的串扰,同时还可以在有限的面积内设置数量较多的数据输入输出端信号通孔21,满足更多的信号出线,进而有助于成倍提升芯片的存储器访问带宽。In some embodiments, as shown in Figures 2 to 4, the above-mentioned first group of data input and output terminal signal through holes and the second group of data input and output terminal signal through holes are located at the junction of two adjacent side areas, that is, located on the first side. The junction of area 11 and the second side area 12, the junction of the second side area 12 and the third side area 13, the junction of the third side area 13 and the fourth side area 14, and the junction of the fourth side area 14 and the first side area 11 In this way, as mentioned above, the arrangement of the plurality of data input and output signal through holes in the first group of data input and output signal through holes and the second group of data input and output signal through holes can be smaller. A relatively large number of data input and output signal through holes are provided within the area, and two adjacent ones (including two adjacent ones in the same two rows, two adjacent ones in the same column, or two adjacent ones diagonally opposite) are effectively enlarged. Three situations) The spacing between the data input and output terminal signal through holes 21 can effectively reduce the crosstalk of signals. Therefore, when the above-mentioned first group of data input and output terminal signal through holes and the second group of data input and output terminal signal through holes are located At the junction of two adjacent side areas, not only can the crosstalk of signals at the junction of two adjacent side areas be effectively reduced, but a larger number of data input and output signal through holes 21 can also be provided in a limited area to meet more needs. The signals are routed out, which in turn helps to exponentially increase the memory access bandwidth of the chip.
根据本申请的一些实施例,参照图2至图4,第一数据输入输出端信号通孔211、第二数据输入输出端信号通孔212、第三数据输入输出端信号通孔213和第四数据输入输出端信号通孔214的中间设置有一个接地端信号通孔(VSS)22,即如上述所,第一数据输入输出端信号通孔211、第二数据输入输出端信号通孔212、第三数据输入输出端信号通孔213和第四数据输入输出端信号通孔214的连线可以构成一个菱形结构或似菱形结构,菱形结构或似菱形结构的中心具有一个接地端信号通孔(VSS)22,如此,此处设置接地端信号通孔(VSS)22,可以有效减小第一数据输入输出端信号通孔211、第二数据输入输出端信号通孔212、第三数据输入输出端信号通孔213和第四数据输入输出端信号通孔214彼此之间信号的串扰;第五数据输入输出端信号通孔215、第六数据输入输出端信号通孔216、第七数据输入输出端信号通孔217和第八数据输入输出端信号通孔218的中间设置有一个接地端信号通孔(VSS)22,即如上述所,第五数据输入输出端信号通孔215、第六数据输入输出端信号通孔216、第七数据输入输出端信号通孔217和第八数据输入输出端信号通孔218的连线可以构成一个菱形结构或似菱形结构,菱形结构或似菱形结构的中心具有一个接地端信号通孔(VSS)22,如此,此处设置的接地端信号通孔(VSS)22用于接地,相当于在两个数据输入输出端信号通孔21之间设置了信号隔离结构,可以更好的将距离较近的两个数据输入输出端信号通孔21传输的信号隔离开,避免信号串扰,即可以有效减小第一第五数据输入输出端信号通孔215、第六数据输入输出端信号通孔216、第七数据输入输出端信号通孔217和第八数据输入输出端信号通孔218彼此之间信号的串扰。According to some embodiments of the present application, referring to Figures 2 to 4, the first data input and output terminal signal through hole 211, the second data input and output terminal signal through hole 212, the third data input and output terminal signal through hole 213 and the fourth data input and output terminal signal through hole 211. A ground signal through hole (VSS) 22 is provided in the middle of the data input and output terminal signal through hole 214. That is, as mentioned above, the first data input and output terminal signal through hole 211, the second data input and output terminal signal through hole 212, The connection between the third data input and output terminal signal through hole 213 and the fourth data input and output terminal signal through hole 214 can form a diamond-shaped structure or a diamond-like structure, and the center of the diamond structure or diamond-like structure has a ground signal through hole ( VSS) 22. In this way, the ground signal through hole (VSS) 22 is provided here, which can effectively reduce the size of the first data input and output terminal signal through hole 211, the second data input and output terminal signal through hole 212, and the third data input and output port. The crosstalk between the terminal signal through hole 213 and the fourth data input and output terminal signal through hole 214; the fifth data input and output terminal signal through hole 215, the sixth data input and output terminal signal through hole 216, the seventh data input and output terminal signal through hole 215, and the seventh data input and output terminal signal through hole 215. A ground signal through hole (VSS) 22 is provided in the middle of the terminal signal through hole 217 and the eighth data input and output terminal signal through hole 218. That is, as mentioned above, the fifth data input and output terminal signal through hole 215, the sixth data input and output terminal signal through hole 215 and the sixth data input and output terminal signal through hole 218. The connection of the input and output terminal signal through holes 216, the seventh data input and output terminal signal through holes 217 and the eighth data input and output terminal signal through holes 218 can form a rhombus structure or a rhombus-like structure, and the center of the rhombus structure or rhombus-like structure There is a ground signal through hole (VSS) 22. In this way, the ground signal through hole (VSS) 22 provided here is used for grounding, which is equivalent to setting up signal isolation between the two data input and output signal through holes 21. The structure can better isolate the signals transmitted by the signal through holes 21 of the two data input and output terminals that are close to each other to avoid signal crosstalk, that is, it can effectively reduce the signal through holes 215 of the first and fifth data input and output terminals. Crosstalk of signals between the sixth data input and output terminal signal through hole 216, the seventh data input and output terminal signal through hole 217, and the eighth data input and output terminal signal through hole 218.
根据本申请的实施例,封装结构中相邻两个边区交界处信号通孔的设置方式可如以下几种排布:According to the embodiment of the present application, the signal through holes at the junction of two adjacent side areas in the packaging structure can be arranged as follows:
根据本申请的一些实施例,参照图2,第一组数据输入输出端信号通孔位于第一边区11和第三边区13(即是说第一边区11和第三边区13均设置有至少一个第一组数据输入输出端信号通孔,图2中以两个为例,第一边区11的两端以及第三边区13的两端分别设置有一个第一组数据输入输出端信号通孔),第二组数据输入输出端信号通孔位于第二边区12和第四边区14(即是说第二边区12和第四边区14均设置有至少一个第二组数据输入输出端信号通孔,图2中以两个为例,第二边区12的两端以及第四边区14的两端分别设置有一个第二组数据输入输出端信号通孔),其中,第一数据输入输出端信号通孔211、第三数据输入输出端信号通孔213与第八数据输入输出端信号通孔218位于同一行设置,第二数据输入输出端信号通孔212与第五数据输入输出端信号通孔215、第七数据输入输出端信号通孔217位于同一行设置,第一组数据输入输出端信号通孔中的任一数据输入输出端信号通孔21与第二组数据输入输出端信号通孔中的任一数据输入输出端信号通孔21均不属于同一列,且第五数据输入输出端信号通孔215所在列与第三数据输入输出端信号通孔213所在列之间间隔一列,第二数据输入输出端信号通孔212与第五数据输入输出端信号通孔215之间设置有两个接地端信号通孔(VSS)22,第三数据输入输出端信号通孔213与第八数据输入输出端信号通孔218之间设置两个电源端信号通孔(VDD)24。如此,此处设置的接地端信号通孔(VSS)22用于接地,相当于在两个数据输入输出端信号通孔21之间设置了信号隔离结构,可以更好的将距离较近的两个数据输入输出端信号通孔21传输的信号隔离开,避免信号串扰,即可以更进一步的有效减小第一组数据输入输出端信号通孔和第二组数据输入输出端信号通孔中多个数据输入输出端信号通孔21彼此之间信号的串扰;电源端信号通孔(VDD)24的设置可以将第三数据输入输出端信号通孔213与第八数据输入输出端信号通孔218之间的间距拉大,进而避免其传输信号时发生信号串扰的不良现象。According to some embodiments of the present application, referring to Figure 2, the first group of data input and output signal through holes are located in the first side area 11 and the third side area 13 (that is, the first side area 11 and the third side area 13 are both provided with There is at least one first group of data input and output terminal signal through holes. Two are taken as an example in Figure 2. A first group of data input and output terminal signals are respectively provided at both ends of the first side area 11 and both ends of the third side area 13. through holes), the second group of data input and output terminal signal through holes are located in the second side area 12 and the fourth side area 14 (that is to say, the second side area 12 and the fourth side area 14 are both provided with at least one second group of data input and output terminal signals. Through holes, two are taken as an example in Figure 2. A second group of data input and output signal through holes are respectively provided at both ends of the second side area 12 and both ends of the fourth side area 14), wherein the first data input and output The terminal signal through hole 211, the third data input and output terminal signal through hole 213 and the eighth data input and output terminal signal through hole 218 are located in the same row, and the second data input and output terminal signal through hole 212 and the fifth data input and output terminal signal through hole 212 are arranged in the same row. The through holes 215 and the seventh data input and output terminal signal through holes 217 are located in the same row. Any one of the data input and output terminal signal through holes 21 in the first group of data input and output terminal signal through holes is the same as the second group of data input and output terminal signal through holes. None of the data input and output terminal signal through holes 21 in the through holes belong to the same column, and there is one column between the column where the fifth data input and output terminal signal through hole 215 is located and the column where the third data input and output terminal signal through hole 213 is located. , two ground signal through holes (VSS) 22 are provided between the second data input and output terminal signal through hole 212 and the fifth data input and output terminal signal through hole 215, and the third data input and output terminal signal through hole 213 is connected to the third data input and output terminal signal through hole 213. Two power supply signal through holes (VDD) 24 are provided between the eight data input and output terminal signal through holes 218. In this way, the ground terminal signal through hole (VSS) 22 provided here is used for grounding, which is equivalent to providing a signal isolation structure between the two data input and output terminal signal through holes 21, which can better isolate the two data input and output terminals. The signals transmitted by the data input and output terminal signal through holes 21 are isolated to avoid signal crosstalk, that is, the number of signals in the first group of data input and output terminal signal through holes and the second group of data input and output terminal signal through holes can be further effectively reduced. Crosstalk of signals between the data input and output terminal signal through holes 21; the setting of the power supply terminal signal through hole (VDD) 24 can connect the third data input and output terminal signal through hole 213 and the eighth data input and output terminal signal through hole 218 The distance between them is increased to avoid the undesirable phenomenon of signal crosstalk when transmitting signals.
进一步的,如图2所示,以第一边区11和第二边区12的交界处为例,第一边区11的第一行(即第六数据输入输出端信号通孔216所在行)还可以设置有三个接地端信号通孔(VSS)22,以及在第六数据输入输出端信号通孔216所在行,且第六数据输入输出端信号通孔216与第一边区11之间也还可以进一步设置两个接地端信号通孔(VSS)22,如此上述接地端信号通孔(VSS)22用于接地,相当于在两个数据输入输出端信号通孔21之间设置了信号隔离结构,可以更好的将距离较近的两个数据输入输出端信号通孔21传输的信号隔离开,可以更进一步的有效减小多个数据输入输出端信号通孔21彼此之间信号的串扰。另外,其它相邻两个边区的交界处的设置方式也可如上述所述,以便更好的减小多个数据输入输出端信号通孔21彼此之间信号的串扰,具体的不再过多的描述。Further, as shown in FIG. 2 , taking the junction of the first side area 11 and the second side area 12 as an example, the first row of the first side area 11 (that is, the row where the sixth data input and output terminal signal through hole 216 is located) Three ground signal vias (VSS) 22 may also be provided in the row where the sixth data input and output terminal signal vias 216 are located, and there are also between the sixth data input and output terminal signal vias 216 and the first side area 11 Two ground signal through holes (VSS) 22 can also be further provided. In this way, the ground signal through holes (VSS) 22 are used for grounding, which is equivalent to setting up signal isolation between the two data input and output signal through holes 21. The structure can better isolate the signals transmitted by the signal through holes 21 of the two data input and output terminals that are close to each other, and can further effectively reduce the crosstalk of the signals between the signal through holes 21 of the multiple data input and output terminals. . In addition, the junctions of other two adjacent side areas can also be arranged as described above, in order to better reduce the crosstalk of signals between the multiple data input and output terminal signal through holes 21. The specific details are not too many. description of.
根据本申请的另一些实施例,参照图3,第一组数据输入输出端信号通孔位于第一边区11和第三边区13(即是说,第一边区11和第三边区13均设置有至少一个第一组数据输入输出端信号通孔,图3中以两个为例,第一边区11的两端以及第三边区13的两端分别设置有一个第一组数据输入输出端信号通孔),第二组数据输入输出端信号通孔位于第二边区12和第四边区14(即是说,第二边区12和第四边区14均设置有至少一个第二组数据输入输出端信号通孔,图3中以两个为例,第二边区12的两端以及第四边区14的两端分别设置有一个第二组数据输入输出端信号通孔),其中,第二数据输入输出端信号通孔212与第八数据输入输出端信号通孔218位于同一行设置,第一组数据输入输出端信号通孔中的任一数据输入输出端信号通孔21与第二组数据输入输出端信号通孔中的任一数据输入输出端信号通孔21均不属于同一列,且第五数据输入输出端信号通孔215与第三数据输入输出端信号通孔213位于相邻两列,第二数据输入输出端信号通孔212与第八数据输入输出端信号通孔218之间设置两个电源端信号通孔(VDD)24。如此,此处设置的电源端信号通孔(VDD)24,可以将第三数据输入输出端信号通孔213与第八数据输入输出端信号通孔218之间的间距拉大,进而避免其传输信号时发生信号串扰的不良现象,即是说,电源端信号通孔(VDD)24的设置可以更进一步的有效减小第一组数据输入输出端信号通孔和第二组数据输入输出端信号通孔中多个数据输入输出端信号通孔21彼此之间信号的串扰。According to other embodiments of the present application, referring to Figure 3, the first group of data input and output signal through holes are located in the first side area 11 and the third side area 13 (that is, the first side area 11 and the third side area 13 are both At least one first group of data input and output terminal signal through holes are provided. Two are taken as an example in Figure 3. One first group of data input and output ports are respectively provided at both ends of the first side area 11 and both ends of the third side area 13. terminal signal through holes), the second group of data input and output terminal signal through holes are located in the second side area 12 and the fourth side area 14 (that is to say, the second side area 12 and the fourth side area 14 are both provided with at least one second group of data input Output signal through holes, two are taken as an example in Figure 3. A second set of data input and output signal through holes are respectively provided at both ends of the second side area 12 and both ends of the fourth side area 14), wherein the second The data input and output terminal signal through holes 212 and the eighth data input and output terminal signal through holes 218 are located in the same row. Any data input and output terminal signal through holes 21 in the first group of data input and output terminal signal through holes are in the same row as the second group of data input and output terminal signal through holes 218 . None of the data input and output signal through holes 21 belongs to the same column, and the fifth data input and output signal through hole 215 and the third data input and output signal through hole 213 are located adjacent to each other. In two columns, two power supply signal through holes (VDD) 24 are provided between the second data input and output terminal signal through hole 212 and the eighth data input and output terminal signal through hole 218. In this way, the power terminal signal through hole (VDD) 24 provided here can widen the distance between the third data input and output terminal signal through hole 213 and the eighth data input and output terminal signal through hole 218, thereby preventing their transmission. The undesirable phenomenon of signal crosstalk occurs when the signal is transmitted, that is to say, the setting of the power supply signal through hole (VDD) 24 can further effectively reduce the signal through holes of the first group of data input and output terminals and the signal of the second group of data input and output terminals. Crosstalk of signals between multiple data input and output terminal signal through holes 21 in the through holes.
进一步的,如图3所示,以第一边区11和第二边区12的交界处为例,第一边区11的第一行(即第六数据输入输出端信号通孔216所在行)和第二行(即第五数据输入输出端信号通孔216所在行)还可以分别设置有三个接地端信号通孔(VSS)22,以及在第六数据输入输出端信号通孔216所在行,且第六数据输入输出端信号通孔216与第一边区11之间也还可以进一步设置一个接地端信号通孔(VSS)22,如此上述接地端信号通孔(VSS)22的设置,接地端信号通孔(VSS)22用于接地,相当于在两个数据输入输出端信号通孔21之间设置了信号隔离结构,可以更好的将距离较近的两个数据输入输出端信号通孔21传输的信号隔离开,可以更进一步的有效减小多个数据输入输出端信号通孔21彼此之间信号的串扰。另外,其它相邻两个边区的交界处的设置方式也可如上述所述,以便更好的减小多个数据输入输出端信号通孔21彼此之间信号的串扰,具体的不再过多的描述。Further, as shown in FIG. 3 , taking the junction of the first side area 11 and the second side area 12 as an example, the first row of the first side area 11 (that is, the row where the sixth data input and output terminal signal through hole 216 is located) and the second row (that is, the row where the fifth data input and output terminal signal through holes 216 are located) can also be provided with three ground signal through holes (VSS) 22 respectively, and the row where the sixth data input and output terminal signal through holes 216 are located, Moreover, a ground signal through hole (VSS) 22 can also be further provided between the sixth data input and output terminal signal through hole 216 and the first side area 11. In this way, the above ground signal through hole (VSS) 22 is provided to ground. The terminal signal through hole (VSS) 22 is used for grounding, which is equivalent to setting a signal isolation structure between the two data input and output terminal signal through holes 21, which can better connect the signals of the two data input and output terminals that are close to each other. The signals transmitted by the holes 21 are isolated, which can further effectively reduce the crosstalk of signals between the multiple data input and output terminal signal through holes 21 . In addition, the junctions of other two adjacent side areas can also be arranged as described above, in order to better reduce the crosstalk of signals between the multiple data input and output terminal signal through holes 21. The specific details are not too many. description of.
根据本申请的又一些实施例,参照图4,第一组数据输入输出端信号通孔位于第一边区11和第三边区13(即是说,第一边区11和第三边区13均设置有至少一个第一组数据输入输出端信号通孔,图4中以两个为例,第一边区11的两端以及第三边区13的两端分别设置有一个第一组数据输入输出端信号通孔),第二组数据输入输出端信号通孔中的第五数据输入输出端信号通孔215位于第二边区12和第四边区14,第二组数据输入输出端信号通孔中的第六数据输入输出端信号通孔216、第七数据输入输出端信号通孔217和第八数据输入输出端信号通孔218位于第二边区12和第四边区14,其中,第三数据输入输出端信号通孔213与第五数据输入输出端信号通孔215位于同一列,第一组数据输入输出端信号通孔中的任一数据输入输出端信号通孔21与第二组数据输入输出端信号通孔21中的任一数据输入输出端信号通孔均不属于同一行,且第二数据输入输出端信号通孔212与第八数据输入输出端信号通孔218位于相邻两行,第三数据输入输出端信号通孔213与第五数据输入输出端信号通孔215之间设置两个电源端信号通孔(VDD)24。如此,此处设置的接地端信号通孔(VSS)22用于接地,相当于在两个数据输入输出端信号通孔21之间设置了信号隔离结构,可以更好的将距离较近的两个数据输入输出端信号通孔21传输的信号隔离开,避免信号串扰,即可以更进一步的有效减小第一组数据输入输出端信号通孔和第二组数据输入输出端信号通孔中多个数据输入输出端信号通孔21彼此之间信号的串扰;电源端信号通孔(VDD)24的设置可以将第三数据输入输出端信号通孔213与第八数据输入输出端信号通孔218之间的间距拉大,进而避免其传输信号时发生信号串扰的不良现象。According to some embodiments of the present application, referring to Figure 4, the first group of data input and output signal through holes are located in the first side area 11 and the third side area 13 (that is, the first side area 11 and the third side area 13 are both At least one first group of data input and output terminal signal through holes are provided. Two are taken as an example in Figure 4. One first group of data input and output ports are respectively provided at both ends of the first side area 11 and both ends of the third side area 13. end signal through hole), the fifth data input and output end signal through hole 215 in the second group of data input and output end signal through holes is located in the second side area 12 and the fourth side area 14, and the second group of data input and output end signal through holes The sixth data input and output terminal signal through hole 216, the seventh data input and output terminal signal through hole 217 and the eighth data input and output terminal signal through hole 218 are located in the second side area 12 and the fourth side area 14, wherein the third data input The output signal through hole 213 and the fifth data input and output signal through hole 215 are located in the same column. Any data input and output signal through hole 21 in the first group of data input and output signal through holes is in the same row as the second group of data input and output signal through holes. None of the data input/output signal vias 21 belong to the same row, and the second data input/output signal via 212 and the eighth data input/output signal via 218 are located in two adjacent rows, Two power supply signal through holes (VDD) 24 are provided between the third data input and output terminal signal through hole 213 and the fifth data input and output terminal signal through hole 215. In this way, the ground terminal signal through hole (VSS) 22 provided here is used for grounding, which is equivalent to providing a signal isolation structure between the two data input and output terminal signal through holes 21, which can better isolate the two data input and output terminals. The signals transmitted by the data input and output terminal signal through holes 21 are isolated to avoid signal crosstalk, that is, the number of signals in the first group of data input and output terminal signal through holes and the second group of data input and output terminal signal through holes can be further effectively reduced. Crosstalk of signals between the data input and output terminal signal through holes 21; the setting of the power supply terminal signal through hole (VDD) 24 can connect the third data input and output terminal signal through hole 213 and the eighth data input and output terminal signal through hole 218 The distance between them is increased to avoid the undesirable phenomenon of signal crosstalk when transmitting signals.
进一步的,如图4所示,以第一边区11和第二边区12的交界处为例,第一边区11中,第二数据输入输出端信号通孔212所在列且其上方还可以设置有三个接地端信号通孔(VSS)22,以及第一数据输入输出端信号通孔211所在列且其上方还可以设置有三个接地端信号通孔(VSS)22,以及第五数据输入输出端信号通孔215所在列且其上方还可以设置有一个接地端信号通孔(VSS)22,如此上述的接地端信号通孔(VSS)22用于接地,相当于在两个数据输入输出端信号通孔21之间设置了信号隔离结构,可以更好的将距离较近的两个数据输入输出端信号通孔21传输的信号隔离开,避免信号串扰,即接地端信号通孔(VSS)22的设置,可以更进一步的有效减小多个数据输入输出端信号通孔21彼此之间信号的串扰。另外,其它相邻两个边区的交界处的设置方式也可如上述所述,以便更好的减小多个数据输入输出端信号通孔21彼此之间信号的串扰,具体的不再过多的描述。Further, as shown in Figure 4, taking the junction of the first side area 11 and the second side area 12 as an example, in the first side area 11, the second data input and output terminal signal through hole 212 is located in the column and above it. Three ground signal through holes (VSS) 22 are provided, as well as the column where the first data input and output signal through hole 211 is located, and three ground signal through holes (VSS) 22 can be provided above it, as well as a fifth data input and output. A ground signal through hole (VSS) 22 can be provided in the column where the terminal signal through hole 215 is located and above it. In this way, the above ground terminal signal through hole (VSS) 22 is used for grounding, which is equivalent to two data input and output terminals. A signal isolation structure is set up between the signal through holes 21, which can better isolate the signals transmitted by the two data input and output terminal signal through holes 21 that are close to each other and avoid signal crosstalk, that is, the ground signal through hole (VSS) The arrangement of 22 can further effectively reduce the crosstalk of signals between the multiple data input and output terminal signal through holes 21 . In addition, the junctions of other two adjacent side areas can also be arranged as described above, in order to better reduce the crosstalk of signals between the multiple data input and output terminal signal through holes 21. The specific details are not too many. description of.
根据本申请的实施例,上述列举的三种具体实施例中的数据输入输出端信号通孔排布方式可以在同一封装结构中设置,即使说,第一边区11和第二边区12交界处的数据输入输出端信号通孔21排布方式、第二边区12和第三边区13交界处的数据输入输出端信号通孔21排布方式、第三边区13和第四边区14交界处的数据输入输出端信号通孔21排布方式、第四边区14和第一边区11交界处的数据输入输出端信号通孔21排布方式可以相同(如图2~图4),也可以不同,即可以选择上述三种的任一种的排布方式,或者说,第一边区11和第二边区12交界处的数据输入输出端信号通孔21排布方式、第二边区12和第三边区13交界处的数据输入输出端信号通孔21排布方式、第三边区13和第四边区14交界处的数据输入输出端信号通孔21排布方式、第四边区14和第一边区11交界处的数据输入输出端信号通孔21排布方式是相互独立的。According to the embodiment of the present application, the arrangement of signal through holes of the data input and output terminals in the three specific embodiments listed above can be set in the same packaging structure, that is, at the junction of the first side area 11 and the second side area 12 The arrangement of the data input and output terminal signal through holes 21, the arrangement of the data input and output terminal signal through holes 21 at the junction of the second side area 12 and the third side area 13, the data at the junction of the third side area 13 and the fourth side area 14 The arrangement of the input and output signal through holes 21 and the arrangement of the data input and output signal through holes 21 at the junction of the fourth side area 14 and the first side area 11 can be the same (as shown in Figure 2 to Figure 4), or they can be different. That is, you can choose any of the above three arrangements, or in other words, the arrangement of the data input and output signal through holes 21 at the junction of the first side area 11 and the second side area 12, the arrangement of the second side area 12 and the third side area. The arrangement of the data input and output terminal signal through holes 21 at the junction of the third side area 13 and the fourth side area 14, the arrangement of the data input and output terminal signal through holes 21 at the junction of the third side area 13 and the fourth side area 14, the fourth side area 14 and the first side area The arrangement of the signal through holes 21 at the data input and output terminals at the junction 11 is independent of each other.
根据本申请的实施例,在上述的封装结构中,除了前面提到的数据输入输出端信号通孔21、接地端信号通孔(VSS)22以及电源端信号通孔(VDD)24的排布,其与信号通孔的排布以及不同的信号通孔对应的具体信号出线均没有特殊要求,本领域技术人员可以根据实际情况灵活选择,在此不做限制要求。According to the embodiment of the present application, in the above package structure, in addition to the aforementioned arrangement of the data input and output terminal signal through holes 21, the ground terminal signal through holes (VSS) 22 and the power terminal signal through holes (VDD) 24 , there are no special requirements for the arrangement of signal through holes and the specific signal outlets corresponding to different signal through holes. Those skilled in the art can flexibly choose according to the actual situation, and there are no restrictions here.
在本申请的另一方面,本申请提供了一种处理器芯片。根据本申请的实施例,参照图5,该处理器芯片1000包括前面所述的封装结构1100,进一步的,如图4所示,该处理器芯片还包括设置于该封装结构1100的表面上的多个存储颗粒1200,以及位于存储颗粒1200远离封装结构1100一侧的塑封层1300,如此,可以对存储颗粒1200和封装结构1100起到良好的保护作用。由此,该处理器芯片可实现成倍提升的存储器访问带宽。作为一个非限制性示例,采用该封装结构的处理器芯片的存储器访问带宽可达到128bits。本领域技术人员可以理解,该处理器芯片具有前面所述的封装结构的所有特征和优点,在此不再过多的赘述。In another aspect of the present application, the present application provides a processor chip. According to an embodiment of the present application, with reference to FIG. 5 , the processor chip 1000 includes the previously described packaging structure 1100 . Further, as shown in FIG. 4 , the processor chip further includes a surface disposed on the surface of the packaging structure 1100 The plurality of storage particles 1200 and the plastic sealing layer 1300 located on the side of the storage particles 1200 away from the packaging structure 1100 can provide good protection for the storage particles 1200 and the packaging structure 1100 . As a result, the processor chip can achieve exponentially increased memory access bandwidth. As a non-limiting example, the memory access bandwidth of a processor chip using this packaging structure can reach 128 bits. Those skilled in the art can understand that the processor chip has all the features and advantages of the previously described packaging structure, which will not be described in detail here.
其中,上述塑封层1300可以为环氧树脂或其它适用于芯片封装的塑封材料。在一些具体实施例中,该处理器芯片为应用处理器芯片(AP芯片)。The above-mentioned plastic sealing layer 1300 may be epoxy resin or other plastic sealing materials suitable for chip packaging. In some specific embodiments, the processor chip is an application processor chip (AP chip).
在本申请的另一方面,本申请提供了一种POP封装组件。根据本申请的实施例,参照图6,该POP封装组件1包括:前面所述的处理器芯片1000;以及与所述处理器芯片1000垂直堆叠封装的第一芯片2000。由此,该POP封装组件具有前面的处理器芯片,可以实现成倍提升的存储器访问带宽。作为一个非限制性示例,采用该封装结构的处理器芯片的存储器访问带宽可达到128bits。In another aspect of the present application, the present application provides a POP packaging component. According to an embodiment of the present application, referring to FIG. 6 , the POP package component 1 includes: the aforementioned processor chip 1000; and a first chip 2000 vertically stacked and packaged with the processor chip 1000. As a result, the POP package component has a front processor chip and can achieve exponentially increased memory access bandwidth. As a non-limiting example, the memory access bandwidth of a processor chip using this packaging structure can reach 128 bits.
具体的,上述第一芯片可以为DRAM芯片(动态随机存储芯片),处理器芯片与DRAM芯片垂直堆叠封装构成POP封装组件。Specifically, the above-mentioned first chip may be a DRAM chip (dynamic random access memory chip), and the processor chip and the DRAM chip are vertically stacked and packaged to form a POP package component.
在本申请的另一方面,本申请提供了一种电子设备。根据本申请的实施例,该电子设备包括前面所述的处理器芯片。由此,该电子设备具有更好的性能。In another aspect of the present application, the present application provides an electronic device. According to an embodiment of the present application, the electronic device includes the aforementioned processor chip. As a result, the electronic device has better performance.
其中,电子设备的具体种类没有特殊要求,本领域技术人员可以根据实际需求灵活选择,比如,电子设备的具体种类包括但不限于手机、iPad、电脑、电视等一切可以应用处理器芯片的电子设备。Among them, there are no special requirements for the specific types of electronic devices. Those skilled in the art can flexibly choose according to actual needs. For example, the specific types of electronic devices include but are not limited to mobile phones, iPads, computers, TVs and other electronic devices that can apply processor chips. .
文中术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中,“多个”的含义是两个或两个以上,除非另有明确具体的限定。The terms "first" and "second" in this article are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of this application, "plurality" means two or more than two, unless otherwise explicitly and specifically limited.
在本说明书的描述中,参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。在本说明书中,对上述术语的示意性表述不必针对的是相同的实施例或示例。而且,描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外,在不相互矛盾的情况下,本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。In the description of this specification, reference to the terms "one embodiment," "some embodiments," "an example," "specific examples," or "some examples" or the like means that specific features are described in connection with the embodiment or example. , structures, materials or features are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine different embodiments or examples and features of different embodiments or examples described in this specification unless they are inconsistent with each other.
尽管上面已经示出和描述了本申请的实施例,可以理解的是,上述实施例是示例性的,不能理解为对本申请的限制,本领域的普通技术人员在本申请的范围内可以对上述实施例进行变化、修改、替换和变型。Although the embodiments of the present application have been shown and described above, it can be understood that the above-mentioned embodiments are illustrative and cannot be understood as limitations of the present application. Those of ordinary skill in the art can make modifications to the above-mentioned embodiments within the scope of the present application. The embodiments are subject to changes, modifications, substitutions and variations.

Claims (29)

  1. 一种封装结构,其中,包括:A packaging structure, including:
    基板,所述基板具有周边区,所述周边区包括依次相连的第一边区、第二边区、第三边区和第四边区,所述第一边区、所述第二边区、所述第三边区和所述第四边区具有呈多行多列设置的信号通孔,所述信号通孔中设置有导体。A substrate having a peripheral area, the peripheral area including a first side area, a second side area, a third side area and a fourth side area connected in sequence, the first side area, the second side area, the third side area The three side areas and the fourth side area have signal via holes arranged in multiple rows and columns, and conductors are arranged in the signal via holes.
  2. 根据权利要求1所述的封装结构,其中,所述导体为铜柱。The package structure of claim 1, wherein the conductor is a copper pillar.
  3. 根据权利要求1所述的封装结构,其中,位于所述第二边区和所述第四边区的所述信号通孔呈三行排布,位于所述第一边区和所述第三边区的所述信号通孔呈至少两列排布。The package structure according to claim 1, wherein the signal through holes located in the second side area and the fourth side area are arranged in three rows, and the signal through holes located in the first side area and the third side area are arranged in three rows. The signal through holes are arranged in at least two rows.
  4. 根据权利要求1所述的封装结构,其中,位于所述第一边区和所述第三边区的所述信号通孔呈三列排布。The packaging structure according to claim 1, wherein the signal through holes located in the first side area and the third side area are arranged in three columns.
  5. 根据权利要求3所述的封装结构,其中,所述信号通孔包括数据输入输出端信号通孔,位于同一行或同一列的相邻两个上述数据输入输出端信号通孔之间具有至少一个非数据输入输出端信号通孔。The package structure according to claim 3, wherein the signal through holes include data input and output signal through holes, and there is at least one between two adjacent data input and output signal through holes located in the same row or the same column. Non-data input and output signal through holes.
  6. 根据权利要求1-5中任一项所述的封装结构,其中,所述信号通孔包括至少一组数据输入输出端信号通孔,所述至少一组所述数据输入输出端信号通孔包括分布在相邻的三行和三列且呈菱形结构或似菱形结构排布的四个数据输入输出端信号通孔。The packaging structure according to any one of claims 1 to 5, wherein the signal vias include at least one group of data input and output signal vias, and the at least one group of data input and output signal vias includes Four data input and output terminal signal through holes are distributed in three adjacent rows and three columns and arranged in a rhombus or rhombus-like structure.
  7. 根据权利要求1-6中任一项所述的封装结构,其中,所述信号通孔包括第一组数据输入输出端信号通孔和第二组数据输入输出端信号通孔,所述第一组数据输入输出端信号通孔用于传输的数据信号和所述第二组数据输入输出端信号通孔用于传输不同数据通道的数据信号,所述第一组数据输入输出端信号通孔和所述第二组数据输入输出端信号通孔满足以下条件至少之一:The packaging structure according to any one of claims 1 to 6, wherein the signal through holes include a first group of data input and output terminal signal through holes and a second group of data input and output terminal signal through holes, and the first A group of data input and output terminal signal through holes are used to transmit data signals and the second group of data input and output terminal signal through holes are used to transmit data signals of different data channels. The first group of data input and output terminal signal through holes are used to transmit data signals. The second group of data input and output signal through holes meet at least one of the following conditions:
    所述第一组数据输入输出端信号通孔包括第一数据输入输出端信号通孔、第二数据输入输出端信号通孔、第三数据输入输出端信号通孔和第四数据输入输出端信号通孔,所述第一数据输入输出端信号通孔和所述第三数据输入输出端信号通孔位于同一行,所述第二数据输入输出端信号通孔和所述第四数据输入输出端信号通孔位于同一列,且与所述第一数据输入输出端信号通孔和所述第三数据输入输出端信号通孔不在同一行;The first group of data input and output terminal signal through holes includes a first data input and output terminal signal through hole, a second data input and output terminal signal through hole, a third data input and output terminal signal through hole and a fourth data input and output terminal signal through hole. through holes, the first data input and output terminal signal through holes and the third data input and output terminal signal through holes are located in the same row, the second data input and output terminal signal through holes and the fourth data input and output terminal The signal through holes are located in the same column and are not in the same row as the first data input and output terminal signal through holes and the third data input and output terminal signal through holes;
    所述第二组数据输入输出端信号通孔包括第五数据输入输出端信号通孔、第六数据输入输出端信号通孔、第七数据输入输出端信号通孔和第八数据输入输出端信号通孔,所述第五数据输入输出端信号通孔和所述第七数据输入输出端信号通孔位于同一行,所述第六数据输入输出端信号通孔和所述第八数据输入输出端信号通孔位于同一列,且与所述第五数据输入输出端信号通孔和所述第七数据输入输出端信号通孔不在同一行。The second group of data input and output terminal signal through holes includes a fifth data input and output terminal signal through hole, a sixth data input and output terminal signal through hole, a seventh data input and output terminal signal through hole and an eighth data input and output terminal signal through hole. through holes, the fifth data input and output terminal signal through holes and the seventh data input and output terminal signal through holes are located in the same row, the sixth data input and output terminal signal through holes and the eighth data input and output terminal The signal through holes are located in the same column and are not in the same row as the fifth data input and output terminal signal through holes and the seventh data input and output terminal signal through holes.
  8. 根据权利要求7所述的封装结构,其中,所述第一组数据输入输出端信号通孔和所述第二组数据输入输出端信号通孔均位于相邻两个边区交界处。The packaging structure according to claim 7, wherein the first group of data input and output terminal signal through holes and the second group of data input and output terminal signal through holes are located at the junction of two adjacent side areas.
  9. 根据权利要求7所述的封装结构,其中,所述第一组数据输入输出端信号通孔和所述第二组数 据输入输出端信号通孔满足以下条件至少之一:The packaging structure according to claim 7, wherein the first group of data input and output terminal signal through holes and the second group of digital The input and output signal through holes meet at least one of the following conditions:
    所述第一数据输入输出端信号通孔、所述第二数据输入输出端信号通孔、所述第三数据输入输出端信号通孔和所述第四数据输入输出端信号通孔分布在相邻的三行三列,呈菱形结构或似菱形结构排布;The first data input and output terminal signal through holes, the second data input and output terminal signal through holes, the third data input and output terminal signal through holes and the fourth data input and output terminal signal through holes are distributed in the same direction. There are three adjacent rows and three columns, arranged in a rhombus or rhombus-like structure;
    所述第五数据输入输出端信号通孔、所述第六数据输入输出端信号通孔、所述第七数据输入输出端信号通孔和所述第八数据输入输出端信号通孔分布在相邻的三行三列,形成菱形结构或似菱形结构布置。The fifth data input and output terminal signal through holes, the sixth data input and output terminal signal through holes, the seventh data input and output terminal signal through holes and the eighth data input and output terminal signal through holes are distributed in the same direction. Three adjacent rows and three columns form a rhombus or rhombus-like structure arrangement.
  10. 根据权利要求9所述的封装结构,其中,所述第一数据输入输出端信号通孔、所述第二数据输入输出端信号通孔、所述第三数据输入输出端信号通孔和所述第四数据输入输出端信号通孔的中间设置有一个接地端信号通孔,所述第五数据输入输出端信号通孔、所述第六数据输入输出端信号通孔、所述第七数据输入输出端信号通孔和所述第八数据输入输出端信号通孔的中间设置有一个所述接地端信号通孔。The package structure according to claim 9, wherein the first data input and output terminal signal through holes, the second data input and output terminal signal through holes, the third data input and output terminal signal through holes and the A ground signal through hole is provided in the middle of the fourth data input and output terminal signal through hole, the fifth data input and output terminal signal through hole, the sixth data input and output terminal signal through hole, the seventh data input terminal signal through hole, One of the ground terminal signal through holes is disposed between the output terminal signal through hole and the eighth data input and output terminal signal through hole.
  11. 根据权利要求9所述的封装结构,其中,所述第一组数据输入输出端信号通孔位于所述第一边区和所述第三边区,所述第二组数据输入输出端信号通孔位于所述第二边区和所述第四边区,其中,所述第一数据输入输出端信号通孔、所述第三数据输入输出端信号通孔与所述第八数据输入输出端信号通孔位于同一行设置,所述第二数据输入输出端信号通孔与所述第五数据输入输出端信号通孔、所述第七数据输入输出端信号通孔位于同一行设置,所述第一组数据输入输出端信号通孔中的任一数据输入输出端信号通孔与所述第二组数据输入输出端信号通孔中的任一数据输入输出端信号通孔均不属于同一列,且所述第五数据输入输出端信号通孔所在列与所述第三数据输入输出端信号通孔所在列之间间隔一列,所述第二数据输入输出端信号通孔与所述第五数据输入输出端信号通孔之间设置有两个接地端信号通孔,所述第三数据输入输出端信号通孔与所述第八数据输入输出端信号通孔之间设置两个电源端信号通孔。The package structure according to claim 9, wherein the first group of data input and output terminal signal through holes are located in the first side area and the third side area, and the second group of data input and output terminal signal through holes Located in the second side area and the fourth side area, wherein the first data input and output terminal signal through hole, the third data input and output terminal signal through hole and the eighth data input and output terminal signal through hole Located in the same row, the second data input and output terminal signal through holes, the fifth data input and output terminal signal through holes, and the seventh data input and output terminal signal through holes are located in the same row, and the first group Any data input and output signal through holes in the data input and output signal through holes and any data input and output signal through holes in the second group of data input and output signal through holes do not belong to the same column, and all data input and output signal through holes do not belong to the same column. There is one column spaced between the column where the fifth data input and output terminal signal through holes are located and the column where the third data input and output terminal signal through holes are located, and the second data input and output terminal signal through holes and the fifth data input and output terminal signal through holes are separated by one column. Two ground terminal signal through holes are provided between the terminal signal through holes, and two power terminal signal through holes are provided between the third data input and output terminal signal through holes and the eighth data input and output terminal signal through holes.
  12. 根据权利要求9所述的封装结构,其中,所述第一组数据输入输出端信号通孔位于所述第一边区和所述第三边区,所述第二组数据输入输出端信号通孔位于所述第二边区和所述第四边区,其中,所述第二数据输入输出端信号通孔与所述第八数据输入输出端信号通孔位于同一行设置,所述第一组数据输入输出端信号通孔中的任一数据输入输出端信号通孔与所述第二组数据输入输出端信号通孔中的任一数据输入输出端信号通孔均不属于同一列,且所述第五数据输入输出端信号通孔与所述第三数据输入输出端信号通孔位于相邻两列,所述第二数据输入输出端信号通孔与所述第八数据输入输出端信号通孔之间设置两个电源端信号通孔。The package structure according to claim 9, wherein the first group of data input and output terminal signal through holes are located in the first side area and the third side area, and the second group of data input and output terminal signal through holes Located in the second side area and the fourth side area, wherein the second data input and output terminal signal through holes and the eighth data input and output terminal signal through holes are located in the same row, and the first group of data input Any data input and output signal through holes in the output signal through holes and any data input and output signal through holes in the second group of data input and output signal through holes do not belong to the same column, and the third group of data input and output signal through holes does not belong to the same column. The fifth data input and output terminal signal through holes and the third data input and output terminal signal through holes are located in two adjacent columns, and the second data input and output terminal signal through holes are between the eighth data input and output terminal signal through holes. Two power supply signal through holes are provided between them.
  13. 根据权利要求9所述的封装结构,其中,所述第一组数据输入输出端信号通孔位于所述第一边区和所述第三边区,所述第二组数据输入输出端信号通孔中的所述第五数据输入输出端信号通孔位于所述第一边区和所述第三边区,所述第二组数据输入输出端信号通孔中的所述第六数据输入输出端信号通孔、所述第七数据输入输出端信号通孔和所述第八数据输入输出端信号通孔位于所述第二边区和所述第四边区,其中,所述第三数据输入输出端信号通孔与所述第五数据输入输出端信号通孔位于同一列,所 述第一组数据输入输出端信号通孔中的任一数据输入输出端信号通孔与所述第二组数据输入输出端信号通孔中的任一数据输入输出端信号通孔均不属于同一行,且所述第二数据输入输出端信号通孔与所述第八数据输入输出端信号通孔位于相邻两行,所述第三数据输入输出端信号通孔与所述第五数据输入输出端信号通孔之间设置两个电源端信号通孔。The package structure according to claim 9, wherein the first group of data input and output terminal signal through holes are located in the first side area and the third side area, and the second group of data input and output terminal signal through holes The fifth data input and output terminal signal through holes are located in the first side area and the third side area, and the sixth data input and output terminal signals in the second group of data input and output terminal signal through holes are located in the first side area and the third side area. The through hole, the seventh data input and output terminal signal through hole and the eighth data input and output terminal signal through hole are located in the second side area and the fourth side area, wherein the third data input and output terminal signal The through hole is located in the same column as the fifth data input and output terminal signal through hole, so Any data input and output terminal signal through holes in the first group of data input and output terminal signal through holes and any data input and output terminal signal through holes in the second group of data input and output terminal signal through holes do not belong to the same rows, and the second data input and output terminal signal through holes and the eighth data input and output terminal signal through holes are located in two adjacent rows, and the third data input and output terminal signal through holes and the fifth data input terminal signal through holes are located in two adjacent rows. Two power supply signal through holes are provided between the output signal through holes.
  14. 一种处理器芯片,其中,包括权利要求1所述的封装结构。A processor chip, which includes the packaging structure of claim 1.
  15. 根据权利要求14所述的处理器芯片,其中,所述导体为铜柱。The processor chip of claim 14, wherein the conductor is a copper pillar.
  16. 根据权利要求14所述的处理器芯片,其中,位于所述第二边区和所述第四边区的所述信号通孔呈三行排布,位于所述第一边区和所述第三边区的所述信号通孔呈至少两列排布。The processor chip according to claim 14, wherein the signal through holes located in the second side area and the fourth side area are arranged in three rows, and the signal via holes located in the first side area and the third side area The signal via holes are arranged in at least two rows.
  17. 根据权利要求14所述的处理器芯片,其中,位于所述第一边区和所述第三边区的所述信号通孔呈三列排布。The processor chip according to claim 14, wherein the signal through holes located in the first side area and the third side area are arranged in three columns.
  18. 根据权利要求16所述的处理器芯片,其中,所述信号通孔包括数据输入输出端信号通孔,位于同一行或同一列的相邻两个上述数据输入输出端信号通孔之间具有至少一个非数据输入输出端信号通孔。The processor chip according to claim 16, wherein the signal vias include data input and output signal vias, and there are at least two adjacent data input and output signal vias located in the same row or column. A non-data input and output signal via.
  19. 根据权利要求14-18中任一项所述的处理器芯片,其中,所述信号通孔包括至少一组数据输入输出端信号通孔,所述至少一组所述数据输入输出端信号通孔包括分布在相邻的三行和三列且呈菱形结构或似菱形结构排布的四个数据输入输出端信号通孔。The processor chip according to any one of claims 14 to 18, wherein the signal vias include at least one group of data input and output signal vias, and the at least one group of data input and output signal vias It includes four data input and output signal through holes distributed in three adjacent rows and three columns and arranged in a rhombus or rhombus-like structure.
  20. 根据权利要求14-19中任一项所述的处理器芯片,其中,所述信号通孔包括第一组数据输入输出端信号通孔和第二组数据输入输出端信号通孔,所述第一组数据输入输出端信号通孔用于传输的数据信号和所述第二组数据输入输出端信号通孔用于传输不同数据通道的数据信号,所述第一组数据输入输出端信号通孔和所述第二组数据输入输出端信号通孔满足以下条件至少之一:The processor chip according to any one of claims 14 to 19, wherein the signal vias include a first group of data input and output terminal signal via holes and a second group of data input and output terminal signal via holes, and the third group of data input and output terminal signal via holes A group of data input and output terminal signal through holes are used to transmit data signals, and the second group of data input and output terminal signal through holes are used to transmit data signals of different data channels. The first group of data input and output terminal signal through holes are used to transmit data signals of different data channels. and the second group of data input and output signal through holes meet at least one of the following conditions:
    所述第一组数据输入输出端信号通孔包括第一数据输入输出端信号通孔、第二数据输入输出端信号通孔、第三数据输入输出端信号通孔和第四数据输入输出端信号通孔,所述第一数据输入输出端信号通孔和所述第三数据输入输出端信号通孔位于同一行,所述第二数据输入输出端信号通孔和所述第四数据输入输出端信号通孔位于同一列,且与所述第一数据输入输出端信号通孔和所述第三数据输入输出端信号通孔不在同一行;The first group of data input and output terminal signal through holes includes a first data input and output terminal signal through hole, a second data input and output terminal signal through hole, a third data input and output terminal signal through hole and a fourth data input and output terminal signal through hole. through holes, the first data input and output terminal signal through holes and the third data input and output terminal signal through holes are located in the same row, the second data input and output terminal signal through holes and the fourth data input and output terminal The signal through holes are located in the same column and are not in the same row as the first data input and output terminal signal through holes and the third data input and output terminal signal through holes;
    所述第二组数据输入输出端信号通孔包括第五数据输入输出端信号通孔、第六数据输入输出端信号通孔、第七数据输入输出端信号通孔和第八数据输入输出端信号通孔,所述第五数据输入输出端信号通孔和所述第七数据输入输出端信号通孔位于同一行,所述第六数据输入输出端信号通孔和所述第八数据输入输出端信号通孔位于同一列,且与所述第五数据输入输出端信号通孔和所述第七数据输入输出端信号通孔不在同一行。The second group of data input and output terminal signal through holes includes a fifth data input and output terminal signal through hole, a sixth data input and output terminal signal through hole, a seventh data input and output terminal signal through hole and an eighth data input and output terminal signal through hole. through holes, the fifth data input and output terminal signal through holes and the seventh data input and output terminal signal through holes are located in the same row, the sixth data input and output terminal signal through holes and the eighth data input and output terminal The signal through holes are located in the same column and are not in the same row as the fifth data input and output terminal signal through holes and the seventh data input and output terminal signal through holes.
  21. 根据权利要求20所述的处理器芯片,其中,所述第一组数据输入输出端信号通孔和所述第二组数据输入输出端信号通孔均位于相邻两个边区交界处。 The processor chip according to claim 20, wherein the first group of data input and output terminal signal through holes and the second group of data input and output terminal signal through holes are located at the junction of two adjacent side areas.
  22. 根据权利要求20所述的处理器芯片,其中,所述第一组数据输入输出端信号通孔和所述第二组数据输入输出端信号通孔满足以下条件至少之一:The processor chip according to claim 20, wherein the first group of data input and output terminal signal through holes and the second group of data input and output terminal signal through holes satisfy at least one of the following conditions:
    所述第一数据输入输出端信号通孔、所述第二数据输入输出端信号通孔、所述第三数据输入输出端信号通孔和所述第四数据输入输出端信号通孔分布在相邻的三行三列,呈菱形结构或似菱形结构排布;The first data input and output terminal signal through holes, the second data input and output terminal signal through holes, the third data input and output terminal signal through holes and the fourth data input and output terminal signal through holes are distributed in the same direction. There are three adjacent rows and three columns, arranged in a rhombus or rhombus-like structure;
    所述第五数据输入输出端信号通孔、所述第六数据输入输出端信号通孔、所述第七数据输入输出端信号通孔和所述第八数据输入输出端信号通孔分布在相邻的三行三列,形成菱形结构或似菱形结构布置。The fifth data input and output terminal signal through holes, the sixth data input and output terminal signal through holes, the seventh data input and output terminal signal through holes and the eighth data input and output terminal signal through holes are distributed in the same direction. Three adjacent rows and three columns form a rhombus or rhombus-like structure arrangement.
  23. 根据权利要求22所述的处理器芯片,其中,所述第一数据输入输出端信号通孔、所述第二数据输入输出端信号通孔、所述第三数据输入输出端信号通孔和所述第四数据输入输出端信号通孔的中间设置有一个接地端信号通孔,所述第五数据输入输出端信号通孔、所述第六数据输入输出端信号通孔、所述第七数据输入输出端信号通孔和所述第八数据输入输出端信号通孔的中间设置有一个所述接地端信号通孔。The processor chip according to claim 22, wherein the first data input and output terminal signal through holes, the second data input and output terminal signal through holes, the third data input and output terminal signal through holes and the There is a ground signal through hole in the middle of the fourth data input and output terminal signal through hole, the fifth data input and output terminal signal through hole, the sixth data input and output terminal signal through hole, the seventh data input and output terminal signal through hole, and the seventh data input and output terminal signal through hole. One of the ground terminal signal through holes is disposed between the input and output terminal signal through holes and the eighth data input and output terminal signal through holes.
  24. 根据权利要求22所述的处理器芯片,其中,所述第一组数据输入输出端信号通孔位于所述第一边区和所述第三边区,所述第二组数据输入输出端信号通孔位于所述第二边区和所述第四边区,其中,所述第一数据输入输出端信号通孔、所述第三数据输入输出端信号通孔与所述第八数据输入输出端信号通孔位于同一行设置,所述第二数据输入输出端信号通孔与所述第五数据输入输出端信号通孔、所述第七数据输入输出端信号通孔位于同一行设置,所述第一组数据输入输出端信号通孔中的任一数据输入输出端信号通孔与所述第二组数据输入输出端信号通孔中的任一数据输入输出端信号通孔均不属于同一列,且所述第五数据输入输出端信号通孔所在列与所述第三数据输入输出端信号通孔所在列之间间隔一列,所述第二数据输入输出端信号通孔与所述第五数据输入输出端信号通孔之间设置有两个接地端信号通孔,所述第三数据输入输出端信号通孔与所述第八数据输入输出端信号通孔之间设置两个电源端信号通孔。The processor chip according to claim 22, wherein the first group of data input and output terminal signal through holes are located in the first side area and the third side area, and the second group of data input and output terminal signal through holes are located in the first side area and the third side area. Holes are located in the second side area and the fourth side area, wherein the first data input and output terminal signal through holes, the third data input and output terminal signal through holes and the eighth data input and output terminal signal through holes The holes are arranged in the same row, the second data input and output terminal signal through holes, the fifth data input and output terminal signal through holes and the seventh data input and output terminal signal through holes are arranged in the same row, and the first data input and output terminal signal through holes are arranged in the same row. Any data input/output signal through-hole in the group of data input/output signal through-holes does not belong to the same column as any data input/output signal through-hole in the second group of data input/output signal through-holes, and There is one column spaced between the column where the fifth data input and output terminal signal through holes are located and the column where the third data input and output terminal signal through holes are located, and the second data input and output terminal signal through holes and the fifth data input terminal are located Two ground signal through holes are provided between the output signal through holes, and two power supply signal through holes are provided between the third data input and output signal through holes and the eighth data input and output signal through holes. .
  25. 根据权利要求22所述的处理器芯片,其中,所述第一组数据输入输出端信号通孔位于所述第一边区和所述第三边区,所述第二组数据输入输出端信号通孔位于所述第二边区和所述第四边区,其中,所述第二数据输入输出端信号通孔与所述第八数据输入输出端信号通孔位于同一行设置,所述第一组数据输入输出端信号通孔中的任一数据输入输出端信号通孔与所述第二组数据输入输出端信号通孔中的任一数据输入输出端信号通孔均不属于同一列,且所述第五数据输入输出端信号通孔与所述第三数据输入输出端信号通孔位于相邻两列,所述第二数据输入输出端信号通孔与所述第八数据输入输出端信号通孔之间设置两个电源端信号通孔。The processor chip according to claim 22, wherein the first group of data input and output terminal signal through holes are located in the first side area and the third side area, and the second group of data input and output terminal signal through holes are located in the first side area and the third side area. The holes are located in the second side area and the fourth side area, wherein the second data input and output terminal signal through holes and the eighth data input and output terminal signal through holes are located in the same row, and the first group of data Any data input and output signal through holes in the input and output signal through holes and any data input and output signal through holes in the second group of data input and output signal through holes do not belong to the same column, and the The fifth data input and output terminal signal through holes and the third data input and output terminal signal through holes are located in two adjacent columns, the second data input and output terminal signal through holes and the eighth data input and output terminal signal through holes Two power supply signal through holes are provided between them.
  26. 根据权利要求22所述的处理器芯片,其中,所述第一组数据输入输出端信号通孔位于所述第一边区和所述第三边区,所述第二组数据输入输出端信号通孔中的所述第五数据输入输出端信号通孔位于所述第一边区和所述第三边区,所述第二组数据输入输出端信号通孔中的所述第六数据输入输出端信号通孔、所述第七数据输入输出端信号通孔和所述第八数据输入输出端信号通孔位于所述第二边区和所 述第四边区,其中,所述第三数据输入输出端信号通孔与所述第五数据输入输出端信号通孔位于同一列,所述第一组数据输入输出端信号通孔中的任一数据输入输出端信号通孔与所述第二组数据输入输出端信号通孔中的任一数据输入输出端信号通孔均不属于同一行,且所述第二数据输入输出端信号通孔与所述第八数据输入输出端信号通孔位于相邻两行,所述第三数据输入输出端信号通孔与所述第五数据输入输出端信号通孔之间设置两个电源端信号通孔。The processor chip according to claim 22, wherein the first group of data input and output terminal signal through holes are located in the first side area and the third side area, and the second group of data input and output terminal signal through holes are located in the first side area and the third side area. The fifth data input and output terminal signal through hole in the hole is located in the first side area and the third side area, and the sixth data input and output terminal in the second group of data input and output terminal signal through holes The signal through hole, the seventh data input and output terminal signal through hole and the eighth data input and output terminal signal through hole are located in the second side area and the The fourth side area, wherein the third data input and output terminal signal through holes and the fifth data input and output terminal signal through holes are located in the same column, and any one of the first group of data input and output terminal signal through holes The data input and output signal through holes do not belong to the same row as any of the data input and output signal through holes in the second group of data input and output signal through holes, and the second data input and output signal through holes are not in the same row as the second data input and output signal through holes. The eighth data input and output terminal signal through holes are located in two adjacent rows, and two power supply terminal signal through holes are provided between the third data input and output terminal signal through holes and the fifth data input and output terminal signal through holes. .
  27. 一种POP封装组件,其中,包括:A POP packaging component, including:
    如权利要求14-26任意一项所述的处理器芯片;以及The processor chip according to any one of claims 14-26; and
    与所述处理器芯片垂直堆叠封装的第一芯片。A first chip packaged vertically stacked with the processor chip.
  28. 根据权利要求27所述的POP封装组件,其中,所述第一芯片为DRAM芯片。The POP package assembly according to claim 27, wherein the first chip is a DRAM chip.
  29. 一种电子设备,其中,包括权利要求14-26任意一项所述的处理器芯片。 An electronic device, including the processor chip according to any one of claims 14-26.
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