WO2023217277A1 - Package structure, processor chip, pop package assembly and electronic device - Google Patents

Abstract

A package structure, a processor chip, a POP package assembly and an electronic device. The package structure comprises a substrate, wherein the substrate has a peripheral area, which comprises first through fourth peripheral areas that are sequentially connected; signal through holes arranged in multiple rows and multiple columns are distributed in each of the first through fourth peripheral areas; and conductors are provided in the signal through holes. Signal through holes arranged in multiple rows and multiple columns are provided in each peripheral area of a substrate, such that more signal lines are led out, thereby being conducive to multiplying the data access bandwidth for a processor.

Description

Packaging structures, processor chips, POP packaging components and electronic equipment

priority information

[Correction 13.06.2023 under Rule 91]
This application requests priority for the patent application with patent application number 2022105210246 submitted to the State Intellectual Property Office of China on May 12, 2022, and the patent application with patent application number 202310533654X submitted to the State Intellectual Property Office of China on May 11, 2023. rights and interests, and is incorporated herein by reference in its entirety.

Technical field

This application relates to the field of chip technology, specifically to packaging structures, processor chips, POP packaging components and electronic equipment.

Background technique

Low Power Double Rate Synchronous Dynamic Random Access Memory (LPDDR) has been widely used in various electronic devices, especially in power-constrained mobile devices. The traditional JEDEC (Solid State Circuit Technology Association) 496ball POP (vertically stacked package) pinmap (chip pinmap) for LPDDR can only provide 4 access channels on the package of DRAM chip (dynamic random access memory chip). For example, there are currently three pinmaps for LPDDR chips for POP type packaging, namely MO-273 and MO-317A for LPDDR4 and MO-344 for LPDDR5. The DRAM package sizes corresponding to these three pinmaps are 15mm. *15mm, 14mm*14mm and 14mm*12.4mm. However, these three pinmaps only provide 4 DRAM channels, and can only support a maximum data bandwidth of 64bits.

Contents of the invention

In one aspect of the present application, the present application provides a packaging structure. According to an embodiment of the present application, the packaging structure includes: a substrate having a peripheral area, the peripheral area including a first side area, a second side area, a third side area and a fourth side area connected in sequence, the first side area being The side area, the second side area, the third side area and the fourth side area have signal through holes arranged in multiple rows and columns, and copper pillars are provided in the signal through holes.

In another aspect of the present application, the present application provides a processor chip. According to an embodiment of the present application, the processor chip includes a packaging structure. The packaging structure includes: a substrate, the substrate has a peripheral area, the peripheral area includes a first side area, a second side area, a third side area and a fourth side area connected in sequence, the first side area, the second side area The side area, the third side area and the fourth side area have signal through holes arranged in multiple rows and columns, and copper pillars are provided in the signal through holes.

In another aspect of the present application, the present application provides a POP packaging component. According to an embodiment of the present application, the POP package component includes: a processor chip and a first chip that is vertically stacked and packaged with the processor chip. The processor chip includes a package structure. The packaging structure includes: a substrate, the substrate has a peripheral area, the peripheral area includes a first side area, a second side area, a third side area and a fourth side area connected in sequence, the first side area, the second side area The side area, the third side area and the fourth side area have signal through holes arranged in multiple rows and columns, and copper pillars are provided in the signal through holes.

In another aspect of the present application, the present application provides an electronic device. According to an embodiment of the present application, the electronic device includes the aforementioned processor chip. The processor chip includes a package structure. The packaging structure includes: a substrate, the substrate has a peripheral area, the peripheral area includes a first side area, a second side area, a third side area and a fourth side area connected in sequence, the first side area, the second side area The side area, the third side area and the fourth side area have signal through holes arranged in multiple rows and columns, and copper pillars are provided in the signal through holes.

Description of the drawings

The above and/or additional aspects and advantages of the present application will become apparent and readily understood from the description of the embodiments in conjunction with the following drawings, in which:

Figure 1 is a schematic diagram of the packaging structure in one embodiment of the present application;

Figure 2 is a schematic diagram of a packaging structure in another embodiment of the present application;

Figure 3 is a schematic diagram of the packaging structure in yet another embodiment of the present application;

Figure 4 is a schematic diagram of the packaging structure in yet another embodiment of the present application;

Figure 5 is a schematic diagram of a processor chip in another embodiment of the present application;

Figure 6 is a schematic diagram of a POP packaging component in yet another embodiment of the present application.

Detailed ways

The solution of the present application will be explained below with reference to examples. Those skilled in the art will understand that the following examples are only used to illustrate the present application and should not be regarded as limiting the scope of the present application. If specific techniques or conditions are not specified in the examples, the techniques or conditions described in literature in the field or product instructions will be followed.

The present application will be described below with reference to specific embodiments. It should be noted that these embodiments are only descriptive and do not limit the present application in any way.

In one aspect of the present application, the present application provides a packaging structure. According to an embodiment of the present application, with reference to Figures 1 to 4, the packaging structure includes: a substrate 10, the substrate 10 has a peripheral area, and the peripheral area includes a first side area 11, a second side area 12, and a third side area that are connected in sequence. 13 and the fourth side area 14, the first side area 11, the second side area 12, the third side area 13 and the fourth side area 14 have signal via holes 20 arranged in multiple rows and columns, and conductors are arranged in the signal via holes 20. In one embodiment, the conductors may be copper posts, or other conductive materials known in the art. Therefore, the packaging structure can meet the outlet requirements of more signals by arranging multiple rows and columns of signal through holes 20 in the peripheral areas on all four sides of the substrate 10 , thereby doubling the memory access bandwidth of the chip. As a non-limiting example, the memory access bandwidth of a chip using this packaging structure can reach 128 bits.

It should be noted that the chip (such as application processor AP chip) package is connected to the pins of the DRAM chip (dynamic random access memory chip) through the through-hole (TIV) array of the package structure for data input and output. The AP chip package structure has A plurality of data channels are used to transmit data, and each data channel includes a plurality of through holes arranged in an array. Taking an AP chip with a 64-bit data channel as an example, each channel includes 16 data signals TIV + 7 CA signals (address signals) TIV, that is, a total of 23 TIVs. Different channels transmit data in the same form, but the transmitted data signals are different. For example, when transmitting data in parallel, one channel transmits the data in the first data packet, and the second channel transmits the data in the second data packet. .

According to the embodiment of the present application, with reference to FIGS. 1 to 4 , the signal vias 20 located in the second side area 12 and the fourth side area 14 are arranged in three rows (there is no special requirement for the specific number of columns. Those skilled in the art can determine the number of columns according to the number of the chip. The size and other actual conditions can be flexibly selected, and there are no restrictions here.) The signal through holes 20 located in the first side area 11 and the third side area 13 are arranged in at least two columns (there are no special requirements for the specific number of rows, and those skilled in the art can Flexible selection is made according to the actual situation such as the size of the chip, and there are no restrictions here). In some preferred embodiments, the signal vias 20 located in the first side area 11 and the third side area 13 are arranged in three columns. In this way, the higher memory access bandwidth requirements of the chip can be achieved and the outlet requirements of more signals can be met; if more rows of signal vias are set in the first side area and the third side area, signal via holes will be correspondingly formed. The waste will also occupy more area of the substrate, affecting the routing of the chip substrate and signals; if there are less than three columns, it will be relatively difficult to meet the routing requirements of the signal through holes, which is not conducive to the realization of the chip for higher memory. Access bandwidth requirements.

According to an embodiment of the present application, referring to FIGS. 1 to 4 , the signal via 20 includes a data input and output terminal signal via (DQ) 21 , wherein two adjacent data input and output terminal signal vias (DQ) located in the same row or column are There is at least one non-data input and output signal through hole between the holes 21 (that is, other signal through holes except the data input and output signal through holes 21).

Further, in some embodiments, referring to Figures 1 to 4, there is at least one non-data input and output signal through hole between the two adjacent data input and output signal through holes 21 located in the same row or column, The data input and output signal through holes 21 in this arrangement can be located at the junction of two adjacent side areas (ie, the junction of the first side area 11 and the second side area 12, the junction of the second side area 12 and the third side area 13, The data input and output signal through holes 21 are arranged at intervals at the junction of the third side area 13 and the fourth side area 14 and at the junction of the fourth side area 14 and the first side area 11 , and may also be located in a certain side area (i.e., the first side area). Area 11, second side area 12, third side area 13 and/or fourth side area 14) in the middle (i.e. at the junction of two non-adjacent side areas), the details are as follows:

In some specific embodiments, referring to FIG. 1 , there is at least one non-data input and output signal through hole between the two adjacent data input and output signal through holes 21 located in the same row or column. The data in this arrangement is The input and output signal through holes 21 are located in the middle of a certain side area (i.e., the first side area 11, the second side area 12, the third side area 13 and/or the fourth side area 14) (only the second side area 12 is taken as an example in Figure 1 ). Therefore, no matter where the data input and output terminal signal through holes 21 are located, at least one non-data input and output terminal signal through hole (such as a ground terminal) can be provided between two adjacent data input and output terminal signal through holes 21 The signal vias (VSS) 22) separate them to avoid crosstalk when transmitting signals between the signal vias 21 of different data input and output terminals that are relatively close to each other. Those skilled in the art can understand that in FIG. 4 , only the data input and output terminal signal through hole 21 in the above arrangement is located somewhere in the middle of the second side area 12 as an example. The first side area 11 , the third side area 13 and the fourth side area 14 In the above arrangement, at least part of the data input and output signal through holes 21 are located at the junction of two adjacent side areas. Of course, those skilled in the art can choose to arrange all the data input and output signal through holes 21 required by the above settings at the middle position of the first side area 11 , the middle position of the second side area 12 , and the middle position of the third side area 13 And the middle position of the fourth side area 14, or the middle position of one side area, any two side areas, or any three side areas.

In other specific embodiments, as shown in FIG. 2 , the junction of the first side area 11 and the second side area 12 includes a plurality of data input and output terminal signal through holes 21 , and the plurality of data input and output terminal signal through holes 21 are spaced apart. Setting, that is, there is at least one (take 1 in the figure as an example) non-data input and output signal through hole, such as grounding, between two adjacent data input and output signal through holes 21 located in the same row or column. terminal signal via (VSS) 22; the junction of the second side area 12 and the third side area 13 includes a plurality of data input and output terminal signal via holes 21, and the plurality of data input and output terminal signal via holes 21 are arranged at intervals, that is, located here There is at least one (one is taken as an example in the figure) non-data input and output signal through holes 21 between two adjacent data input and output signal through holes 21 in the same row or column, such as a ground signal through hole (VSS). )22; The junction of the third side area 13 and the fourth side area 14 includes a plurality of data input and output terminal signal through holes 21. The plurality of data input and output terminal signal through holes 21 are arranged at intervals, that is, the ones located in the same row or the same column are here. There is at least one non-data input and output signal through hole (one in the figure is taken as an example) between two adjacent data input and output signal through holes 21, such as a ground signal through hole (VSS) 22; the fourth side area The junction between 14 and the first side area 11 includes a plurality of data input and output signal through holes 21. The plurality of data input and output signal through holes 21 are arranged at intervals, that is, two adjacent data holes 21 are located in the same row or column. There is at least one non-data input and output signal through hole (one is taken as an example in the figure) between the input and output signal through holes 21 , such as a ground signal through hole (VSS) 22 . Therefore, the above non-data input and output terminal signal through holes are arranged in a manner that separates two adjacent data input and output terminal signal through holes 21 located in the same row or the same column, which can effectively reduce the risk of different data input and output at the junction. Crosstalk between terminal signal vias 21.

According to an embodiment of the present invention, referring to FIG. 1 , the signal via 20 includes at least one group of data input and output signal vias S1 , and at least one group of data input and output signal vias S1 includes three adjacent rows and three columns. And there are four data input and output terminal signal through holes 21 arranged in a diamond-shaped structure or a diamond-like structure. Therefore, the above-mentioned setting method is simple and easy to arrange, and can set up a relatively large number of data input and output signal through holes in a small area, effectively realizing more signal outgoing requirements, which in turn helps to exponentially increase the memory of the chip. Access bandwidth, while effectively increasing the signal through holes 21 between two adjacent data input and output ends (including two adjacent ones in the same row, two adjacent ones in the same column, or two adjacent ones diagonally). The spacing between them can more effectively reduce the crosstalk between the signal through holes 21 of different data input and output terminals at the junction. Among them, at least one group of data input and output signal through holes S1 can be located at the edge of the side area, that is, at the junction of two side areas (as shown in Figures 1 to 4), or can be arranged in a certain side area (i.e., the first side area). area 11, the second side area 12, the third side area 13 and/or the fourth side area 14) in the middle position (the second side area 12 in Figure 1), those skilled in the art can flexibly set it according to actual needs. In other words: at least one group of data input and output signal through holes S1 in any side area can be arranged near the middle of the first side area 11; or at least one group of data input and output signal through holes in all side areas. Holes S1 are all set at the junction of two adjacent side areas (as shown in Figures 1 to 3); or at least one group of data input and output signal through holes in any one side area, any two side areas, or any three side areas. S1 is set near the middle, and at least one group of data input and output signal through holes S1 in the remaining side areas is located at the junction of two adjacent side areas. Taking Figure 1 as an example, at least one group of data input ports in the second side area 12 The output signal through hole S1 is located in the middle of the side area, and at least one set of data input and output signal through holes S1 in the other three side areas is located at the junction of two adjacent side areas.

According to an embodiment of the present application, with reference to Figures 1 to 4, the signal through holes include a first group of data input and output terminal signal through holes and a second group of data input and output terminal signal through holes. The first group of data input and output terminal signal through holes The data signals used for transmission and the second group of data input and output terminal signal through holes are used for transmitting data signals of different data channels. The first group of data input and output terminal signal through holes include the first data input and output terminal signal through holes 211 and the third data input and output terminal signal through holes. The second data input and output terminal signal through hole 212, the third data input and output terminal signal through hole 213 and the fourth data input and output terminal signal through hole 214. The first data input and output terminal signal through holes 211 and the third data input and output terminal signal through holes 213 are located in the same row, and the second data input and output terminal signal through holes 212 and the fourth data input and output terminal signal through holes 214 are located in the same column. The second data input and output terminal signal through holes 212 and the first data input and output terminal signal through holes 211 are not in the same row, and the second data input and output terminal signal through holes 212 and the third data input and output terminal signal through holes 213 are not in the same row. . The fourth data input and output terminal signal through holes 214 and the first data input and output terminal signal through holes 211 are not in the same row, and the fourth data input and output terminal signal through holes 214 and the third data input and output terminal signal through holes 213 are not in the same row. . The second group of data input and output terminal signal through holes includes the fifth data input and output terminal signal through hole 215, the sixth data input and output terminal signal through hole 216, the seventh data input and output terminal signal through hole 217 and the eighth data input and output terminal. Signal via 218. The fifth data input and output terminal signal through hole 215 and the seventh data input and output terminal signal through hole 217 are located in the same row, and the sixth data input and output terminal signal through hole 216 and the eighth data input and output terminal signal through hole 218 are located in the same column. The sixth data input and output terminal signal through hole 216 and the fifth data input and output terminal signal through hole 215 are not in the same row, and the sixth data input and output terminal signal through hole 216 and the seventh data input and output terminal signal through hole 217 are not in the same row. . The eighth data input and output terminal signal through hole 218 and the fifth data input and output terminal signal through hole 215 are not in the same row, and the eighth data input and output terminal signal through hole 218 and the seventh data input and output terminal signal through hole 217 are not in the same row. . The above setting method is simple and easy to arrange. It can set up a relatively large number of data input and output signal through holes in a small area, and effectively enlarge the size of two adjacent ones (including two adjacent ones in the same row and the same column). The spacing between two adjacent or diagonally adjacent two data input and output terminal signal through holes 21 can effectively reduce the crosstalk between different data input and output terminal signal through holes 21 at the junction. .

Among them, as mentioned above, the first group of data input and output terminal signal through holes are used to transmit data signals and the second group of data input and output terminal signal through holes are used to transmit data signals of different data channels, that is, the first group of data input terminals is used to transmit data signals. The output signal through holes and the second group of data input and output signal through holes are located in different signal channels. Further, the first data input and output terminal signal through holes 211, the second data input and output terminal signal through holes 212, the third data input and output terminal signal through holes 213 and the fourth data input and output terminal signal through holes in the first group of data input and output terminal signal through holes. The data input and output signal through holes 214 are located in the same signal channel and can be used to transmit the same data signal or different data signals. Those skilled in the art can flexibly choose according to the actual situation; similarly, the second group Among the data input and output terminal signal through holes, the fifth data input and output terminal signal through hole 215, the sixth data input and output terminal signal through hole 216, the seventh data input and output terminal signal through hole 217 and the eighth data input and output terminal signal through hole. The same signal channel of hole 218 can be used to transmit the same data signal or different data signals. Those skilled in the art can flexibly choose according to the actual situation.

According to some embodiments of the present application, with reference to Figures 1 to 4, the first data input and output terminal signal through hole 211, the second data input and output terminal signal through hole 212, the third data input and output terminal signal through hole 213 and the fourth data input and output terminal signal through hole 211. The data input and output terminal signal through holes 214 are distributed in three adjacent rows and three columns. In this way, the first data input and output terminal signal through holes 211, the second data input and output terminal signal through holes 212, and the third data input and output terminal signal through holes 214. The connection between the hole 213 and the fourth data input and output terminal signal through hole 214 can form a diamond-shaped structure or a diamond-like structure. In some specific embodiments, the first data input and output terminal signal through hole 211 and the second data input and output terminal The signal through hole 212, the third data input and output terminal signal through hole 213 and the fourth data input and output terminal signal through hole 214 can be arranged counterclockwise or clockwise (counterclockwise is used as an example in the drawing); the fifth data The input and output terminal signal through holes 215, the sixth data input and output terminal signal through holes 216, the seventh data input and output terminal signal through holes 217 and the eighth data input and output terminal signal through holes 218 are distributed in three adjacent rows and three columns. In this way, the connection of the fifth data input and output terminal signal through hole 215, the sixth data input and output terminal signal through hole 216, the seventh data input and output terminal signal through hole 217 and the eighth data input and output terminal signal through hole 218 can be formed. A diamond-shaped structure or a diamond-like structure. In some specific embodiments, the fifth data input and output terminal signal through hole 215, the sixth data input and output terminal signal through hole 216, the seventh data input and output terminal signal through hole 217 and the eighth data input and output terminal signal through hole 217. The data input and output signal through holes 218 can be arranged counterclockwise or clockwise (counterclockwise is used as an example in the figure). In this way, the above-mentioned arrangement of multiple data input and output terminal signal through holes can provide a relatively large number of data input and output terminal signal through holes in a small area, and effectively increase the size of two adjacent ones (including the same two rows). Two adjacent ones, two adjacent ones in the same column or two adjacent ones diagonally) The spacing between the signal through holes 21 at the data input and output ends, thereby effectively reducing the crosstalk of the signals, and at the same time, on this basis This makes the arrangement of signal vias have certain rules, which is easy to set up and identify.

In some embodiments, as shown in Figures 2 to 4, the above-mentioned first group of data input and output terminal signal through holes and the second group of data input and output terminal signal through holes are located at the junction of two adjacent side areas, that is, located on the first side. The junction of area 11 and the second side area 12, the junction of the second side area 12 and the third side area 13, the junction of the third side area 13 and the fourth side area 14, and the junction of the fourth side area 14 and the first side area 11 In this way, as mentioned above, the arrangement of the plurality of data input and output signal through holes in the first group of data input and output signal through holes and the second group of data input and output signal through holes can be smaller. A relatively large number of data input and output signal through holes are provided within the area, and two adjacent ones (including two adjacent ones in the same two rows, two adjacent ones in the same column, or two adjacent ones diagonally opposite) are effectively enlarged. Three situations) The spacing between the data input and output terminal signal through holes 21 can effectively reduce the crosstalk of signals. Therefore, when the above-mentioned first group of data input and output terminal signal through holes and the second group of data input and output terminal signal through holes are located At the junction of two adjacent side areas, not only can the crosstalk of signals at the junction of two adjacent side areas be effectively reduced, but a larger number of data input and output signal through holes 21 can also be provided in a limited area to meet more needs. The signals are routed out, which in turn helps to exponentially increase the memory access bandwidth of the chip.

According to some embodiments of the present application, referring to Figures 2 to 4, the first data input and output terminal signal through hole 211, the second data input and output terminal signal through hole 212, the third data input and output terminal signal through hole 213 and the fourth data input and output terminal signal through hole 211. A ground signal through hole (VSS) 22 is provided in the middle of the data input and output terminal signal through hole 214. That is, as mentioned above, the first data input and output terminal signal through hole 211, the second data input and output terminal signal through hole 212, The connection between the third data input and output terminal signal through hole 213 and the fourth data input and output terminal signal through hole 214 can form a diamond-shaped structure or a diamond-like structure, and the center of the diamond structure or diamond-like structure has a ground signal through hole ( VSS) 22. In this way, the ground signal through hole (VSS) 22 is provided here, which can effectively reduce the size of the first data input and output terminal signal through hole 211, the second data input and output terminal signal through hole 212, and the third data input and output port. The crosstalk between the terminal signal through hole 213 and the fourth data input and output terminal signal through hole 214; the fifth data input and output terminal signal through hole 215, the sixth data input and output terminal signal through hole 216, the seventh data input and output terminal signal through hole 215, and the seventh data input and output terminal signal through hole 215. A ground signal through hole (VSS) 22 is provided in the middle of the terminal signal through hole 217 and the eighth data input and output terminal signal through hole 218. That is, as mentioned above, the fifth data input and output terminal signal through hole 215, the sixth data input and output terminal signal through hole 215 and the sixth data input and output terminal signal through hole 218. The connection of the input and output terminal signal through holes 216, the seventh data input and output terminal signal through holes 217 and the eighth data input and output terminal signal through holes 218 can form a rhombus structure or a rhombus-like structure, and the center of the rhombus structure or rhombus-like structure There is a ground signal through hole (VSS) 22. In this way, the ground signal through hole (VSS) 22 provided here is used for grounding, which is equivalent to setting up signal isolation between the two data input and output signal through holes 21. The structure can better isolate the signals transmitted by the signal through holes 21 of the two data input and output terminals that are close to each other to avoid signal crosstalk, that is, it can effectively reduce the signal through holes 215 of the first and fifth data input and output terminals. Crosstalk of signals between the sixth data input and output terminal signal through hole 216, the seventh data input and output terminal signal through hole 217, and the eighth data input and output terminal signal through hole 218.

According to the embodiment of the present application, the signal through holes at the junction of two adjacent side areas in the packaging structure can be arranged as follows:

According to some embodiments of the present application, referring to Figure 2, the first group of data input and output signal through holes are located in the first side area 11 and the third side area 13 (that is, the first side area 11 and the third side area 13 are both provided with There is at least one first group of data input and output terminal signal through holes. Two are taken as an example in Figure 2. A first group of data input and output terminal signals are respectively provided at both ends of the first side area 11 and both ends of the third side area 13. through holes), the second group of data input and output terminal signal through holes are located in the second side area 12 and the fourth side area 14 (that is to say, the second side area 12 and the fourth side area 14 are both provided with at least one second group of data input and output terminal signals. Through holes, two are taken as an example in Figure 2. A second group of data input and output signal through holes are respectively provided at both ends of the second side area 12 and both ends of the fourth side area 14), wherein the first data input and output The terminal signal through hole 211, the third data input and output terminal signal through hole 213 and the eighth data input and output terminal signal through hole 218 are located in the same row, and the second data input and output terminal signal through hole 212 and the fifth data input and output terminal signal through hole 212 are arranged in the same row. The through holes 215 and the seventh data input and output terminal signal through holes 217 are located in the same row. Any one of the data input and output terminal signal through holes 21 in the first group of data input and output terminal signal through holes is the same as the second group of data input and output terminal signal through holes. None of the data input and output terminal signal through holes 21 in the through holes belong to the same column, and there is one column between the column where the fifth data input and output terminal signal through hole 215 is located and the column where the third data input and output terminal signal through hole 213 is located. , two ground signal through holes (VSS) 22 are provided between the second data input and output terminal signal through hole 212 and the fifth data input and output terminal signal through hole 215, and the third data input and output terminal signal through hole 213 is connected to the third data input and output terminal signal through hole 213. Two power supply signal through holes (VDD) 24 are provided between the eight data input and output terminal signal through holes 218. In this way, the ground terminal signal through hole (VSS) 22 provided here is used for grounding, which is equivalent to providing a signal isolation structure between the two data input and output terminal signal through holes 21, which can better isolate the two data input and output terminals. The signals transmitted by the data input and output terminal signal through holes 21 are isolated to avoid signal crosstalk, that is, the number of signals in the first group of data input and output terminal signal through holes and the second group of data input and output terminal signal through holes can be further effectively reduced. Crosstalk of signals between the data input and output terminal signal through holes 21; the setting of the power supply terminal signal through hole (VDD) 24 can connect the third data input and output terminal signal through hole 213 and the eighth data input and output terminal signal through hole 218 The distance between them is increased to avoid the undesirable phenomenon of signal crosstalk when transmitting signals.

Further, as shown in FIG. 2 , taking the junction of the first side area 11 and the second side area 12 as an example, the first row of the first side area 11 (that is, the row where the sixth data input and output terminal signal through hole 216 is located) Three ground signal vias (VSS) 22 may also be provided in the row where the sixth data input and output terminal signal vias 216 are located, and there are also between the sixth data input and output terminal signal vias 216 and the first side area 11 Two ground signal through holes (VSS) 22 can also be further provided. In this way, the ground signal through holes (VSS) 22 are used for grounding, which is equivalent to setting up signal isolation between the two data input and output signal through holes 21. The structure can better isolate the signals transmitted by the signal through holes 21 of the two data input and output terminals that are close to each other, and can further effectively reduce the crosstalk of the signals between the signal through holes 21 of the multiple data input and output terminals. . In addition, the junctions of other two adjacent side areas can also be arranged as described above, in order to better reduce the crosstalk of signals between the multiple data input and output terminal signal through holes 21. The specific details are not too many. description of.

According to other embodiments of the present application, referring to Figure 3, the first group of data input and output signal through holes are located in the first side area 11 and the third side area 13 (that is, the first side area 11 and the third side area 13 are both At least one first group of data input and output terminal signal through holes are provided. Two are taken as an example in Figure 3. One first group of data input and output ports are respectively provided at both ends of the first side area 11 and both ends of the third side area 13. terminal signal through holes), the second group of data input and output terminal signal through holes are located in the second side area 12 and the fourth side area 14 (that is to say, the second side area 12 and the fourth side area 14 are both provided with at least one second group of data input Output signal through holes, two are taken as an example in Figure 3. A second set of data input and output signal through holes are respectively provided at both ends of the second side area 12 and both ends of the fourth side area 14), wherein the second The data input and output terminal signal through holes 212 and the eighth data input and output terminal signal through holes 218 are located in the same row. Any data input and output terminal signal through holes 21 in the first group of data input and output terminal signal through holes are in the same row as the second group of data input and output terminal signal through holes 218 . None of the data input and output signal through holes 21 belongs to the same column, and the fifth data input and output signal through hole 215 and the third data input and output signal through hole 213 are located adjacent to each other. In two columns, two power supply signal through holes (VDD) 24 are provided between the second data input and output terminal signal through hole 212 and the eighth data input and output terminal signal through hole 218. In this way, the power terminal signal through hole (VDD) 24 provided here can widen the distance between the third data input and output terminal signal through hole 213 and the eighth data input and output terminal signal through hole 218, thereby preventing their transmission. The undesirable phenomenon of signal crosstalk occurs when the signal is transmitted, that is to say, the setting of the power supply signal through hole (VDD) 24 can further effectively reduce the signal through holes of the first group of data input and output terminals and the signal of the second group of data input and output terminals. Crosstalk of signals between multiple data input and output terminal signal through holes 21 in the through holes.

Further, as shown in FIG. 3 , taking the junction of the first side area 11 and the second side area 12 as an example, the first row of the first side area 11 (that is, the row where the sixth data input and output terminal signal through hole 216 is located) and the second row (that is, the row where the fifth data input and output terminal signal through holes 216 are located) can also be provided with three ground signal through holes (VSS) 22 respectively, and the row where the sixth data input and output terminal signal through holes 216 are located, Moreover, a ground signal through hole (VSS) 22 can also be further provided between the sixth data input and output terminal signal through hole 216 and the first side area 11. In this way, the above ground signal through hole (VSS) 22 is provided to ground. The terminal signal through hole (VSS) 22 is used for grounding, which is equivalent to setting a signal isolation structure between the two data input and output terminal signal through holes 21, which can better connect the signals of the two data input and output terminals that are close to each other. The signals transmitted by the holes 21 are isolated, which can further effectively reduce the crosstalk of signals between the multiple data input and output terminal signal through holes 21 . In addition, the junctions of other two adjacent side areas can also be arranged as described above, in order to better reduce the crosstalk of signals between the multiple data input and output terminal signal through holes 21. The specific details are not too many. description of.

According to some embodiments of the present application, referring to Figure 4, the first group of data input and output signal through holes are located in the first side area 11 and the third side area 13 (that is, the first side area 11 and the third side area 13 are both At least one first group of data input and output terminal signal through holes are provided. Two are taken as an example in Figure 4. One first group of data input and output ports are respectively provided at both ends of the first side area 11 and both ends of the third side area 13. end signal through hole), the fifth data input and output end signal through hole 215 in the second group of data input and output end signal through holes is located in the second side area 12 and the fourth side area 14, and the second group of data input and output end signal through holes The sixth data input and output terminal signal through hole 216, the seventh data input and output terminal signal through hole 217 and the eighth data input and output terminal signal through hole 218 are located in the second side area 12 and the fourth side area 14, wherein the third data input The output signal through hole 213 and the fifth data input and output signal through hole 215 are located in the same column. Any data input and output signal through hole 21 in the first group of data input and output signal through holes is in the same row as the second group of data input and output signal through holes. None of the data input/output signal vias 21 belong to the same row, and the second data input/output signal via 212 and the eighth data input/output signal via 218 are located in two adjacent rows, Two power supply signal through holes (VDD) 24 are provided between the third data input and output terminal signal through hole 213 and the fifth data input and output terminal signal through hole 215. In this way, the ground terminal signal through hole (VSS) 22 provided here is used for grounding, which is equivalent to providing a signal isolation structure between the two data input and output terminal signal through holes 21, which can better isolate the two data input and output terminals. The signals transmitted by the data input and output terminal signal through holes 21 are isolated to avoid signal crosstalk, that is, the number of signals in the first group of data input and output terminal signal through holes and the second group of data input and output terminal signal through holes can be further effectively reduced. Crosstalk of signals between the data input and output terminal signal through holes 21; the setting of the power supply terminal signal through hole (VDD) 24 can connect the third data input and output terminal signal through hole 213 and the eighth data input and output terminal signal through hole 218 The distance between them is increased to avoid the undesirable phenomenon of signal crosstalk when transmitting signals.

Further, as shown in Figure 4, taking the junction of the first side area 11 and the second side area 12 as an example, in the first side area 11, the second data input and output terminal signal through hole 212 is located in the column and above it. Three ground signal through holes (VSS) 22 are provided, as well as the column where the first data input and output signal through hole 211 is located, and three ground signal through holes (VSS) 22 can be provided above it, as well as a fifth data input and output. A ground signal through hole (VSS) 22 can be provided in the column where the terminal signal through hole 215 is located and above it. In this way, the above ground terminal signal through hole (VSS) 22 is used for grounding, which is equivalent to two data input and output terminals. A signal isolation structure is set up between the signal through holes 21, which can better isolate the signals transmitted by the two data input and output terminal signal through holes 21 that are close to each other and avoid signal crosstalk, that is, the ground signal through hole (VSS) The arrangement of 22 can further effectively reduce the crosstalk of signals between the multiple data input and output terminal signal through holes 21 . In addition, the junctions of other two adjacent side areas can also be arranged as described above, in order to better reduce the crosstalk of signals between the multiple data input and output terminal signal through holes 21. The specific details are not too many. description of.

According to the embodiment of the present application, the arrangement of signal through holes of the data input and output terminals in the three specific embodiments listed above can be set in the same packaging structure, that is, at the junction of the first side area 11 and the second side area 12 The arrangement of the data input and output terminal signal through holes 21, the arrangement of the data input and output terminal signal through holes 21 at the junction of the second side area 12 and the third side area 13, the data at the junction of the third side area 13 and the fourth side area 14 The arrangement of the input and output signal through holes 21 and the arrangement of the data input and output signal through holes 21 at the junction of the fourth side area 14 and the first side area 11 can be the same (as shown in Figure 2 to Figure 4), or they can be different. That is, you can choose any of the above three arrangements, or in other words, the arrangement of the data input and output signal through holes 21 at the junction of the first side area 11 and the second side area 12, the arrangement of the second side area 12 and the third side area. The arrangement of the data input and output terminal signal through holes 21 at the junction of the third side area 13 and the fourth side area 14, the arrangement of the data input and output terminal signal through holes 21 at the junction of the third side area 13 and the fourth side area 14, the fourth side area 14 and the first side area The arrangement of the signal through holes 21 at the data input and output terminals at the junction 11 is independent of each other.

According to the embodiment of the present application, in the above package structure, in addition to the aforementioned arrangement of the data input and output terminal signal through holes 21, the ground terminal signal through holes (VSS) 22 and the power terminal signal through holes (VDD) 24 , there are no special requirements for the arrangement of signal through holes and the specific signal outlets corresponding to different signal through holes. Those skilled in the art can flexibly choose according to the actual situation, and there are no restrictions here.

In another aspect of the present application, the present application provides a processor chip. According to an embodiment of the present application, with reference to FIG. 5 , the processor chip 1000 includes the previously described packaging structure 1100 . Further, as shown in FIG. 4 , the processor chip further includes a surface disposed on the surface of the packaging structure 1100 The plurality of storage particles 1200 and the plastic sealing layer 1300 located on the side of the storage particles 1200 away from the packaging structure 1100 can provide good protection for the storage particles 1200 and the packaging structure 1100 . As a result, the processor chip can achieve exponentially increased memory access bandwidth. As a non-limiting example, the memory access bandwidth of a processor chip using this packaging structure can reach 128 bits. Those skilled in the art can understand that the processor chip has all the features and advantages of the previously described packaging structure, which will not be described in detail here.

The above-mentioned plastic sealing layer 1300 may be epoxy resin or other plastic sealing materials suitable for chip packaging. In some specific embodiments, the processor chip is an application processor chip (AP chip).

In another aspect of the present application, the present application provides a POP packaging component. According to an embodiment of the present application, referring to FIG. 6 , the POP package component 1 includes: the aforementioned processor chip 1000; and a first chip 2000 vertically stacked and packaged with the processor chip 1000. As a result, the POP package component has a front processor chip and can achieve exponentially increased memory access bandwidth. As a non-limiting example, the memory access bandwidth of a processor chip using this packaging structure can reach 128 bits.

Specifically, the above-mentioned first chip may be a DRAM chip (dynamic random access memory chip), and the processor chip and the DRAM chip are vertically stacked and packaged to form a POP package component.

In another aspect of the present application, the present application provides an electronic device. According to an embodiment of the present application, the electronic device includes the aforementioned processor chip. As a result, the electronic device has better performance.

Among them, there are no special requirements for the specific types of electronic devices. Those skilled in the art can flexibly choose according to actual needs. For example, the specific types of electronic devices include but are not limited to mobile phones, iPads, computers, TVs and other electronic devices that can apply processor chips. .

The terms "first" and "second" in this article are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of this application, "plurality" means two or more than two, unless otherwise explicitly and specifically limited.

In the description of this specification, reference to the terms "one embodiment," "some embodiments," "an example," "specific examples," or "some examples" or the like means that specific features are described in connection with the embodiment or example. , structures, materials or features are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine different embodiments or examples and features of different embodiments or examples described in this specification unless they are inconsistent with each other.

Although the embodiments of the present application have been shown and described above, it can be understood that the above-mentioned embodiments are illustrative and cannot be understood as limitations of the present application. Those of ordinary skill in the art can make modifications to the above-mentioned embodiments within the scope of the present application. The embodiments are subject to changes, modifications, substitutions and variations.

Claims (29)

1. A packaging structure, including:

   A substrate having a peripheral area, the peripheral area including a first side area, a second side area, a third side area and a fourth side area connected in sequence, the first side area, the second side area, the third side area The three side areas and the fourth side area have signal via holes arranged in multiple rows and columns, and conductors are arranged in the signal via holes.
2. The package structure of claim 1, wherein the conductor is a copper pillar.
3. The package structure according to claim 1, wherein the signal through holes located in the second side area and the fourth side area are arranged in three rows, and the signal through holes located in the first side area and the third side area are arranged in three rows. The signal through holes are arranged in at least two rows.
4. The packaging structure according to claim 1, wherein the signal through holes located in the first side area and the third side area are arranged in three columns.
5. The package structure according to claim 3, wherein the signal through holes include data input and output signal through holes, and there is at least one between two adjacent data input and output signal through holes located in the same row or the same column. Non-data input and output signal through holes.
6. The packaging structure according to any one of claims 1 to 5, wherein the signal vias include at least one group of data input and output signal vias, and the at least one group of data input and output signal vias includes Four data input and output terminal signal through holes are distributed in three adjacent rows and three columns and arranged in a rhombus or rhombus-like structure.
7. The packaging structure according to any one of claims 1 to 6, wherein the signal through holes include a first group of data input and output terminal signal through holes and a second group of data input and output terminal signal through holes, and the first A group of data input and output terminal signal through holes are used to transmit data signals and the second group of data input and output terminal signal through holes are used to transmit data signals of different data channels. The first group of data input and output terminal signal through holes are used to transmit data signals. The second group of data input and output signal through holes meet at least one of the following conditions:

   The first group of data input and output terminal signal through holes includes a first data input and output terminal signal through hole, a second data input and output terminal signal through hole, a third data input and output terminal signal through hole and a fourth data input and output terminal signal through hole. through holes, the first data input and output terminal signal through holes and the third data input and output terminal signal through holes are located in the same row, the second data input and output terminal signal through holes and the fourth data input and output terminal The signal through holes are located in the same column and are not in the same row as the first data input and output terminal signal through holes and the third data input and output terminal signal through holes;

   The second group of data input and output terminal signal through holes includes a fifth data input and output terminal signal through hole, a sixth data input and output terminal signal through hole, a seventh data input and output terminal signal through hole and an eighth data input and output terminal signal through hole. through holes, the fifth data input and output terminal signal through holes and the seventh data input and output terminal signal through holes are located in the same row, the sixth data input and output terminal signal through holes and the eighth data input and output terminal The signal through holes are located in the same column and are not in the same row as the fifth data input and output terminal signal through holes and the seventh data input and output terminal signal through holes.
8. The packaging structure according to claim 7, wherein the first group of data input and output terminal signal through holes and the second group of data input and output terminal signal through holes are located at the junction of two adjacent side areas.
9. The packaging structure according to claim 7, wherein the first group of data input and output terminal signal through holes and the second group of digital The input and output signal through holes meet at least one of the following conditions:

   The first data input and output terminal signal through holes, the second data input and output terminal signal through holes, the third data input and output terminal signal through holes and the fourth data input and output terminal signal through holes are distributed in the same direction. There are three adjacent rows and three columns, arranged in a rhombus or rhombus-like structure;

   The fifth data input and output terminal signal through holes, the sixth data input and output terminal signal through holes, the seventh data input and output terminal signal through holes and the eighth data input and output terminal signal through holes are distributed in the same direction. Three adjacent rows and three columns form a rhombus or rhombus-like structure arrangement.
10. The package structure according to claim 9, wherein the first data input and output terminal signal through holes, the second data input and output terminal signal through holes, the third data input and output terminal signal through holes and the A ground signal through hole is provided in the middle of the fourth data input and output terminal signal through hole, the fifth data input and output terminal signal through hole, the sixth data input and output terminal signal through hole, the seventh data input terminal signal through hole, One of the ground terminal signal through holes is disposed between the output terminal signal through hole and the eighth data input and output terminal signal through hole.
11. The package structure according to claim 9, wherein the first group of data input and output terminal signal through holes are located in the first side area and the third side area, and the second group of data input and output terminal signal through holes Located in the second side area and the fourth side area, wherein the first data input and output terminal signal through hole, the third data input and output terminal signal through hole and the eighth data input and output terminal signal through hole Located in the same row, the second data input and output terminal signal through holes, the fifth data input and output terminal signal through holes, and the seventh data input and output terminal signal through holes are located in the same row, and the first group Any data input and output signal through holes in the data input and output signal through holes and any data input and output signal through holes in the second group of data input and output signal through holes do not belong to the same column, and all data input and output signal through holes do not belong to the same column. There is one column spaced between the column where the fifth data input and output terminal signal through holes are located and the column where the third data input and output terminal signal through holes are located, and the second data input and output terminal signal through holes and the fifth data input and output terminal signal through holes are separated by one column. Two ground terminal signal through holes are provided between the terminal signal through holes, and two power terminal signal through holes are provided between the third data input and output terminal signal through holes and the eighth data input and output terminal signal through holes.
12. The package structure according to claim 9, wherein the first group of data input and output terminal signal through holes are located in the first side area and the third side area, and the second group of data input and output terminal signal through holes Located in the second side area and the fourth side area, wherein the second data input and output terminal signal through holes and the eighth data input and output terminal signal through holes are located in the same row, and the first group of data input Any data input and output signal through holes in the output signal through holes and any data input and output signal through holes in the second group of data input and output signal through holes do not belong to the same column, and the third group of data input and output signal through holes does not belong to the same column. The fifth data input and output terminal signal through holes and the third data input and output terminal signal through holes are located in two adjacent columns, and the second data input and output terminal signal through holes are between the eighth data input and output terminal signal through holes. Two power supply signal through holes are provided between them.
13. The package structure according to claim 9, wherein the first group of data input and output terminal signal through holes are located in the first side area and the third side area, and the second group of data input and output terminal signal through holes The fifth data input and output terminal signal through holes are located in the first side area and the third side area, and the sixth data input and output terminal signals in the second group of data input and output terminal signal through holes are located in the first side area and the third side area. The through hole, the seventh data input and output terminal signal through hole and the eighth data input and output terminal signal through hole are located in the second side area and the fourth side area, wherein the third data input and output terminal signal The through hole is located in the same column as the fifth data input and output terminal signal through hole, so Any data input and output terminal signal through holes in the first group of data input and output terminal signal through holes and any data input and output terminal signal through holes in the second group of data input and output terminal signal through holes do not belong to the same rows, and the second data input and output terminal signal through holes and the eighth data input and output terminal signal through holes are located in two adjacent rows, and the third data input and output terminal signal through holes and the fifth data input terminal signal through holes are located in two adjacent rows. Two power supply signal through holes are provided between the output signal through holes.
14. A processor chip, which includes the packaging structure of claim 1.
15. The processor chip of claim 14, wherein the conductor is a copper pillar.
16. The processor chip according to claim 14, wherein the signal through holes located in the second side area and the fourth side area are arranged in three rows, and the signal via holes located in the first side area and the third side area The signal via holes are arranged in at least two rows.
17. The processor chip according to claim 14, wherein the signal through holes located in the first side area and the third side area are arranged in three columns.
18. The processor chip according to claim 16, wherein the signal vias include data input and output signal vias, and there are at least two adjacent data input and output signal vias located in the same row or column. A non-data input and output signal via.
19. The processor chip according to any one of claims 14 to 18, wherein the signal vias include at least one group of data input and output signal vias, and the at least one group of data input and output signal vias It includes four data input and output signal through holes distributed in three adjacent rows and three columns and arranged in a rhombus or rhombus-like structure.
20. The processor chip according to any one of claims 14 to 19, wherein the signal vias include a first group of data input and output terminal signal via holes and a second group of data input and output terminal signal via holes, and the third group of data input and output terminal signal via holes A group of data input and output terminal signal through holes are used to transmit data signals, and the second group of data input and output terminal signal through holes are used to transmit data signals of different data channels. The first group of data input and output terminal signal through holes are used to transmit data signals of different data channels. and the second group of data input and output signal through holes meet at least one of the following conditions:

    The first group of data input and output terminal signal through holes includes a first data input and output terminal signal through hole, a second data input and output terminal signal through hole, a third data input and output terminal signal through hole and a fourth data input and output terminal signal through hole. through holes, the first data input and output terminal signal through holes and the third data input and output terminal signal through holes are located in the same row, the second data input and output terminal signal through holes and the fourth data input and output terminal The signal through holes are located in the same column and are not in the same row as the first data input and output terminal signal through holes and the third data input and output terminal signal through holes;

    The second group of data input and output terminal signal through holes includes a fifth data input and output terminal signal through hole, a sixth data input and output terminal signal through hole, a seventh data input and output terminal signal through hole and an eighth data input and output terminal signal through hole. through holes, the fifth data input and output terminal signal through holes and the seventh data input and output terminal signal through holes are located in the same row, the sixth data input and output terminal signal through holes and the eighth data input and output terminal The signal through holes are located in the same column and are not in the same row as the fifth data input and output terminal signal through holes and the seventh data input and output terminal signal through holes.
21. The processor chip according to claim 20, wherein the first group of data input and output terminal signal through holes and the second group of data input and output terminal signal through holes are located at the junction of two adjacent side areas.
22. The processor chip according to claim 20, wherein the first group of data input and output terminal signal through holes and the second group of data input and output terminal signal through holes satisfy at least one of the following conditions:

    The first data input and output terminal signal through holes, the second data input and output terminal signal through holes, the third data input and output terminal signal through holes and the fourth data input and output terminal signal through holes are distributed in the same direction. There are three adjacent rows and three columns, arranged in a rhombus or rhombus-like structure;

    The fifth data input and output terminal signal through holes, the sixth data input and output terminal signal through holes, the seventh data input and output terminal signal through holes and the eighth data input and output terminal signal through holes are distributed in the same direction. Three adjacent rows and three columns form a rhombus or rhombus-like structure arrangement.
23. The processor chip according to claim 22, wherein the first data input and output terminal signal through holes, the second data input and output terminal signal through holes, the third data input and output terminal signal through holes and the There is a ground signal through hole in the middle of the fourth data input and output terminal signal through hole, the fifth data input and output terminal signal through hole, the sixth data input and output terminal signal through hole, the seventh data input and output terminal signal through hole, and the seventh data input and output terminal signal through hole. One of the ground terminal signal through holes is disposed between the input and output terminal signal through holes and the eighth data input and output terminal signal through holes.
24. The processor chip according to claim 22, wherein the first group of data input and output terminal signal through holes are located in the first side area and the third side area, and the second group of data input and output terminal signal through holes are located in the first side area and the third side area. Holes are located in the second side area and the fourth side area, wherein the first data input and output terminal signal through holes, the third data input and output terminal signal through holes and the eighth data input and output terminal signal through holes The holes are arranged in the same row, the second data input and output terminal signal through holes, the fifth data input and output terminal signal through holes and the seventh data input and output terminal signal through holes are arranged in the same row, and the first data input and output terminal signal through holes are arranged in the same row. Any data input/output signal through-hole in the group of data input/output signal through-holes does not belong to the same column as any data input/output signal through-hole in the second group of data input/output signal through-holes, and There is one column spaced between the column where the fifth data input and output terminal signal through holes are located and the column where the third data input and output terminal signal through holes are located, and the second data input and output terminal signal through holes and the fifth data input terminal are located Two ground signal through holes are provided between the output signal through holes, and two power supply signal through holes are provided between the third data input and output signal through holes and the eighth data input and output signal through holes. .
25. The processor chip according to claim 22, wherein the first group of data input and output terminal signal through holes are located in the first side area and the third side area, and the second group of data input and output terminal signal through holes are located in the first side area and the third side area. The holes are located in the second side area and the fourth side area, wherein the second data input and output terminal signal through holes and the eighth data input and output terminal signal through holes are located in the same row, and the first group of data Any data input and output signal through holes in the input and output signal through holes and any data input and output signal through holes in the second group of data input and output signal through holes do not belong to the same column, and the The fifth data input and output terminal signal through holes and the third data input and output terminal signal through holes are located in two adjacent columns, the second data input and output terminal signal through holes and the eighth data input and output terminal signal through holes Two power supply signal through holes are provided between them.
26. The processor chip according to claim 22, wherein the first group of data input and output terminal signal through holes are located in the first side area and the third side area, and the second group of data input and output terminal signal through holes are located in the first side area and the third side area. The fifth data input and output terminal signal through hole in the hole is located in the first side area and the third side area, and the sixth data input and output terminal in the second group of data input and output terminal signal through holes The signal through hole, the seventh data input and output terminal signal through hole and the eighth data input and output terminal signal through hole are located in the second side area and the The fourth side area, wherein the third data input and output terminal signal through holes and the fifth data input and output terminal signal through holes are located in the same column, and any one of the first group of data input and output terminal signal through holes The data input and output signal through holes do not belong to the same row as any of the data input and output signal through holes in the second group of data input and output signal through holes, and the second data input and output signal through holes are not in the same row as the second data input and output signal through holes. The eighth data input and output terminal signal through holes are located in two adjacent rows, and two power supply terminal signal through holes are provided between the third data input and output terminal signal through holes and the fifth data input and output terminal signal through holes. .
27. A POP packaging component, including:

    The processor chip according to any one of claims 14-26; and

    A first chip packaged vertically stacked with the processor chip.
28. The POP package assembly according to claim 27, wherein the first chip is a DRAM chip.
29. An electronic device, including the processor chip according to any one of claims 14-26.