CN109509737B - Electronic packaging component and circuit layout structure - Google Patents
Electronic packaging component and circuit layout structure Download PDFInfo
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- CN109509737B CN109509737B CN201710833412.7A CN201710833412A CN109509737B CN 109509737 B CN109509737 B CN 109509737B CN 201710833412 A CN201710833412 A CN 201710833412A CN 109509737 B CN109509737 B CN 109509737B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
Abstract
The invention discloses an electronic packaging component and a circuit layout structure. The electronic packaging component is provided with a plurality of grounding welding balls and a plurality of signal welding balls which are arranged corresponding to a configuration point array. The configuration point array comprises a plurality of grounding configuration points for bearing grounding solder balls, a plurality of signal configuration points for bearing signal solder balls and a plurality of vacant configuration points. The configuration point array is formed by arranging a plurality of ground configuration points, a plurality of signal configuration points and a plurality of vacancy configuration points in m columns along a first direction and n rows along a second direction, and a plurality of ground configuration points and a plurality of vacancy configuration points in the 1 st row or the 1 st column at the outermost side of the configuration point array are alternately arranged.
Description
Technical Field
The present invention relates to an electronic package component and a circuit layout structure, and more particularly, to an electronic package component and a circuit layout structure using ball grid array packaging technology.
Background
An integrated circuit package member formed by ball grid array packaging techniques is provided with an array of solder ball pads on a bottom surface. In addition, the circuit board usually includes a plurality of pads corresponding to the ball pad array and a plurality of traces respectively connected to the pads. When the integrated circuit package component is mounted on the circuit board, the integrated circuit package component is pasted and welded on the corresponding welding pad through the welding ball pad, and signal connection is established between the integrated circuit package component and other elements arranged on the circuit board through a plurality of wires connected with the welding pad.
Generally, some of the plurality of solder ball pads are grounded through the traces to provide ground shielding for other traces and solder ball pads used for signal transmission, thereby providing a preferred signal transmission quality between the ic package and other components. As the size of integrated circuit package components becomes smaller, the number of pads provided in a unit area of a circuit board becomes denser.
Although the pad and the trace are located on the same layer of the circuit board, the signal transmission loss or the signal coupling can be reduced, because the distance between the pads arranged on the circuit board is smaller and smaller, only the pad located at the first circle or the second circle of the outermost periphery of the pad array is allowed to be directly connected to another element through the trace on the same layer. Other pads located inside the pad array must be connected to another element through conductive vias (conductive via) and traces disposed on the inner or bottom layer of the circuit board.
When the integrated circuit packaging component transmits signals through the lower layer wiring, the wiring which is positioned on the lower layer and used for transmitting the signals is difficult to achieve complete grounding shielding, and therefore the requirement of high-frequency signal transmission is met.
Disclosure of Invention
The present invention is directed to an electronic package and a circuit layout structure thereof, which are provided to overcome the disadvantages of the prior art, and to increase the line space utilization rate of a circuit board and to take into account the signal transmission quality.
In order to solve the above technical problems, one technical solution of the present invention is to provide an electronic package component having a plurality of ground solder balls and a plurality of signal solder balls disposed corresponding to a configuration point array. The configuration point array comprises a plurality of grounding configuration points for bearing grounding solder balls, a plurality of signal configuration points for bearing signal solder balls and a plurality of vacant configuration points, the configuration point array is formed by arranging the grounding configuration points, the signal configuration points and the vacant configuration points into m columns along a first direction and n rows along a second direction, and the grounding configuration points and the vacant configuration points in the 1 st row or the 1 st column at the outermost side of the configuration point array are alternately arranged.
Another technical solution adopted by the present invention is to provide a circuit layout structure formed in a circuit board to cooperate with the electronic package component. The circuit layout structure comprises a welding pad array, wherein the welding pad array is arranged in a welding pad configuration area on one surface of the circuit board, and comprises a plurality of grounding welding pads, a plurality of signal welding pads and a plurality of welding-pad-free areas. The pad array is formed by arranging a plurality of ground pads, a plurality of signal pads and a plurality of non-pad areas into m rows along a first direction and n rows along a second direction, and the plurality of ground pads and the plurality of non-pad areas in the 1 st row or the 1 st column at the outermost side of the pad array are alternately arranged.
One of the advantages of the electronic package component and the circuit layout structure provided by the invention is that the solder pad array and each signal line corresponding to the ball grid array on the circuit board can be completely shielded by the grounding line through the technical scheme of alternately arranging a plurality of grounding configuration points and a plurality of vacancy configuration points in at least one outermost row or one outermost column of the ball grid array of the electronic package component.
For a better understanding of the features and technical content of the present invention, reference should be made to the following detailed description of the invention and accompanying drawings, which are provided for purposes of illustration and description only and are not intended to limit the invention.
Drawings
Fig. 1 is a partial bottom view of an electronic package according to an embodiment of the invention.
Fig. 2 is a schematic top view of a circuit layout structure according to an embodiment of the invention.
Description of reference numerals:
Solder ball placement area 10
Configuring a dot array 100
Null allocation point 100R
Grounding solder ball 110G
First row configuration point group N1
Second row configuration point group N2
Lower layer wiring configuration point group M1
Lower layer wiring configuration point group M2
Top layer routing pad group a1
Lower wiring pad group a2
Non-pad region 210R
Top layer circuit layer L1
Lower wiring layer L2
First signal line S1
First ground line G1
Second signal line S2
Second ground line G2
First direction D1
Second direction D2
Detailed Description
Referring to fig. 1, fig. 1 is a partial top view of an electronic package component according to an embodiment of the invention. The electronic package component 1 of the present embodiment is formed by a semiconductor chip, which may be an integrated circuit chip, a dynamic random access memory chip or other semiconductor elements, through a ball grid array packaging technique.
The bottom of the electronic package component 1 has a solder ball placement area 10, and the solder ball placement area 10 has a placement point array 100 therein. In addition, the electronic package component 1 has a ball grid array (not numbered) including a plurality of ground solder balls 110G and a plurality of signal solder balls 110S disposed corresponding to the arrangement point array 100. After the electronic package component 1 is disposed on the circuit board, the grounding solder balls 110G of the electronic package component 1 are electrically grounded.
In the present embodiment, the arrangement point array 100 includes a plurality of signal arrangement points 100S for carrying signal solder balls 110S, a plurality of ground arrangement points 100G for carrying ground solder balls 110G, and a plurality of vacant arrangement points 100R. Note that, in the embodiment of the present invention, no solder ball is provided on the vacant site 100R.
As shown in fig. 1, the layout point array 100 is a matrix array, and a plurality of ground layout points 100G, a plurality of signal layout points 100S, and null layout points 100R are arranged in m rows along a first direction D1 and n rows along a second direction D2. In other words, m × n configuration points are included in the configuration point array 100.
In the present embodiment, a plurality of ground arrangement points 100G and a plurality of dummy arrangement points 100R are alternately arranged in the 1 st row or the 1 st column located at the outermost side of the arrangement point array 100. In the embodiment of fig. 1, the description will be made showing the arrangement manner of the plurality of ground arrangement points 100G and the plurality of dummy arrangement points 100R in the 1 st column (m is 1) located at the outermost side of the arrangement point array 100. In other words, in the arrangement point array 100 of the present embodiment, there is a portion of the outermost row 1 where no solder ball is disposed. Further, in the outermost 1 st column (m is 1) of the arrangement point array 100, one vacant arrangement point 100R is provided between every two adjacent ground arrangement points 100G.
Therefore, the outer contour of the ball grid array (excluding the null allocation points 100R) of this embodiment will have a wave structure. It is to be noted that the plurality of signal arrangement points 100S and the plurality of dummy arrangement points 100R in the 2 nd column (m is 2) located at the outermost side of the arrangement point array 100 are also alternately arranged. As shown in fig. 1, one vacant arrangement point 100R is provided between every two adjacent signal arrangement points 100S in the 2 nd column (m is 2) located at the outermost side of the arrangement point array 100.
Further, one vacancy distribution point 100R in the 1 st column (m is 1) located on the outermost side of the distribution point array 100 is positioned on the same row as one vacancy distribution point 100R in the 2 nd column (m is 2) located on the outermost side of the distribution point array 100. In other words, in the present embodiment, the plurality of vacancy distribution points 100R in the outermost 1 st column and the plurality of vacancy distribution points 100R in the 2 nd column may be aligned with each other in the second direction D2, respectively.
As shown in FIG. 1, the configuration point array 100 includes a first row of configuration point groups N1. The first row of pads group N1 includes a plurality of ground pads 100G and a plurality of signal pads 100S alternately disposed, and two signal pads 100S are disposed between every two adjacent ground pads 100G. In other words, the plurality of ground pads 100G and the plurality of signal pads 100S located in one row (e.g., row 1 in fig. 1) of the pad array 100 are alternately arranged in the second direction D2. Thus, one grounding solder ball 110G is disposed before and after each two adjacent signal solder balls 110S.
In addition, the configuration point array 100 includes a second row of configuration point group N2. As shown in fig. 1, the second row layout point group N2 includes a plurality of adjacent null layout points 100R, a plurality of signal layout points 100S adjacent to each other, and at least one ground layout point 100G, and the plurality of signal layout points 100S adjacent to each other are located between one of the null layout points 100R and at least one of the ground layout points 100G.
In the present embodiment, two null configuration points 100R, four signal configuration points 100S and a ground configuration point 100G are sequentially disposed in another row (e.g., row 2 in fig. 1) of the configuration point array 100. In addition, one of the signal pads 100S in the second row pad group N2 and one of the ground pads 100G in the first row pad group N1 are in the same column. In addition, at least one ground node 100G of the second row node group N2 is in the same row as one of the ground nodes 100G of the first row node group N1.
For example, the grounding solder ball 110G and the signal solder ball 110S are disposed on the row 1, the column 4 of the configuration point array 100 and the row 2, the column 4 of the configuration point array 100, respectively. The 1 st row and 7 th column of the configuration dot array 100 and the 2 nd row and 7 th column of the configuration dot array are provided with the ground solder balls 110G.
Furthermore, the dot array 100 of the present embodiment is composed of a plurality of first row dot groups N1 and a plurality of second row dot groups N2, which are alternately arranged in the first direction, and each of the second row dot groups N2 is disposed between every two adjacent first row dot groups N1.
The layout dot array 100 includes a lower layout dot group M1, and the lower layout dot group M1 includes a plurality of ground layout dots 100G, a plurality of signal layout dots 100S, and a plurality of dummy layout dots 100R. In the lower layer wiring arrangement point group M1, the ratio of the number of signal arrangement points 100S to the number of ground arrangement points 100G is 2: 1, and the ratio of the number of signal allocation points 100S to the number of null allocation points 100R is also 2: 1.
corresponding to the arrangement of the first row of pads group N1, the two ground pads 100G and the two signal pads 100S in the lower layer of wiring pad group M1 are located in the same row (e.g., row 1 of the pad array), and the two signal pads 100S are located between two adjacent ground pads 100G.
In addition, corresponding to the arrangement of the second row allocation point group N2, the two signal allocation points 100S and the two dummy allocation points 100R are located in the same row (e.g. the 2 nd row of the allocation point array), and the two dummy allocation points 100R are adjacent to each other.
It should be noted that, since the vacant positions 100R are disposed on the outermost rows 1 and 2 of the arrangement point array 100, when the electronic package component 1 is disposed on the circuit board, the ground solder balls 110G and the signal solder balls 110S on the ground arrangement points 100G and the signal arrangement points 100S of the lower wiring arrangement point group M1 can be connected to the corresponding connection points through the circuits on the surface of the circuit board, and the signal solder balls 110S and the circuits connected thereto can be completely shielded by the ground solder balls 110G and the circuits connected thereto.
In the embodiment of fig. 1, the lower wiring arrangement point group M1 includes a plurality of ground arrangement points 100G, a plurality of signal arrangement points 100S, and a plurality of dummy arrangement points 100R in the 1 st to 4 th columns located at the outermost sides of the arrangement point array 100. That is, the ground solder balls 110G and the signal solder balls 110S in the 1 st to 4 th columns (m is 1-4) at the outermost side of the ball grid array may be connected to the circuit on the surface layer of the circuit board. Thus, compared with the ball grid array of the electronic package component 1 in the prior art, the utilization rate of the circuit space on the surface of the circuit board can be improved.
The distribution point array 100 of the embodiment of the invention further includes a lower layer of wiring distribution point group M2. The lower wiring layout point group M2 includes a plurality of ground layout points 100G and a plurality of signal layout points 100S. The ratio of the number of signal configuration points 100S to the number of ground configuration points 100G is 2: 1, and the plurality of ground pads 100G in the lower wiring pad group M2 are located in the same column, such as the 7 th column shown in fig. 1.
When the electronic package component 1 is disposed on a circuit board, the ground pads 100G and the ground balls 110G and the signal balls 110S on the lower layer of the wiring pad group M2 are connected to corresponding contacts through the conductive vias of the circuit board and the traces on the lower layer of the circuit board. The conductive via may be a conductive blind via or a conductive through via. The circuit of the lower layer of the circuit board can be a circuit embedded in the circuit board or a circuit positioned at the lowest layer of the circuit board.
It should be noted that, when the electronic package component 1 is mounted on a circuit board, the ground solder balls 110G and the circuits connected thereto in the top-layer wiring layout point group M1 can shield the signal solder balls 110S and the circuits connected thereto on the signal layout points 100S.
In addition, the ground solder balls 110G and the lines connected thereto on the ground pads 100G of the lower layer wiring pad group M2 can also shield the signal solder balls 110S and the lines connected thereto on the signal pads 100S to prevent the lines from being coupled to each other. Therefore, the requirement of high-frequency signal transmission can be met under the condition of not increasing the circuit complexity of the circuit board.
Referring to fig. 2, a partial top view of a circuit layout structure according to an embodiment of the invention is shown. The circuit layout structure 200 is formed in a circuit board 2 to be matched with the electronic package component 1 as described above. It is noted that, in the present embodiment, one surface of the circuit board 2 is provided with a pad configuration area 20, and the pad configuration area 20 can be divided into a peripheral area 20A and an inner area 20B.
The circuit layout structure 200 includes a pad array 210, a top circuit layer L1 connected to the pad array 210, and a bottom circuit layer L2 connected to the pad array 210. The top circuit layer L1 and the pad array 210 are located on the same side of the circuit board 2, and the lower circuit layer L2 and the pad array 210 are located on two opposite sides of the circuit board 2. Therefore, the circuit layout structure 200 further includes a plurality of conductive vias (not shown), so that the pad array 210 and the lower circuit layer L2 can be connected through the conductive vias.
As shown in fig. 2, the pad array 210 is disposed in the pad configuration region 20 and includes a plurality of ground pads 210G, a plurality of signal pads 210S, and a plurality of non-pad regions 210R. Further, the pad array 210 corresponds to the arrangement point array 100 and the ball grid array of the electronic package component 1. Similar to the arrangement point array 100, the pad array 210 is formed by a plurality of ground pads 210G, a plurality of signal pads 210S, and a plurality of pad-free regions 210R arranged in m rows along a first direction D1 and n rows along a second direction D2.
The pad array 210 of the present embodiment includes a top routing pad group a1 located in the peripheral region 20A. The top routing pad group a1 of the present embodiment includes a plurality of ground pads 210G, a plurality of signal pads 210S, and a plurality of non-pad regions 210R in the outermost 1 st column (m ═ 1) to 4 th column (m ═ 4) of the pad array 210. The pad-free region 210R corresponds to the vacancy configuration point 100R of the electronic package component 1, and no pad is disposed. In the top routing pad group a1, the ratio of the number of signal pads 210S to the number of ground pads 210G is 2: 1, and the ratio of the number of signal pads 210S to the number of non-pad regions 210R is 2: 1.
furthermore, in the present embodiment, the plurality of ground pads 210G and the plurality of non-pad areas 210R in the outermost 1 st column (m is 1) of the pad array 210 are alternately disposed. As shown in fig. 2, in the outermost 1 st column of the pad array 210, one pad-free region 210R is disposed between every two adjacent ground pads 210G.
In addition, in the present embodiment, the signal pads 210S and the non-pad areas 210R in the outermost 2 nd column (m is 2) of the pad array 210 are alternately disposed, and one non-pad area 210R is disposed between every two adjacent signal pads 210S. In detail, the non-pad area 210R in the outermost 1 st column of the pad array 210 and one non-pad area 210R in the outermost 2 nd column of the pad array 210 are located in the same row, such as the 2 nd and 4 th rows shown in fig. 2.
The top routing pad group a1 further includes a plurality of signal pads 210S located in the outermost 3 rd column of the pad array 210, and a plurality of signal pads 210S and a plurality of ground pads 210G located in the outermost 4 th column of the pad array 210 and alternately arranged.
The number of pads in the outermost 1 st row of the pad array 210 is smaller than the number of pads in the 3 rd column, so that there is a wider pitch between every two adjacent ground pads 210G in the 1 st column and every two adjacent signal pads 210S in the 2 nd column.
In addition, in the embodiment, the plurality of ground pads 210G and the plurality of signal pads 210S in the top routing pad group a1 are all connected to the top circuit layer L1. Further, the non-pad region 210R in the outermost row 1 of the pad array 210 can be used as a circuit layout region for disposing the top circuit layer L1.
As shown in fig. 2, the top circuit layer L1 includes a plurality of first signal circuits S1 and a plurality of first ground circuits G1. The first signal lines S1 are respectively connected to the signal pads 210S in the top routing pad group a1, and the first ground lines G1 are respectively connected to the ground pads 210G in the top routing pad group a 1. A non-routing area is defined between every two adjacent first signal lines S1 and first ground lines G1.
In other words, no other first signal line S1 passes through the region between every two nearest neighboring first signal lines S1 and first ground line G1. Therefore, one first ground line G1 is provided beside each first signal line S1, thereby providing a complete ground shield for each first signal line S1.
As can be seen from fig. 2, the first signal line S1 connected to the signal pad 210S located at row 1, column 3 and the first ground line G1 connected to the ground pad 210G located at row 1, column 4 pass through the non-pad region 210R.
Accordingly, the signal pads 210S and the ground pads 210G in the 1 st to 4 th rows of the pad array 210 can be electrically connected to another component on the circuit board 2 through the top circuit layer L1. Therefore, in the pad array 210 according to the embodiment of the present invention, the arrangement of the non-pad region 210R can effectively improve the line space utilization rate of the surface of the circuit board 2.
In addition, the pad array 210 further includes a lower routing pad group a2 located in an inner region 20B of the pad layout area 20. The lower routing pad group a2 includes a plurality of signal pads 210S and a plurality of ground pads 210G. In this embodiment, the ratio between the number of signal pads 210S and the number of ground pads 210G is 2: 1, and the plurality of ground pads 210G in the lower routing pad group a2 are arranged in the same row in the first direction D1.
The signal pads 210S and the ground pads 210G in the lower wiring pad group a2 are connected to the lower wiring layer L2 through a plurality of conductive vias, respectively.
The lower wiring layer L2 includes a plurality of second signal wirings S2 and a plurality of second ground wirings G2. The second signal lines S2 are respectively connected to the signal pads 210S in the lower wiring pad group a 2. In addition, the second ground lines G2 are connected to the ground pads 210G in the lower wiring pad group a2, respectively. Similar to the top layer L1, a non-routing area is defined between every two adjacent second signal lines S2 and second ground lines G2, so that each second ground line G2 can shield the second signal line S2 adjacent thereto.
In summary, in the circuit layout structure 200 according to the embodiment of the invention, for each signal pad 210S, at least one ground pad 210G is located in a plurality of pads that are immediately adjacent to the signal pad 210S, or is immediately adjacent to one ground line G1 (or G2).
Specifically, regarding the plurality of ground pads 210G and signal pads 210S located in the peripheral region 20A, a pad located in the next row of the signal pad 210S (position coordinate m is 3, n is 3) is the ground pad 210G (position coordinate m is 4, n is 3) with the signal pad 210S (position coordinate m is 3, n is 3) as the center.
In the signal pad 210S located in the 3 rd column, 2 nd row (position coordinate m is 3, n is 2), the signal pad 210S (position coordinate m is 3, n is 2) is not a ground pad 210G, but one first ground line G1 connected to the ground pad 210G (position coordinate m is 4, n is 1) is routed near the signal pad 210S (position coordinate m is 3, n is 2).
Similarly, the same applies to the plurality of ground pads 210G and the plurality of signal pads 210S in the inner region 20B. The signal pad 210S (position coordinate m is 5, n is 2) and the other signal pad 210S (position coordinate m is 6, n is 2) are explained in detail below as an example. For the signal pad 210S (position coordinate m is 6, n is 2), among four pads located above, below, on, or to the left of the signal pad 210S (position coordinate m is 6, n is 2), at least one ground pad 210G (located in the 7 th column, 2 nd row (position coordinate m is 7, n is 2)).
In the other signal pad 210S (position coordinate m is 5, n is 2), the ground pad 210G is not provided in any of the four pads above, below, to the left, and to the right of the signal pad 210S (position coordinate m is 5, n is 2), but one second ground line G2 connected to the ground pad 210G (position coordinate m is 7, n is 1) is provided near the signal pad 210S (position coordinate m is 5, n is 2).
Accordingly, the circuit layout structure 200 of the embodiment of the invention can provide a complete ground shield for each of the signal pads 210S, the first signal line S1 and the second signal line S2.
Specifically, the circuit layout structure 200 according to the embodiment of the present invention can ensure that after each signal of the electronic package component 1 is transmitted to another component through the corresponding first signal line S1 (or the second signal line S2), the signal is returned from the first signal line S1 (or the second signal line S2) or the first ground line G1 (or the second ground line G2) adjacent thereto. That is, the first ground line G1 (or the second signal line S2) respectively adjacent to each of the first signal lines S1 (or the second signal line S2) is a return path of the signal.
In summary, one of the advantages of the present invention is that the electronic package component 1 and the circuit layout structure 200 corresponding to the electronic package component 1 provided by the present invention can make more rows or more columns of pads of the pad array 210 directly connect to the top circuit layer L1 by the technical scheme of "setting the vacant configuration points and the non-pad areas in at least the outermost row or the outermost column of the configuration point array 100 of the electronic package component 1 and the pad array of the circuit layout structure 200, respectively", so as to increase the utilization rate of the circuit space of the circuit board 2.
In addition, in the circuit layout structure 200 on the circuit board 2, in the top routing pad group a1, the plurality of ground pads 210G and the plurality of first ground lines G1 connected thereto are grounded, and the plurality of first ground lines G1 can completely shield all the signal pads 210S in the top routing pad group a1 and the first signal lines S1 connected thereto. Similarly, the plurality of ground pads 210G in the lower routing pad group a2 and the plurality of second ground lines G2 connected thereto are grounded, so that all the signal pads 210S in the lower routing pad group a2 and the second signal lines S2 connected thereto are shielded, thereby preventing interference during high frequency signal transmission.
That is, with the circuit layout structure 200 provided by the embodiment of the present invention, even if the number of the ground pads 210G is smaller than that of the signal pads 210S, a good ground shield can be provided for the signal pads 210S.
The disclosure is only a preferred embodiment of the invention and should not be taken as limiting the scope of the invention, which is defined by the appended claims.
Claims (10)
1. An electronic package member having a plurality of ground solder balls and a plurality of signal solder balls arranged corresponding to a configuration point array, wherein the configuration point array includes a plurality of ground configuration points for carrying the ground solder balls, a plurality of signal configuration points for carrying the signal solder balls, and a plurality of vacancy configuration points, the configuration point array is formed by arranging a plurality of the ground configuration points, a plurality of the signal configuration points, and a plurality of the vacancy configuration points into m columns along a first direction and n rows along a second direction, and a plurality of the ground configuration points and a plurality of the vacancy configuration points in the outermost 1 st row or the outermost 1 st column of the configuration point array are alternately arranged.
2. The electronic package component of claim 1, wherein a plurality of said ground configuration points and a plurality of said ground configuration points in an outermost column 1 of said configuration point array alternate, and one said vacancy configuration point is disposed between every two adjacent said ground configuration points.
3. The electronic package component according to claim 2, wherein a plurality of said signal arrangement points located in the outermost 2 nd column of said arrangement point array are alternately arranged with a plurality of said vacancy arrangement points, and one of said vacancy arrangement points located in the outermost 1 st column of said arrangement point array is in the same row as one of said vacancy arrangement points located in the outermost 2 nd column of said arrangement point array.
4. The electronic package component of claim 1, wherein the array of configuration points comprises:
a first row of configuration point groups, each of the first row of configuration point groups including a plurality of the ground configuration points and a plurality of the signal configuration points, which are alternately arranged, and two signal configuration points are arranged between every two adjacent ground configuration points; and
a second row configuration point group, the second row configuration point group comprising a plurality of adjacent vacancy configuration points, a plurality of signal configuration points adjacent to each other and at least one ground configuration point, and the plurality of signal configuration points adjacent to each other are located between one of the vacancy configuration points and at least one of the ground configuration points;
the configuration dot array is composed of a plurality of first row configuration dot groups and a plurality of second row configuration dot groups which are repeatedly and alternately arranged in the first direction, and each second row configuration dot group is arranged between every two adjacent first row configuration dot groups.
5. The electronic package according to claim 4, wherein at least one of the ground pads in the second row of pads is in the same column as one of the ground pads in the first row of pads.
6. A circuit layout structure formed in a circuit board to cooperate with the electronic package component of claim 1, wherein the circuit layout structure comprises a pad array disposed in a pad configuration region on one surface of the circuit board, the pad array comprises a plurality of ground pads, a plurality of signal pads and a plurality of non-pad regions, the pad array is formed by arranging the plurality of ground pads, the plurality of signal pads and the plurality of non-pad regions in m rows along a first direction and n rows along a second direction, and the plurality of ground pads and the plurality of non-pad regions in the outermost 1 st row or 1 st row of the pad array are alternately disposed.
7. The circuit layout structure of claim 6, wherein the pad array comprises a top routing pad group located in a peripheral region of the pad layout area, the top routing pad group comprising a plurality of ground pads, a plurality of signal pads, and a plurality of no pad regions, and in the top routing pad group, a ratio of the number of signal pads to the number of ground pads is 2: 1, and the ratio of the number of signal pads to the number of pad-free regions is 2: 1.
8. the circuit layout structure of claim 7, further comprising a top layer of lines, the top layer of lines being located on the same side of the circuit board as the top group of routing pads, wherein the top layer of lines comprises:
the first signal circuits are respectively connected with the signal welding pads in the top layer wiring welding pad group; and
the first grounding circuits are respectively connected with the grounding welding pads in the top layer wiring welding pad group, wherein a non-wiring area is defined between every two adjacent first signal circuits and the first grounding circuits.
9. The circuit layout structure of claim 8, wherein the pad array further comprises a lower routing pad group located in an inner region of the pad layout region, the lower routing pad group comprising a plurality of signal pads and a plurality of ground pads arranged in a plurality of rows along the second direction, a ratio between the number of signal pads and the number of ground pads being 2: 1, and a plurality of the ground pads in the lower routing pad group are arranged in the same column in the first direction.
10. The circuit layout structure of claim 9, further comprising a lower circuit layer, wherein the lower circuit layer and the lower routing pad group are respectively located on two opposite sides of the circuit board, and wherein the lower circuit layer comprises:
a plurality of second signal lines respectively connected to the plurality of signal pads in the lower wiring pad group; and
and a plurality of second grounding circuits respectively connected with the plurality of grounding pads in the lower-layer wiring pad group, wherein a non-wiring area is defined between every two adjacent second signal circuits and the second grounding circuits.
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| CN201710833412.7A CN109509737B (en) | 2017-09-15 | 2017-09-15 | Electronic packaging component and circuit layout structure |
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| CN201710833412.7A CN109509737B (en) | 2017-09-15 | 2017-09-15 | Electronic packaging component and circuit layout structure |
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| CN109509737A CN109509737A (en) | 2019-03-22 |
| CN109509737B true CN109509737B (en) | 2020-09-08 |
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| CN112490219B (en) * | 2020-11-27 | 2022-05-03 | 海宁利伊电子科技有限公司 | Radiation-leakage-resistant conformal shielding SIP packaging structure |
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| CN1387256A (en) * | 2002-06-05 | 2002-12-25 | 威盛电子股份有限公司 | Crystal covered chip and crystal covered package substrate |
| CN1622315A (en) * | 2003-11-25 | 2005-06-01 | 国际商业机器公司 | High performance chip carrier substrate |
| CN2879422Y (en) * | 2005-10-11 | 2007-03-14 | 威盛电子股份有限公司 | Conducting cushion configuration of grid array package |
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| JP2006278805A (en) * | 2005-03-30 | 2006-10-12 | Elpida Memory Inc | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1387256A (en) * | 2002-06-05 | 2002-12-25 | 威盛电子股份有限公司 | Crystal covered chip and crystal covered package substrate |
| CN1622315A (en) * | 2003-11-25 | 2005-06-01 | 国际商业机器公司 | High performance chip carrier substrate |
| CN2879422Y (en) * | 2005-10-11 | 2007-03-14 | 威盛电子股份有限公司 | Conducting cushion configuration of grid array package |
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