CN221041109U - Package for converting ball grid array chip into flat leadless chip - Google Patents
Package for converting ball grid array chip into flat leadless chip Download PDFInfo
- Publication number
- CN221041109U CN221041109U CN202322016019.2U CN202322016019U CN221041109U CN 221041109 U CN221041109 U CN 221041109U CN 202322016019 U CN202322016019 U CN 202322016019U CN 221041109 U CN221041109 U CN 221041109U
- Authority
- CN
- China
- Prior art keywords
- chip
- welding spot
- welding
- pcb substrate
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000003466 welding Methods 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000004806 packaging method and process Methods 0.000 claims abstract description 17
- 230000017525 heat dissipation Effects 0.000 claims abstract description 12
- 230000002093 peripheral effect Effects 0.000 claims abstract description 8
- 239000003990 capacitor Substances 0.000 claims abstract description 6
- WBLJAACUUGHPMU-UHFFFAOYSA-N copper platinum Chemical compound [Cu].[Pt] WBLJAACUUGHPMU-UHFFFAOYSA-N 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 3
- 229910000679 solder Inorganic materials 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 2
- AGCPZMJBXSCWQY-UHFFFAOYSA-N 1,1,2,3,4-pentachlorobutane Chemical compound ClCC(Cl)C(Cl)C(Cl)Cl AGCPZMJBXSCWQY-UHFFFAOYSA-N 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
The utility model discloses a package for packaging a ball mould grid array chip into a flat pin-free chip, which comprises a PCB substrate, wherein flat pin-free packaging welding spots are arranged on the edge of the bottom surface of the PCB substrate, the flat pin-free packaging welding spots are used for functional connection of the chip, a chip heat dissipation welding spot is arranged in the middle of the bottom surface of the PCB substrate, the chip heat dissipation welding spot is used for grounding and dissipating heat of the chip, a welding spot array area is arranged on the top surface of the PCB substrate, and the welding spot array area is used for connecting the ball mould grid array chip; the periphery of the welding spot array area is provided with a filter capacitor welding spot and a protection element welding spot; the PCB substrate is provided with the chip heat dissipation welding spots, the functional welding spots of the flat leadless chip package are arranged on the edge of the substrate, and the filter capacitor welding spots and the protection element welding spots are arranged on the periphery of the chip, so that the peripheral circuit is simpler, the heat dissipation effect is better, the requirements of simplifying the PCB and the utilization of the space are met, the design space and the production efficiency are improved, and the precision of the requirements on the produced equipment is more relaxed.
Description
Technical Field
The utility model belongs to the technical field of chip packaging, and particularly relates to a package for packaging a ball grid array chip to a flat pin-free chip.
Background
The chip package structure is a housing for mounting a semiconductor integrated circuit chip, plays roles of placing, fixing, sealing, protecting the chip and enhancing the electrothermal performance, and is also a bridge for communicating the world inside the chip with an external circuit. At present, the packaging mode of the ball grid array chip is as follows: the contacts on the chip are wired to pins of the package housing which in turn establish connections with other devices through wires on the printed board. The chip can generate heat during working, and if the chip is poorly packaged, the heat dissipation of the chip can be affected, so that the chip is overheated, and the performance and the service life of the chip are affected; moreover, the processing cost is high, and the process efficiency is low.
Disclosure of utility model
The utility model provides a package for packaging a ball grid array chip into a flat pin-free chip, and aims to solve the technical problems of poor heat dissipation effect, limited design space, low production efficiency and high precision requirement on production equipment in the existing packaging mode.
In order to solve the technical problems, the technical scheme of the utility model is as follows: the utility model provides a package for packaging ball mould grid array chip changes flat leadless chip, includes PCB base plate, its characterized in that: the edge of the bottom surface of the PCB substrate is provided with a flat leadless packaging welding spot which is used for functional connection of chips, the middle part of the bottom surface of the PCB substrate is provided with a chip heat dissipation welding spot which is used for grounding and dissipating heat of the chips, the top surface of the PCB substrate is provided with a welding spot array area which is used for connecting with a ball grid array chip; and the periphery of the welding spot array area is provided with a filter capacitor welding spot and a protection element welding spot.
The technical scheme is further defined, and the structure of the PCB substrate comprises: the panel comprises a plurality of layers of panels, wherein a top panel and a bottom panel in the plurality of layers of panels are connected through copper-platinum wires.
The technical scheme is further defined, and the structure of the welding spot array area is as follows: the central welding spot is arranged in the middle of the welding spot array area, the peripheral welding spots are distributed on the periphery of the central welding spot, and the peripheral welding spots are close to the edge of the welding spot array area.
The utility model has the beneficial effects that: the middle part at PCB base plate bottom surface is equipped with chip heat dissipation solder joint, and chip function solder joint sets up on the limit portion of base plate, and in addition, filter capacitor solder joint and protection element solder joint set up at the chip periphery, and peripheral circuit is succinct more when designing the application like this, and the radiating effect is better, reaches the requirement of simplifying PCB and the utilization in space, is favorable to promoting design space and improvement production efficiency, and the equipment requirement precision to production is more loose.
Drawings
Fig. 1 is a schematic bottom view of a PCB substrate.
Fig. 2 is a schematic top view of a PCB substrate.
Fig. 3 is a cross-sectional view of a PCB substrate.
Detailed Description
As shown in fig. 1 and 2, a package for packaging a ball grid array chip into a flat leadless chip comprises a PCB substrate 1, wherein a flat leadless packaging welding spot 2 is arranged on the edge of the bottom surface of the PCB substrate, the flat leadless packaging welding spot is used for functional connection of the chip, a chip heat dissipation welding spot 3 is arranged in the middle of the bottom surface of the PCB substrate, the chip heat dissipation welding spot is used for grounding and dissipating heat of the chip, a welding spot array area 4 is arranged on the top surface of the PCB substrate, and the welding spot array area is used for connecting the ball grid array chip; a filter capacitor welding spot 5 and a protection element welding spot 6 are arranged on the top surface of the PCB substrate;
As shown in fig. 3, the structure of the PCB1 substrate: comprising a plurality of layers of panels, the top panel 101 and the bottom panel 102 of the plurality of layers of panels are connected by copper-platinum wires 103.
As shown in fig. 2, the structure of the solder joint array region: the central welding spot is arranged in the middle of the welding spot array area, peripheral welding spots are distributed on the periphery of the central welding spot, and the peripheral welding spots are close to the edge of the welding spot array area; the distribution mode of the center welding points is beneficial to heat dissipation and circuit connection.
Claims (3)
1. The utility model provides a package for packaging ball mould grid array chip changes flat leadless chip, includes PCB base plate, its characterized in that: the edge of the bottom surface of the PCB substrate is provided with a flat leadless packaging welding spot which is used for functional connection of chips, the middle part of the bottom surface of the PCB substrate is provided with a chip heat dissipation welding spot which is used for grounding and dissipating heat of the chips, the top surface of the PCB substrate is provided with a welding spot array area which is used for connecting with a ball grid array chip; and the periphery of the welding spot array area is provided with a filter capacitor welding spot and a protection element welding spot.
2. A package for packaging a ball grid array chip to a flat no-lead chip as defined in claim 1, wherein: the structure of the PCB substrate comprises: the panel comprises a plurality of layers of panels, wherein a top panel and a bottom panel in the plurality of layers of panels are connected through copper-platinum wires.
3. A package for packaging a ball grid array chip to a flat leadless chip as claimed in claim 1 or 2, wherein: the structure of the welding spot array area is as follows: the central welding spot is arranged in the middle of the welding spot array area, the peripheral welding spots are distributed on the periphery of the central welding spot, and the peripheral welding spots are close to the edge of the welding spot array area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322016019.2U CN221041109U (en) | 2023-07-29 | 2023-07-29 | Package for converting ball grid array chip into flat leadless chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322016019.2U CN221041109U (en) | 2023-07-29 | 2023-07-29 | Package for converting ball grid array chip into flat leadless chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN221041109U true CN221041109U (en) | 2024-05-28 |
Family
ID=91172681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322016019.2U Active CN221041109U (en) | 2023-07-29 | 2023-07-29 | Package for converting ball grid array chip into flat leadless chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN221041109U (en) |
-
2023
- 2023-07-29 CN CN202322016019.2U patent/CN221041109U/en active Active
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