CN220138315U

CN220138315U - High-density SiP module

Info

Publication number: CN220138315U
Application number: CN202322954506.3U
Authority: CN
Inventors: 彭勃; 郑茂; 杨进; 夏明赟
Original assignee: CETC 30 Research Institute
Current assignee: CETC 30 Research Institute
Priority date: 2023-11-02
Filing date: 2023-11-02
Publication date: 2023-12-05
Anticipated expiration: 2033-11-02

Abstract

The utility model relates to the technical field of packaging, and particularly discloses a high-density SiP module which comprises a plurality of groups of silicon substrates, ceramic tube shells, inner BGA solder balls and outer BGA solder balls, wherein the groups of silicon substrates are sequentially stacked from top to bottom, the ceramic tube shells are positioned below the groups of silicon substrates, the silicon substrates are used for connecting two adjacent layers of silicon substrates, the silicon substrates are close to one side of the ceramic tube shells, the inner BGA solder balls are arranged on the inner BGA solder balls of the ceramic tube shells, and the outer BGA solder balls are arranged on one side of the ceramic tube shells, which is far away from the silicon substrates. The utility model simplifies the design of the multi-layer step bonding finger and the embedded cavity structure of the bare chip in the prior art, thereby reducing the process implementation difficulty of the tube shell, shortening the processing period, obviously improving the production yield, reducing the cost of the tube shell, and having high integration level and high reliability.

Description

High-density SiP module

Technical Field

The utility model relates to the technical field of packaging, in particular to a high-density SiP module.

Background

The traditional high-reliability metal airtight ceramic package adopts a multi-step multi-cavity multi-layer wiring integrated ceramic tube shell package, wherein the ceramic tube shell is used as a package body and a wiring layer, and is designed to simultaneously consider multi-layer step bonding finger design, multi-layer high-speed wiring and multi-cavity structural design.

The patent with the application number of CN2018103405281 is named as a ceramic double-sided three-dimensional integrated architecture of an ultra-wideband radio frequency micro system and a packaging method, provides a ceramic double-sided three-dimensional integrated architecture of the ultra-wideband radio frequency micro system, and belongs to the technical field of ultra-wideband radio frequency packaging; the micro-frame comprises a ceramic substrate, a metal micro-frame, a front cover plate, a back cover plate and BGA solder balls: the double sides of the ceramic substrate are provided with cavity grooves for installing chips, the metal micro-frame is welded on the front side of the ceramic substrate, the front cover plate is welded on the metal micro-frame, the back cover plate is welded on the back cavity grooves of the ceramic substrate, the area except the back cover plate on the back of the ceramic substrate is provided with BGA bonding pads, and the BGA bonding balls are welded on the back of the ceramic substrate through the BGA bonding pads;

the patent belongs to a traditional high-reliability metal ceramic airtight packaging SiP module, adopts a multilayer step bonding finger design and a bare chip embedded cavity structure, and has the advantages of large design and process implementation difficulty, long processing period, low production yield, high tube shell cost and difficult large-scale popularization in engineering.

The patent with the application number of CN2020207217087 is named as a miniaturized high-density high-efficiency three-dimensional system level packaging circuit, adopts four layers of high-density packaging substrates as wiring layers, and fully exerts the advantage of strong high-density wiring capability of the packaging substrates; the ceramic tube shell is used as a packaging body, is not wired, and only carries out vertical transmission of signals;

the wiring medium of the patent is an organic package substrate, and the whole package is not completely airtight, because the organic package substrate contains organic matters and can volatilize water vapor; the organic package substrate has limited wiring density/precision and occupies more wiring layers and area.

Disclosure of Invention

The technical problem to be solved by the utility model is to provide a high-density SiP module, which reduces the process implementation difficulty of a tube shell, shortens the processing period, obviously improves the production yield, reduces the tube shell cost, and has high integration level and high reliability by simplifying the design of a multi-layer step bonding finger and an embedded cavity structure of a bare chip in the prior art;

the utility model solves the technical problems by adopting the following solution:

a high-density SiP module comprises a plurality of groups of silicon substrates, ceramic tube shells, internal BGA solder balls and external BGA solder balls, wherein the silicon substrates are sequentially stacked from top to bottom, the ceramic tube shells are positioned below the silicon substrates, the internal BGA solder balls are used for connecting the silicon substrates of two adjacent layers of silicon substrates and one side of the silicon substrates, which is close to the ceramic tube shells, and the external BGA solder balls are arranged on one side of the ceramic tube shells, which is far away from the silicon substrates.

In some possible embodiments, the package further comprises a cover plate mounted on the ceramic tube shell and matched with the ceramic tank body to form a hermetic package cavity, and the silicon substrate and the internal BGA solder balls are positioned in the hermetic package cavity.

In some possible embodiments, each group of the silicon substrates includes a substrate body provided with a first vertical transmission structure, and wiring layers disposed on upper and lower sides of the substrate body and connected to the first vertical transmission structure.

In some possible embodiments, the wiring layers include a top wiring layer disposed on top of the substrate body, and a bottom wiring layer disposed on bottom of the substrate body; the top surface wiring layer, the first vertical transmission structure and the bottom surface wiring layer are sequentially connected.

In some possible embodiments, the top wiring layer and the bottom wiring layer are the same and are a multi-layer RDL wiring structure; the first vertical transmission structure is a TVS vertical transmission structure.

In some possible embodiments, a bare chip and a passive device connected with the bare chip are arranged on the top surface wiring layer; the bare chip is connected with the top surface wiring layer through bonding wires.

In some possible embodiments, the bare chips are in multiple groups, and the bonding wires are arranged in a one-to-one correspondence with the bare chips and are connected with each other.

In some possible embodiments, a second vertical transfer structure is disposed within the ceramic package in communication with the inner BGA solder balls, the outer BGA solder balls.

In some possible embodiments, the silicon substrate is two sets.

Compared with the prior art, the utility model has the beneficial effects that:

according to the utility model, the plurality of groups of silicon substrates are stacked in the ceramic tube shell, bare chips are integrated on each group of silicon substrates, so that the chip mounting surfaces with the same number as the plurality of silicon substrates are formed, and the integration density is greatly improved compared with that of the traditional SiP module;

by adopting the POP three-dimensional stacking architecture, the utility model not only realizes all functions of the traditional integrated ceramic package, but also greatly simplifies the design of the multi-layer step bonding finger and the embedded cavity structure of the bare chip, thereby reducing the process implementation difficulty of the tube shell, shortening the processing period, obviously improving the production yield, reducing the tube shell cost and being convenient for large-scale popularization in engineering.

Drawings

FIG. 1 is a schematic diagram of the structure of the present utility model;

FIG. 2 is a schematic view of a silicon substrate according to the present utility model;

FIG. 3 is a top view of a silicon substrate, die, passive device of the present utility model;

FIG. 4 is a schematic diagram of the connection relationship of a silicon substrate, a bare chip, a passive device, and bonding wires in the present utility model;

wherein: 1. a ceramic envelope; 2. a cover plate; 3. a silicon substrate; 4. a wiring layer; 41. a top wiring layer; 42. a bottom wiring layer; 5. a first vertical transport structure; 6. a passive device; 7. a bare chip; 8. bonding wires; 9. internal BGA solder balls; 10. a second vertical transport structure; 11. external BGA solder balls.

Detailed Description

In the present utility model, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. Reference to "first," "second," and similar terms herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. In the implementation of the present utility model, "and/or" describes the association relationship of the association object, which means that there may be three relationships, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In the description of the embodiments of the present utility model, unless otherwise indicated, the meaning of "a plurality" means two or more. For example, a plurality of positioning posts refers to two or more positioning posts. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.

The present utility model will be described in detail below.

As shown in fig. 1-4:

as shown in fig. 1-4:

a high-density SiP module comprises a plurality of groups of silicon substrates 3, a ceramic tube shell 1, an inner BGA solder ball 9 and an outer BGA solder ball 11, wherein the groups of silicon substrates 3 are sequentially stacked from top to bottom, the ceramic tube shell 1 is positioned below the groups of silicon substrates 3, the inner BGA solder ball 9 is used for connecting the silicon substrates 3 of two adjacent layers of silicon substrates 3 and one side, close to the ceramic tube shell 1, of the silicon substrates 3 and the ceramic tube shell 1, and the outer BGA solder ball 11 is arranged on one side, far away from the silicon substrates 3, of the ceramic tube shell 1.

Further, as shown in fig. 1, the silicon substrates 3 are of a two-layer stacked structure, and the top surfaces of the two groups of silicon substrates 3 are used as mounting surfaces for mounting devices (the bare chip 7 and the passive device 6); the inner BGA solder balls 9 arranged on the bottom surface of the silicon substrate 3 are used for realizing signal transmission, and finally the BGA bonding pads on the back surface of the ceramic tube shell 1 are fanned out through the outer BGA solder balls 11; through a POP three-dimensional stacking framework, stacking the silicon substrate 3 inside the ceramic tube shell 1 through two groups of internal BGA solder balls 9, wherein the silicon substrate 3 is in a wiring layer 4 structure, the ceramic tube shell 1 is used as a packaging body, and the whole POP packaging replaces the traditional integrated multilayer wiring HTCC/LTCC ceramic packaging; the internal BGA balls 9 are stacked inside the ceramic package 1 to realize signal interconnection between the silicon substrates 3 and the ceramic package 1.

Furthermore, the silicon substrate 3 is a high-density silicon substrate 3, so that the advantage of high wiring density/precision of the silicon-based semiconductor process is fully exerted; the ceramic tube shell 1 is used as a packaging body for vertical transmission of signals, and the whole POP packaging structure can replace the traditional integrated wiring HTCC/LTCC ceramic packaging.

In some possible embodiments, as shown in fig. 1, the package further comprises a cover plate 2 mounted on the ceramic tube shell 1 and matched with the ceramic can body to form a hermetic package cavity, wherein the silicon substrate 3 and the internal BGA solder balls 9 are positioned in the hermetic package cavity;

the cover plate 2 is connected with the ceramic tube shell 1 through welding, and is used as an airtight packaging structure, and further, the cover plate and the ceramic tube shell are connected by adopting a parallel seam welding process;

in some possible embodiments, as shown in fig. 3, each group of the silicon substrates 3 includes a substrate body provided with a first vertical transmission structure 5, and wiring layers 4 disposed on upper and lower sides of the substrate body and connected to the first vertical transmission structure 5;

the first vertical transmission structure 5 is mainly used for vertical transmission of signals; the multi-layer wiring is realized through the multi-layer RDL wiring structure, meanwhile, the signals are rearranged, and the vertical transmission of the signals is realized through the TVS vertical transmission structure;

the silicon substrate 3 fully exerts the advantage of high wiring density/precision of the silicon-based semiconductor process, can realize high-density multilayer wiring, and simultaneously re-layout signals, and fan-out through the BGA ball grid array on the back (bottom surface).

In some possible embodiments, as shown in fig. 3, the wiring layer 4 includes a top wiring layer 41 disposed on the top of the substrate body, and a bottom wiring layer 42 disposed on the bottom of the substrate body; the top wiring layer 41, the first vertical transmission structure 5 and the bottom wiring layer 42 are sequentially connected; wherein the wiring layer 4 includes a top wiring layer 41, a bottom wiring layer 42; the top wiring layer 41 and the bottom wiring layer 42 are each of a multilayer RDL wiring structure; the first vertical transmission structure 5 is a TVS vertical transmission structure.

The internal BGA solder balls 9 are disposed on the bottom wiring layer 42 and communicate with the first vertical transfer structure 5;

in some of the possible embodiments of the present utility model,

in some possible embodiments, as shown in fig. 2 and fig. 4, a bare chip 7 and a passive device 6 connected to the bare chip 7 are disposed on the top wiring layer 41; the bare chip 7 is connected to the top wiring layer 41 through the bonding wire 8.

Further, the passive device 6 is a chip passive device, and may be a filter, an amplifier, or the like.

The passive device 6 is mounted to the front surface, i.e., the top surface, of the silicon substrate 3 by an SMT process, and the bare chip 7 mounted on the top wiring layer 41 is brought into communication with the top wiring layer 41 by the bonding wires 8, thereby achieving signal transmission.

The bare chip 7 is mounted on the top wiring layer 41, is connected with the top wiring layer 41 through the bonding wire 8, and performs vertical transmission of signals through the first vertical transmission structure 5;

in some possible embodiments, the bare chips 7 are in multiple groups, and the bonding wires 8 are disposed in one-to-one correspondence with the bare chips 7 and are connected to each other.

In some possible embodiments, as shown in fig. 1, a second vertical transmission structure 10 communicating with an inner BGA ball 9 and an outer BGA ball 11 is provided inside the ceramic package 1; the second vertical transmission structure 10 effectively transmits the BGA array signals inside the ceramic package 1 to the back surface of the ceramic package 1, and fans out BGA pads on the back surface of the ceramic package 1 through external BGA solder balls 11.

According to the utility model, two groups of silicon substrates 3 are stacked in the ceramic tube shell 1, a plurality of groups of chips are integrated on each silicon substrate 3, the two groups of silicon substrates 3 form two chip mounting surfaces, and the integration density is doubled compared with that of a traditional SiP module;

the utility model adopts the POP three-dimensional stacking architecture, not only realizes all functions of the traditional integrated ceramic package, but also greatly simplifies the design of the multi-layer step bonding finger and the embedded cavity structure of the bare chip 7, thereby reducing the process implementation difficulty of the tube shell, shortening the processing period, obviously improving the production yield, reducing the tube shell cost and being convenient for large-scale popularization in engineering.

The utility model is not limited to the specific embodiments described above. The utility model extends to any novel one, or any novel combination, of the features disclosed in this specification, as well as to any novel one, or any novel combination, of the steps of the method or process disclosed.

Claims

1. The high-density SiP module is characterized by comprising a plurality of groups of silicon substrates, ceramic tube shells, inner BGA solder balls and outer BGA solder balls, wherein the silicon substrates are sequentially stacked from top to bottom, the ceramic tube shells are positioned below the silicon substrates, the inner BGA solder balls are used for connecting the silicon substrates of two adjacent layers and one side, close to the ceramic tube shells, of the silicon substrates and the ceramic tube shells, and the outer BGA solder balls are arranged on one side, far away from the silicon substrates, of the ceramic tube shells.

2. The high density SiP module of claim 1 further comprising a cover plate mounted on the ceramic package and cooperating with the ceramic can to form a hermetically sealed cavity, said silicon substrate and internal BGA solder balls being located within the hermetically sealed cavity.

3. The high-density SiP module of claim 1, wherein each of the silicon substrates includes a substrate body provided with a first vertical transfer structure, and wiring layers provided on upper and lower sides of the substrate body and connected to the first vertical transfer structure.

4. A high-density SiP module according to claim 3, wherein the wiring layers include a top wiring layer disposed on top of the substrate body and a bottom wiring layer disposed on bottom of the substrate body; the top surface wiring layer, the first vertical transmission structure and the bottom surface wiring layer are sequentially connected.

5. The high-density SiP module of claim 4, wherein the top wiring layer and the bottom wiring layer are the same and are of a multi-layer RDL wiring structure; the first vertical transmission structure is a TVS vertical transmission structure.

6. The high-density SiP module of claim 4, wherein a bare chip, a passive device connected to the bare chip is disposed on said top wiring layer; the bare chip is connected with the top surface wiring layer through bonding wires.

7. The high-density SiP module of claim 6, wherein the bare chips are arranged in a plurality of groups, and the bonding wires are arranged in a one-to-one correspondence with the bare chips and are connected with each other.

8. A high density SiP module according to any of claims 1-7, wherein a second vertical transfer structure is provided in said ceramic package in communication with the inner BGA balls, the outer BGA balls.

9. The high-density SiP module of claim 8, wherein the silicon substrates are in two groups.