WO2022037037A1 - Modular encapsulation structure and method - Google Patents

Modular encapsulation structure and method Download PDF

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Publication number
WO2022037037A1
WO2022037037A1 PCT/CN2021/079251 CN2021079251W WO2022037037A1 WO 2022037037 A1 WO2022037037 A1 WO 2022037037A1 CN 2021079251 W CN2021079251 W CN 2021079251W WO 2022037037 A1 WO2022037037 A1 WO 2022037037A1
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Prior art keywords
chip
module
pad
forming
attachment structure
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PCT/CN2021/079251
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French (fr)
Chinese (zh)
Inventor
曹立强
张凯
耿菲
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华进半导体封装先导技术研发中心有限公司
上海先方半导体有限公司
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Publication of WO2022037037A1 publication Critical patent/WO2022037037A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors

Definitions

  • the present invention relates to the technical field of semiconductor packaging, in particular to a modular packaging structure and method.
  • the existing method for preparing the integrated structure of heterogeneous substrates generally uses multiple layers of heterogeneous substrates and organic metal wiring layers for circuit layout and signal interconnection, and then attaches multiple functional chips to one side to achieve a three-dimensional structure by spatial folding. 3D integration. Since this method uses a multi-layer heterogeneous substrate and an organic metal wiring layer, the size in the Z direction after three-dimensional folding will be very large. For the currently required small size, the X and Y directions are reduced and the Z direction is greatly increased. The size and thickness of the above-mentioned structure cannot effectively reduce the package volume of the structural component and improve the integration degree of the microsystem. Moreover, during operation, the multi-chip generates a large amount of heat, so the multi-layer heterogeneous substrate and the organic wiring layer at the folded and bent position are easily aged and damaged.
  • the purpose of the present invention is to provide a modular packaging structure and method to solve the problem of low integration of the existing heterogeneous integrated structure.
  • the present invention provides a modular packaging structure, including:
  • At least one first module arranged in a stack includes a first chip and a second chip arranged opposite to each other, the first chip is electrically led out to the first surface and/or the second surface of the first module, so the second chip is electrically led out to the first surface and/or the second surface of the first module;
  • a second module attached to the first module comprising a third chip, the third chip being electrically led out to the first surface and/or the second surface of the second module;
  • the second module is electrically connected to the first module.
  • the first chip is a radio frequency system digital chip, used for generating, amplifying and processing digital signals;
  • the second chip is a radio frequency transceiver chip, used for amplifying, phase shifting and attenuating radio frequency signals;
  • the third chip is an antenna module for transmitting and receiving radio frequency signals.
  • the present invention also provides a modular packaging method, comprising:
  • the first module is prepared by the following steps:
  • the second module is prepared by the following steps:
  • the third attachment structure is electrically connected to one or more of the first attachment structure and/or the second attachment structure.
  • forming a first attachment structure for electrically leading out the first chip, and attaching the first chip to the first attachment structure includes:
  • first adhesive layer on the carrier sheet, and sequentially forming a first pad, a first redistribution layer and a first conductive column electrically connected to each other on the first adhesive layer;
  • the pads of the first chip are attached to the first redistribution layer.
  • forming a second attachment structure electrically leading out the first chip, and attaching the second attachment structure to the second chip includes:
  • the second redistribution layer is attached to the pads of the second chip
  • the second conductive column is electrically connected to the first conductive column.
  • the modular packaging method also includes:
  • a plurality of first dielectric layers are formed before, between, and after the steps of forming the first pad, the first redistribution layer, and the first conductive pillar, the first dielectric layers exposing a portion of the first dielectric layer. a pad, the first redistribution layer and the first conductive column;
  • a plurality of second dielectric layers are formed before, between, and after the steps of forming the second conductive pillar, the second redistribution layer, and the second pad, the second dielectric layers exposing a portion of the first two bonding pads, the second redistribution layer and the second conductive pillar;
  • the method further includes: removing the carrier sheet and the first adhesive layer.
  • forming a third attachment structure for electrically leading out the third chip, and attaching the third chip to the third attachment structure includes:
  • the third redistribution layer is attached to the pads of the third chip
  • a plurality of third dielectric layers are formed before, between, and after the steps of forming the third chip, the third redistribution layer, and the third pad, the third dielectric layers exposing portions of the third a chip, the third redistribution layer and the third pad;
  • the slide and the third adhesive layer are removed.
  • forming at least one first module and stacking the at least one first module includes:
  • the lower surface is relative to the next first module, and the upper surface is relative to the previous first module;
  • a second solder ball is formed on the second pad, and the second solder ball of the next first module is attached to the first pad of the previous first module.
  • attaching the second module to the first module includes:
  • a second solder ball is formed on the second pad of the uppermost first module, and the third pad is attached to the second solder ball of the uppermost first module;
  • a third solder ball is formed on the third pad, and the second pad of the uppermost first module is attached to the third solder ball.
  • At least one first module arranged by stacking includes a first chip and a second chip arranged opposite to each other, and the second module attached to the first module includes The third chip, and the second module is electrically connected to the first module, which realizes the package structure of module integration, improves the integration degree of the chip, and avoids bending and aging due to the stacked arrangement and the arrangement opposite to each other, and improves the heat dissipation of the package body.
  • the transmission distance is shorter, and the circuit parasitics and losses are smaller. Due to the modular design, the present invention realizes multi-layer three-dimensional stacking.
  • the modular packaging structure and method of the present invention have higher integration and packaging density and smaller volume; by introducing metal conductive columns and selecting dielectric layers covering different thermal expansion coefficients, heat dissipation is improved, warpage is controlled, and bending is avoided.
  • the problem of aging is higher, and the reliability is higher; the modular design can realize multi-layer three-dimensional stacking by stacking at least one first module; the transmission distance between the three chips is small, which can effectively reduce the loss and parasitic effect and improve the performance.
  • the first chip is a digital chip in the radio frequency system, which can be used to generate, amplify and process various digital signals
  • the second chip is a radio frequency transceiver chip in the radio frequency system, which is used to amplify, phase shift and attenuate the signal
  • the third chip is a different antenna module, which is used to transmit and receive communication signals, thus forming a radio frequency-digital hybrid system.
  • the present invention not only has higher efficiency Integration, smaller loss, and can meet different RF application requirements such as multi-band and multi-direction through the setting of multiple different antenna modules.
  • 1 to 8 are schematic diagrams of a manufacturing process of a first module in an embodiment of the present invention.
  • 9 to 14 are schematic diagrams of the manufacturing process of the second module in an embodiment of the present invention.
  • 15 is an integrated schematic diagram of a single first module and a second module in an embodiment of the present invention.
  • 16 is an integrated schematic diagram of a plurality of first modules and second modules in an embodiment of the present invention.
  • the core idea of the present invention is to provide a modular packaging structure and method to solve the problem of low integration of the existing heterogeneous integrated structure.
  • the present invention provides a modular packaging structure and method, comprising: at least one first module arranged in a stack, each including a first chip and a second chip arranged opposite to each other, the first chip electrically lead out to the first surface and/or the second surface of the first module, the second chip is electrically lead out to the first surface and/or the second surface of the first module; attached to the first surface and/or the second surface of the first module;
  • a second module on a module includes a third chip, the third chip is electrically led out to the first surface and/or the second surface of the second module; the second module is electrically connected to the first module connect.
  • This embodiment provides a modular packaging structure, including: at least one first module 1 arranged in a stack, each including a first chip 3 and a second chip 4 arranged opposite to each other, and the first chip 3 is electrically led out to the The first surface and/or the second surface of the first module 1, the second chip 4 is electrically led out to the first surface and/or the second surface of the first module 1; attached to the first surface and/or the second surface of the first module 1; A second module 2 on a module 1 includes a third chip 5, the third chip 5 is electrically led out to the first surface and/or the second surface of the second module 2; the second module and The first module is electrically connected.
  • the first chip 3 is a radio frequency system digital chip, which is used for generating, amplifying and processing digital signals;
  • the second chip 4 is a radio frequency transceiver chip, which is used for amplifying, amplifying and processing digital signals. Phase-shift and attenuate radio frequency signals;
  • the third chip 5 is an antenna module for transmitting and receiving radio frequency signals.
  • the present embodiment also provides a modular packaging method, comprising: forming at least one first module 1 and arranging at least one first module 1 in a stack, and attaching a second module 2 to the first module 1; the The first module 1 is prepared by the following steps: forming a first attachment structure 6 electrically leading out the first chip 3, attaching the first chip 3 to the first attachment structure 6; arranging the second chip 4 as facing away from the first chip 3; forming a second attachment structure 7 electrically leading out the second chip 4, the second attachment structure 7 is attached to the second chip 4; the second The module 2 is prepared by the following steps: forming a third attachment structure 8 electrically leading out the third chip 5, attaching the third chip 5 to the third attachment structure 8; the third attachment structure 8 and the One or more of the first attachment structures 6 and/or the second attachment structures 7 are electrically connected.
  • forming a first attachment structure 6 for electrically leading out the first chip 3 , and attaching the first chip 3 to the first attachment structure 6 includes: on-board A first adhesive layer 9 is formed on the sheet 20, and a first pad 12, a first redistribution layer 15 and a first conductive column 18 electrically connected to each other are sequentially formed on the first adhesive layer 9; the first chip The pads of 3 are attached to the first redistribution layer 15 .
  • forming a second attachment structure 7 for electrically leading out the first chip 3 and attaching the second attachment structure 7 to the second chip 4 includes: on the first chip 3 A second adhesive layer 10 is formed thereon, and the second chip 4 is placed on the second adhesive layer 10; on the second adhesive layer 10, a second conductive column 19, a second conductive column 19, a second conductive column 19 electrically connected to each other are sequentially formed
  • the wiring layer 16 and the second pad 13 ; the second redistribution layer 16 is attached to the pad of the second chip 4 ; the second conductive column 19 is electrically connected to the first conductive column 18 .
  • the method further includes: before, during and after the steps of forming the first pad 12 , the first redistribution layer 15 and the first conductive pillar 18 .
  • a plurality of first dielectric layers 22 are formed, and the first dielectric layers 22 expose parts of the first pads 12 , the first redistribution layer 15 and the first conductive pillars 18 ; after forming the second conductive
  • a plurality of second dielectric layers 23 are formed before, between and after the steps of the pillar 19 , the second redistribution layer 16 and the second pad 13 , and the second dielectric layer 23 exposes a portion of the second pad
  • forming a third attachment structure 8 for electrically leading out the third chip 5 and attaching the third chip 5 to the third attachment structure 8 includes: on the carrier sheet A third adhesive layer 11 is formed on the 20, and a third chip 5, a third redistribution layer 17 and a third pad 14 are sequentially formed on the third adhesive layer 11 to be electrically connected to each other;
  • the wiring layer 17 is attached to the pads of the third chip 5 ; before, between and after the steps of forming the third chip 5 , the third redistribution layer 17 and the third pads 14 , a plurality of The third dielectric layer 24, the third dielectric layer 24 exposes part of the third chip 5, the third redistribution layer 17 and the third pad 14; remove the carrier 20 and the third Adhesive layer 11 .
  • forming at least one first module 1 and stacking the at least one first module 1 includes: placing the first pads of each first module 1
  • the surface where 12 is located is the lower surface, and the surface where the second pad 13 is located is the upper surface; the lower surface is opposite to the next first module 1, and the upper surface is opposite to the previous first module 1;
  • the first solder ball 21, the first solder ball 21 of the previous first module 1 is attached to the second pad 13 of the next first module 1; or the second solder ball is formed on the second pad 13 21.
  • the second solder balls 21 of the next first module 1 are attached to the first pads 12 of the previous first module 1 .
  • attaching the second module 2 to the first module 1 includes: forming second solder balls 21 on the second pads 13 of the uppermost first module 1, the first The three bonding pads 14 are attached to the second solder balls 21 of the uppermost first module 1 ; or the third solder balls 21 are formed on the third bonding pads 14 , and the second bonding pads 13 of the uppermost first module 1 are attached to the third solder ball 21 .
  • At least one first module 1 arranged by stacking includes a first chip 3 and a second chip 4 arranged opposite to each other, and the chips attached to the first module 1
  • the second module 2 includes a third chip 5, and the third chip 5 is electrically connected to one or more of the first chips 3 and/or the second chips 4, so as to realize a module-integrated package structure,
  • the chip integration is improved, the stacking arrangement and the arrangement facing each other avoid bending aging, improve the heat dissipation of the package, and the transmission distance is shorter, and the circuit parasitics and losses are smaller.
  • the present invention realizes multi-layer three-dimensional stacking due to the modular design. .
  • the modular packaging structure and method of the present invention have higher integration and packaging density and smaller volume; by introducing metal conductive columns and selecting dielectric layers covering different thermal expansion coefficients, heat dissipation is improved, warpage is controlled, and bending is avoided.
  • the problem of aging is higher, and the reliability is higher; the modular design can realize multi-layer three-dimensional stacking by stacking at least one first module 1; the transmission distance between the three chips is small, which can effectively reduce the loss and parasitic effect and improve the performance.
  • the first chip 3 is a digital chip in the radio frequency system, which can be used to generate, amplify and process various digital signals
  • the second chip 4 is a radio frequency transceiver chip in the radio frequency system, which is used to amplify and phase shift the signal.
  • the third chip 5 is a different antenna module, which is used to transmit and receive communication signals, thus forming a radio frequency-digital hybrid system.
  • the present invention not only has the advantages of Higher integration, smaller loss, and can meet different RF application requirements such as multi-band and multi-direction through the setting of multiple different antenna modules.
  • the manufacturing method of the first module 1 includes:
  • a carrier sheet 20 is provided, the front side of the carrier sheet 20 is covered with the first adhesive layer 9 , and then the first pads 12 are formed on the first adhesive layer 9 .
  • the first dielectric layer 22 is then covered to expose the first pads 12 , and then the first redistribution layer 15 is formed on the first dielectric layer 22 .
  • the first redistribution layer 15 is communicated with the first pad 12 .
  • the first dielectric layer 22 of the second layer is first covered over the first redistribution layer 15 so that the first redistribution layer 15 is exposed, and then a first conductive layer is formed at the exposed position of the first redistribution layer 15
  • the pillar 18 , the first conductive pillar 18 is in electrical communication with the first redistribution layer 15 .
  • a first chip 3 is provided, placed over the first redistribution layer 15 , and the first chip 3 is electrically connected to the first redistribution layer 15 through solder balls 21 . Then, the first dielectric layer 22 of the third layer is covered, the third dielectric layer is flush with the back surface of the first chip 3 , and the first conductive pillars 18 are exposed.
  • the second conductive pillar 19 is formed on the upper surface, and the second conductive pillar 19 is connected with the first conductive pillar 18 , and then the second chip 4 is placed, with the pads of the second chip 4 facing upward.
  • the bonding layer 10 is placed on the first chip 3 , and the pad surface of the second chip 4 is flush with the surface of the second conductive pillar 19 .
  • a second dielectric layer 23 is firstly covered, and the second dielectric layer 23 is flush with the pad surface of the second chip 4 and the upper surface of the second conductive pillar 19 , and then the second redistribution layer 16 is fabricated.
  • the wiring layer 16 is in electrical communication with the pads of the second chip 4 and the second conductive pillars 19 .
  • a patterned second dielectric layer 23 is formed, and then the second pads 13 (or the second solder balls 21 are directly formed), the second pads 13 (solder balls 21 ) and the second layer of The wiring layer 16 is in electrical communication.
  • the carrier sheet 20 and the first adhesive layer 9 are removed.
  • Materials with different expansion coefficients can be selected between each of the first dielectric layers 22 and/or between the second dielectric layers 23, so that the stress between the materials can be matched and warpage can be reduced.
  • the manufacturing method of the second module 2 includes:
  • the upper surface of the carrier sheet 20 is covered with the third adhesive layer 11 , and then the third dielectric layer 24 is formed on the third adhesive layer 11 .
  • At least one third chip 5 is placed on the third dielectric layer 24 with the pads of the third chip 5 facing upward, and then a third dielectric layer 24 is covered.
  • the upper surface of 24 is flush with the pad surface of the third chip 5 .
  • This embodiment does not limit the number and position of the third chips 5 , and different numbers of the third chips 5 can be placed according to actual requirements and the positions of the third chips 5 can be arbitrarily arranged according to the actual operation.
  • the third redistribution layer 17 is fabricated, the third redistribution layer 17 is electrically connected to the pads of the third chip 5 , and then a patterned third dielectric layer 24 is covered, so that the third redistribution layer 17 exposed.
  • the third pads 14 are formed (or the third solder balls 21 are directly formed), and the third solder balls 21 are electrically connected to the third redistribution layer 17 .
  • the carrier sheet 20 and the third adhesive layer 11 are removed.
  • FIGS. 15 and 16 The integration of one or more first modules 1 and the integration of the first module 1 and the second module 2 are shown in FIGS. 15 and 16 .
  • the first modules 1 are stacked, fixed by solder balls 21 and electrically connected between the modules.
  • at least one first module 1 may be stacked first, and then a second module 2 may be stacked.
  • the first chip 3 can be a digital chip in a radio frequency system, which can be used to generate, amplify and process various digital signals
  • the second chip 4 can be a radio frequency transceiver chip in the radio frequency system , used to amplify, shift, and attenuate the signal
  • the third chip 5 can be a different antenna module, used to transmit and receive communication signals.
  • a radio frequency-digital hybrid system can be formed.
  • this packaging example not only has a higher integration level and lower loss, but also can pass through multiple different antenna modules.
  • the settings meet different RF application requirements such as multi-band and multi-direction.
  • the packaging of the prior art is limited in the number of layers and cannot be modularized, while the first module adopted by the present invention has circuit pins on the front and back, which can be stacked multiple times according to actual needs; the first module of the present invention is structurally It is almost symmetrical up and down. Through this, the warpage balance can be achieved without selecting a dielectric layer with a matching thermal expansion coefficient, and the reliability of the final package can be increased. It overcomes the defect in the prior art that warpage balance can only be achieved by selecting dielectric layer materials with matching thermal expansion coefficients because the upper and lower structures in the package are not asymmetrical.
  • the above embodiments have described in detail the different configurations of the modular packaging structure and method.
  • the present invention includes but is not limited to the configurations listed in the above embodiments, any configuration basis provided in the above embodiments
  • the contents of the above transformation all belong to the scope of protection of the present invention. Those skilled in the art can draw inferences from the contents of the foregoing embodiments.

Abstract

Provided are a modular encapsulation structure and method. The modular encapsulation structure comprises: at least one first module which is arranged in a stacked manner, with each first module comprising a first chip and a second chip, which are arranged facing away from each other, wherein the first chip is electrically led out to a first surface and/or a second surface of the first module, and the second chip is electrically led out to the first surface and/or the second surface of the first module; and a second module, which is connected to the first module in an attachment manner, wherein the second module comprises a third chip, and the third chip is electrically led out to a first surface and/or a second surface of the second module. The second module is electrically connected to the first module.

Description

模块化封装结构及方法Modular packaging structure and method 技术领域technical field
本发明涉及半导体封装技术领域，特别涉及一种模块化封装结构及方法。The present invention relates to the technical field of semiconductor packaging, in particular to a modular packaging structure and method.
背景技术Background technique
现有的异质基板集成结构的制备方法，一般通过多层异质基板和有机金属布线层进行线路布置和信号互连，然后将多个功能芯片贴于一面，通过空间折叠的形式实现立体式的三维集成。该方法由于采用多层异质基板和有机金属布线层，所以在三维折叠后Z方向上的尺寸会很大，这对当前需要的小尺寸来说，缩小X、Y方向的同时大大增加Z方向上的尺寸厚度，这无法有效的减小结构件的封装体积，提高微系统集成度。而且在工作时，由于多芯片导致发热量较大，因此，其折叠弯曲处的多层异质基板和有机布线层容易因此而老化损坏。The existing method for preparing the integrated structure of heterogeneous substrates generally uses multiple layers of heterogeneous substrates and organic metal wiring layers for circuit layout and signal interconnection, and then attaches multiple functional chips to one side to achieve a three-dimensional structure by spatial folding. 3D integration. Since this method uses a multi-layer heterogeneous substrate and an organic metal wiring layer, the size in the Z direction after three-dimensional folding will be very large. For the currently required small size, the X and Y directions are reduced and the Z direction is greatly increased. The size and thickness of the above-mentioned structure cannot effectively reduce the package volume of the structural component and improve the integration degree of the microsystem. Moreover, during operation, the multi-chip generates a large amount of heat, so the multi-layer heterogeneous substrate and the organic wiring layer at the folded and bent position are easily aged and damaged.
发明内容SUMMARY OF THE INVENTION
本发明的目的在于提供一种模块化封装结构及方法，以解决现有的异质集成结构集成度较低的问题。The purpose of the present invention is to provide a modular packaging structure and method to solve the problem of low integration of the existing heterogeneous integrated structure.
为解决上述技术问题，本发明提供一种模块化封装结构，包括：In order to solve the above technical problems, the present invention provides a modular packaging structure, including:
堆叠布置的至少一个第一模块，均包括相互背对布置的第一芯片及第二芯片，所述第一芯片电性引出至所述第一模块的第一表面和/或第二表面，所述第二芯片电性引出至所述第一模块的第一表面和/或第二表面；At least one first module arranged in a stack includes a first chip and a second chip arranged opposite to each other, the first chip is electrically led out to the first surface and/or the second surface of the first module, so the second chip is electrically led out to the first surface and/or the second surface of the first module;
附连于所述第一模块上的第二模块，其包括第三芯片，所述第三芯片电性引出至所述第二模块的第一表面和/或第二表面；a second module attached to the first module, comprising a third chip, the third chip being electrically led out to the first surface and/or the second surface of the second module;
所述第二模块与第一模块电性连接。The second module is electrically connected to the first module.
可选的，在所述的模块化封装结构中，Optionally, in the modular packaging structure,
所述第一芯片为射频系统数字芯片，用于产生、放大和处理数字信号；The first chip is a radio frequency system digital chip, used for generating, amplifying and processing digital signals;
所述第二芯片为射频收发芯片，用于放大、移相和衰减射频信号；The second chip is a radio frequency transceiver chip, used for amplifying, phase shifting and attenuating radio frequency signals;
所述第三芯片为天线模块，用于传输和接收射频信号。The third chip is an antenna module for transmitting and receiving radio frequency signals.
本发明还提供一种模块化封装方法，包括：The present invention also provides a modular packaging method, comprising:
形成至少一个第一模块并将至少一个第一模块堆叠布置，将第二模块附连至所述第一模块上；forming at least one first module and arranging the at least one first module in a stack, attaching a second module to the first module;
所述第一模块通过以下步骤制备：The first module is prepared by the following steps:
形成将第一芯片电性引出的第一附连结构，将所述第一芯片附连至第一附连结构；forming a first attachment structure electrically leading out the first chip, and attaching the first chip to the first attachment structure;
将第二芯片布置为与所述第一芯片相互背对；arranging the second chip facing away from the first chip;
形成将所述第二芯片电性引出的第二附连结构，第二附连结构附连至所述第二芯片；forming a second attachment structure electrically leading out the second chip, the second attachment structure being attached to the second chip;
所述第二模块通过以下步骤制备：The second module is prepared by the following steps:
形成将第三芯片电性引出的第三附连结构，将所述第三芯片附连至第三附连结构；forming a third attachment structure electrically leading out the third chip, and attaching the third chip to the third attachment structure;
所述第三附连结构与一个或多个所述第一附连结构和/或所述第二附连结构电性连接。The third attachment structure is electrically connected to one or more of the first attachment structure and/or the second attachment structure.
可选的，在所述的模块化封装方法中，形成将第一芯片电性引出的第一附连结构，将所述第一芯片附连至第一附连结构包括：Optionally, in the modular packaging method, forming a first attachment structure for electrically leading out the first chip, and attaching the first chip to the first attachment structure includes:
在载片上形成第一粘合层，在所述第一粘合层上依次形成相互电性连接的第一焊盘、第一重布线层及第一导电柱；forming a first adhesive layer on the carrier sheet, and sequentially forming a first pad, a first redistribution layer and a first conductive column electrically connected to each other on the first adhesive layer;
第一芯片的焊盘附连至所述第一重布线层。The pads of the first chip are attached to the first redistribution layer.
可选的，在所述的模块化封装方法中，形成将第一芯片电性引出的第二附连结构，第二附连结构附连至所述第二芯片包括：Optionally, in the modular packaging method, forming a second attachment structure electrically leading out the first chip, and attaching the second attachment structure to the second chip includes:
在第一芯片上上形成第二粘合层，forming a second adhesive layer on the first chip,
将第二芯片放置于第二粘合层上；placing the second chip on the second adhesive layer;
在所述第二粘合层上依次形成相互电性连接的第二导电柱、第二重布线层及第二焊盘；forming a second conductive column, a second redistribution layer and a second pad that are electrically connected to each other in sequence on the second adhesive layer;
所述第二重布线层附连至第二芯片的焊盘；the second redistribution layer is attached to the pads of the second chip;
所述第二导电柱与所述第一导电柱电性连接。The second conductive column is electrically connected to the first conductive column.
可选的，在所述的模块化封装方法中，还包括：Optionally, in the modular packaging method, it also includes:
在形成所述第一焊盘、所述第一重布线层及所述第一导电柱的步骤之前、之间及之后形成多个第一介质层，所述第一介质层暴露部分所述第一焊盘、所述第一重布线层及所述第一导电柱；A plurality of first dielectric layers are formed before, between, and after the steps of forming the first pad, the first redistribution layer, and the first conductive pillar, the first dielectric layers exposing a portion of the first dielectric layer. a pad, the first redistribution layer and the first conductive column;
在形成所述第二导电柱、所述第二重布线层及所述第二焊盘的步骤之前、之间及之后形成多个第二介质层，所述第二介质层暴露部分所述第二焊盘、所述第二重布线层及所述第二导电柱；A plurality of second dielectric layers are formed before, between, and after the steps of forming the second conductive pillar, the second redistribution layer, and the second pad, the second dielectric layers exposing a portion of the first two bonding pads, the second redistribution layer and the second conductive pillar;
可选的，在所述的模块化封装方法中，还包括：去除所述载片和所述第一粘合层。Optionally, in the modular packaging method, the method further includes: removing the carrier sheet and the first adhesive layer.
可选的，在所述的模块化封装方法中，形成将第三芯片电性引出的第三附连结构，将所述第三芯片附连至第三附连结构包括：Optionally, in the modular packaging method, forming a third attachment structure for electrically leading out the third chip, and attaching the third chip to the third attachment structure includes:
在载片上形成第三粘合层，在所述第三粘合层上依次形成相互电性连接的第三芯片、第三重布线层及第三焊盘；forming a third adhesive layer on the carrier sheet, and sequentially forming a third chip, a third redistribution layer and a third pad that are electrically connected to each other on the third adhesive layer;
所述第三重布线层附连至第三芯片的焊盘；the third redistribution layer is attached to the pads of the third chip;
在形成所述第三芯片、所述第三重布线层及所述第三焊盘的步骤之前、之间及之后形成多个第三介质层，所述第三介质层暴露部分所述第三芯片、所述第三重布线层及所述第三焊盘；A plurality of third dielectric layers are formed before, between, and after the steps of forming the third chip, the third redistribution layer, and the third pad, the third dielectric layers exposing portions of the third a chip, the third redistribution layer and the third pad;
去除所述载片和所述第三粘合层。The slide and the third adhesive layer are removed.
可选的，在所述的模块化封装方法中，形成至少一个第一模块并将至少一个第一模块堆叠布置包括：Optionally, in the modular packaging method, forming at least one first module and stacking the at least one first module includes:
将每个第一模块的第一焊盘所在的面作为下表面，第二焊盘所在的面作为上表面；Take the surface where the first pad of each first module is located as the lower surface, and the surface where the second pad is located as the upper surface;
下表面相对下一个第一模块，上表面相对上一个第一模块；The lower surface is relative to the next first module, and the upper surface is relative to the previous first module;
在所述第一焊盘上形成第一焊球，上一个第一模块的第一焊球附连至下一个第一模块的第二焊盘上；或forming first solder balls on said first pads, the first solder balls of the previous first module being attached to the second pads of the next first module; or
在所述第二焊盘上形成第二焊球，下一个第一模块的第二焊球附连至上一个第一模块的第一焊盘上。A second solder ball is formed on the second pad, and the second solder ball of the next first module is attached to the first pad of the previous first module.
可选的，在所述的模块化封装方法中，将第二模块附连至所述第一模 块上包括：Optionally, in the modular packaging method, attaching the second module to the first module includes:
最上一个第一模块的第二焊盘上形成第二焊球，所述第三焊盘附连至最上一个第一模块的第二焊球；或a second solder ball is formed on the second pad of the uppermost first module, and the third pad is attached to the second solder ball of the uppermost first module; or
所述第三焊盘上形成第三焊球，最上一个第一模块的第二焊盘附连至所述第三焊球。A third solder ball is formed on the third pad, and the second pad of the uppermost first module is attached to the third solder ball.
在本发明提供的模块化封装结构及方法中，通过堆叠布置的至少一个第一模块包括相互背对布置的第一芯片及第二芯片，附连于所述第一模块上的第二模块包括第三芯片，且所述第二模块与第一模块电性连接，实现了模块集成的封装结构，提高了芯片集成度，堆叠布置、相互背对布置避免了弯曲老化，改善了封装体散热，且传输距离更短，电路寄生和损耗更小，本发明由于模块化设计，实现了多层三维堆叠。In the modular packaging structure and method provided by the present invention, at least one first module arranged by stacking includes a first chip and a second chip arranged opposite to each other, and the second module attached to the first module includes The third chip, and the second module is electrically connected to the first module, which realizes the package structure of module integration, improves the integration degree of the chip, and avoids bending and aging due to the stacked arrangement and the arrangement opposite to each other, and improves the heat dissipation of the package body. In addition, the transmission distance is shorter, and the circuit parasitics and losses are smaller. Due to the modular design, the present invention realizes multi-layer three-dimensional stacking.
本发明的模块化封装结构及方法具有更高的集成度和封装密度，体积更小；通过引入金属导电柱以及选择覆盖不同热膨胀系数的介质层，提高散热，控制翘曲，也避免了弯折老化的问题，可靠性更高；采用模块化设计，可通过堆叠至少一个第一模块实现多层三维堆叠；三种芯片之间传输距离小，可有效降低损耗和寄生效应，提高性能。The modular packaging structure and method of the present invention have higher integration and packaging density and smaller volume; by introducing metal conductive columns and selecting dielectric layers covering different thermal expansion coefficients, heat dissipation is improved, warpage is controlled, and bending is avoided. The problem of aging is higher, and the reliability is higher; the modular design can realize multi-layer three-dimensional stacking by stacking at least one first module; the transmission distance between the three chips is small, which can effectively reduce the loss and parasitic effect and improve the performance.
本发明通过第一芯片是射频系统中的数字芯片，其可以用来产生、放大和处理各种数字信号，第二芯片是射频系统中射频收发芯片，用以对信号进行放大、移相、衰减，第三芯片是不同的天线模块，用来传输和接受通讯信号，由此组成了射频-数字混合系统，相比于传统的在基板上集成射频元件的封装工艺，本发明不仅有着更高的集成度、更小的损耗，而且能够通过多个不同天线模块的设置满足多频段、多方向等不同的射频应用需求。In the present invention, the first chip is a digital chip in the radio frequency system, which can be used to generate, amplify and process various digital signals, and the second chip is a radio frequency transceiver chip in the radio frequency system, which is used to amplify, phase shift and attenuate the signal. , the third chip is a different antenna module, which is used to transmit and receive communication signals, thus forming a radio frequency-digital hybrid system. Compared with the traditional packaging process of integrating radio frequency components on the substrate, the present invention not only has higher efficiency Integration, smaller loss, and can meet different RF application requirements such as multi-band and multi-direction through the setting of multiple different antenna modules.
附图说明Description of drawings
图1～8是本发明一实施例中第一模块的制作流程示意图；1 to 8 are schematic diagrams of a manufacturing process of a first module in an embodiment of the present invention;
图9～14是本发明一实施例中第二模块的制作流程示意图；9 to 14 are schematic diagrams of the manufacturing process of the second module in an embodiment of the present invention;
图15是本发明一实施例中单个第一模块与第二模块的集成示意图；15 is an integrated schematic diagram of a single first module and a second module in an embodiment of the present invention;
图16是本发明一实施例中多个第一模块与第二模块的集成示意图；16 is an integrated schematic diagram of a plurality of first modules and second modules in an embodiment of the present invention;
图中所示：1-第一模块；2-第二模块；3-第一芯片；4-第二芯片；5-第三芯片；6-第一附连结构；7-第二附连结构；8-第三附连结构；9-第一粘合层；10-第二粘合层；11-第三粘合层；12-第一焊盘；13-第二焊盘；14-第三焊盘；15-第一重布线层；16-第二重布线层；17-第三重布线层；18-第一导电柱；19-第二导电柱；20-载片；21-焊球；22-第一介质层；23-第二介质层；24-第三介质层。Shown in the figure: 1-first module; 2-second module; 3-first chip; 4-second chip; 5-third chip; 6-first attachment structure; 7-second attachment structure 8-Third attachment structure; 9-First adhesive layer; 10-Second adhesive layer; 11-Third adhesive layer; 12-First pad; 13-Second pad; Three pads; 15-first redistribution layer; 16-second redistribution layer; 17-third redistribution layer; 18-first conductive column; 19-second conductive column; 20-carrier; 21-soldering ball; 22-first dielectric layer; 23-second dielectric layer; 24-third dielectric layer.
具体实施方式detailed description
以下结合附图和具体实施例对本发明提出的模块化封装结构及方法作进一步详细说明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。The modular packaging structure and method proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become apparent from the following description and claims. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.
另外，除非另行说明，本发明的不同实施例中的特征可以相互组合。例如，可以用第二实施例中的某特征替换第一实施例中相对应或功能相同或相似的特征，所得到的实施例同样落入本申请的公开范围或记载范围。Furthermore, unless stated otherwise, features in different embodiments of the invention may be combined with each other. For example, a certain feature in the second embodiment can be used to replace the corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment also falls within the scope of disclosure or description of the present application.
本发明的核心思想在于提供一种模块化封装结构及方法，以解决现有的异质集成结构集成度较低的问题。The core idea of the present invention is to provide a modular packaging structure and method to solve the problem of low integration of the existing heterogeneous integrated structure.
为实现上述思想，本发明提供了一种模块化封装结构及方法，包括：堆叠布置的至少一个第一模块，均包括相互背对布置的第一芯片及第二芯片，所述第一芯片电性引出至所述第一模块的第一表面和/或第二表面，所述第二芯片电性引出至所述第一模块的第一表面和/或第二表面；附连于所述第一模块上的第二模块，其包括第三芯片，所述第三芯片电性引出至所述第二模块的第一表面和/或第二表面；所述第二模块与第一模块电性连接。In order to realize the above idea, the present invention provides a modular packaging structure and method, comprising: at least one first module arranged in a stack, each including a first chip and a second chip arranged opposite to each other, the first chip electrically lead out to the first surface and/or the second surface of the first module, the second chip is electrically lead out to the first surface and/or the second surface of the first module; attached to the first surface and/or the second surface of the first module; A second module on a module includes a third chip, the third chip is electrically led out to the first surface and/or the second surface of the second module; the second module is electrically connected to the first module connect.
本实施例提供一种模块化封装结构，包括：堆叠布置的至少一个第一模块1，均包括相互背对布置的第一芯片3及第二芯片4，所述第一芯片3电性引出至所述第一模块1的第一表面和/或第二表面，所述第二芯片4电性引出至所述第一模块1的第一表面和/或第二表面；附连于所述第一模块1上的第二模块2，其包括第三芯片5，所述第三芯片5电性引出至所述第 二模块2的第一表面和/或第二表面；所述第二模块与第一模块电性连接。This embodiment provides a modular packaging structure, including: at least one first module 1 arranged in a stack, each including a first chip 3 and a second chip 4 arranged opposite to each other, and the first chip 3 is electrically led out to the The first surface and/or the second surface of the first module 1, the second chip 4 is electrically led out to the first surface and/or the second surface of the first module 1; attached to the first surface and/or the second surface of the first module 1; A second module 2 on a module 1 includes a third chip 5, the third chip 5 is electrically led out to the first surface and/or the second surface of the second module 2; the second module and The first module is electrically connected.
具体的，在所述的模块化封装结构中，所述第一芯片3为射频系统数字芯片，用于产生、放大和处理数字信号；所述第二芯片4为射频收发芯片，用于放大、移相和衰减射频信号；所述第三芯片5为天线模块，用于传输和接收射频信号。Specifically, in the modular packaging structure, the first chip 3 is a radio frequency system digital chip, which is used for generating, amplifying and processing digital signals; the second chip 4 is a radio frequency transceiver chip, which is used for amplifying, amplifying and processing digital signals. Phase-shift and attenuate radio frequency signals; the third chip 5 is an antenna module for transmitting and receiving radio frequency signals.
本实施例还提供一种模块化封装方法，包括：形成至少一个第一模块1并将至少一个第一模块1堆叠布置，将第二模块2附连至所述第一模块1上；所述第一模块1通过以下步骤制备：形成将第一芯片3电性引出的第一附连结构6，将所述第一芯片3附连至第一附连结构6；将第二芯片4布置为与所述第一芯片3相互背对；形成将所述第二芯片4电性引出的第二附连结构7，第二附连结构7附连至所述第二芯片4；所述第二模块2通过以下步骤制备：形成将第三芯片5电性引出的第三附连结构8，将所述第三芯片5附连至第三附连结构8；所述第三附连结构8与一个或多个所述第一附连结构6和/或所述第二附连结构7电性连接。The present embodiment also provides a modular packaging method, comprising: forming at least one first module 1 and arranging at least one first module 1 in a stack, and attaching a second module 2 to the first module 1; the The first module 1 is prepared by the following steps: forming a first attachment structure 6 electrically leading out the first chip 3, attaching the first chip 3 to the first attachment structure 6; arranging the second chip 4 as facing away from the first chip 3; forming a second attachment structure 7 electrically leading out the second chip 4, the second attachment structure 7 is attached to the second chip 4; the second The module 2 is prepared by the following steps: forming a third attachment structure 8 electrically leading out the third chip 5, attaching the third chip 5 to the third attachment structure 8; the third attachment structure 8 and the One or more of the first attachment structures 6 and/or the second attachment structures 7 are electrically connected.
进一步的，在所述的模块化封装方法中，形成将第一芯片3电性引出的第一附连结构6，将所述第一芯片3附连至第一附连结构6包括：在载片20上形成第一粘合层9，在所述第一粘合层9上依次形成相互电性连接的第一焊盘12、第一重布线层15及第一导电柱18；第一芯片3的焊盘附连至所述第一重布线层15。在所述的模块化封装方法中，形成将第一芯片3电性引出的第二附连结构7，第二附连结构7附连至所述第二芯片4包括：在第一芯片3上上形成第二粘合层10，将第二芯片4放置于第二粘合层10上；在所述第二粘合层10上依次形成相互电性连接的第二导电柱19、第二重布线层16及第二焊盘13；所述第二重布线层16附连至第二芯片4的焊盘；所述第二导电柱19与所述第一导电柱18电性连接。Further, in the modular packaging method, forming a first attachment structure 6 for electrically leading out the first chip 3 , and attaching the first chip 3 to the first attachment structure 6 includes: on-board A first adhesive layer 9 is formed on the sheet 20, and a first pad 12, a first redistribution layer 15 and a first conductive column 18 electrically connected to each other are sequentially formed on the first adhesive layer 9; the first chip The pads of 3 are attached to the first redistribution layer 15 . In the described modular packaging method, forming a second attachment structure 7 for electrically leading out the first chip 3 , and attaching the second attachment structure 7 to the second chip 4 includes: on the first chip 3 A second adhesive layer 10 is formed thereon, and the second chip 4 is placed on the second adhesive layer 10; on the second adhesive layer 10, a second conductive column 19, a second conductive column 19, a second conductive column 19 electrically connected to each other are sequentially formed The wiring layer 16 and the second pad 13 ; the second redistribution layer 16 is attached to the pad of the second chip 4 ; the second conductive column 19 is electrically connected to the first conductive column 18 .
具体的，在所述的模块化封装方法中，还包括：在形成所述第一焊盘12、所述第一重布线层15及所述第一导电柱18的步骤之前、之间及之后形成多个第一介质层22，所述第一介质层22暴露部分所述第一焊盘12、所述第一重布线层15及所述第一导电柱18；在形成所述第二导电柱19、所述第二重布线层16及所述第二焊盘13的步骤之前、之间及之后形成多 个第二介质层23，所述第二介质层23暴露部分所述第二焊盘13、所述第二重布线层16及所述第二导电柱19；在所述的模块化封装方法中，还包括：去除所述载片20和所述第一粘合层9。Specifically, in the modular packaging method, the method further includes: before, during and after the steps of forming the first pad 12 , the first redistribution layer 15 and the first conductive pillar 18 . A plurality of first dielectric layers 22 are formed, and the first dielectric layers 22 expose parts of the first pads 12 , the first redistribution layer 15 and the first conductive pillars 18 ; after forming the second conductive A plurality of second dielectric layers 23 are formed before, between and after the steps of the pillar 19 , the second redistribution layer 16 and the second pad 13 , and the second dielectric layer 23 exposes a portion of the second pad The disk 13 , the second redistribution layer 16 and the second conductive pillar 19 ; in the modular packaging method, the method further includes: removing the carrier sheet 20 and the first adhesive layer 9 .
另外，在所述的模块化封装方法中，形成将第三芯片5电性引出的第三附连结构8，将所述第三芯片5附连至第三附连结构8包括：在载片20上形成第三粘合层11，在所述第三粘合层11上依次形成相互电性连接的第三芯片5、第三重布线层17及第三焊盘14；所述第三重布线层17附连至第三芯片5的焊盘；在形成所述第三芯片5、所述第三重布线层17及所述第三焊盘14的步骤之前、之间及之后形成多个第三介质层24，所述第三介质层24暴露部分所述第三芯片5、所述第三重布线层17及所述第三焊盘14；去除所述载片20和所述第三粘合层11。In addition, in the described modular packaging method, forming a third attachment structure 8 for electrically leading out the third chip 5 , and attaching the third chip 5 to the third attachment structure 8 includes: on the carrier sheet A third adhesive layer 11 is formed on the 20, and a third chip 5, a third redistribution layer 17 and a third pad 14 are sequentially formed on the third adhesive layer 11 to be electrically connected to each other; The wiring layer 17 is attached to the pads of the third chip 5 ; before, between and after the steps of forming the third chip 5 , the third redistribution layer 17 and the third pads 14 , a plurality of The third dielectric layer 24, the third dielectric layer 24 exposes part of the third chip 5, the third redistribution layer 17 and the third pad 14; remove the carrier 20 and the third Adhesive layer 11 .
在本发明的一个实施例中，在所述的模块化封装方法中，形成至少一个第一模块1并将至少一个第一模块1堆叠布置包括：将每个第一模块1的第一焊盘12所在的面作为下表面，第二焊盘13所在的面作为上表面；下表面相对下一个第一模块1，上表面相对上一个第一模块1；在所述第一焊盘12上形成第一焊球21，上一个第一模块1的第一焊球21附连至下一个第一模块1的第二焊盘13上；或在所述第二焊盘13上形成第二焊球21，下一个第一模块1的第二焊球21附连至上一个第一模块1的第一焊盘12上。在所述的模块化封装方法中，将第二模块2附连至所述第一模块1上包括：最上一个第一模块1的第二焊盘13上形成第二焊球21，所述第三焊盘14附连至最上一个第一模块1的第二焊球21；或所述第三焊盘14上形成第三焊球21，最上一个第一模块1的第二焊盘13附连至所述第三焊球21。In an embodiment of the present invention, in the modular packaging method, forming at least one first module 1 and stacking the at least one first module 1 includes: placing the first pads of each first module 1 The surface where 12 is located is the lower surface, and the surface where the second pad 13 is located is the upper surface; the lower surface is opposite to the next first module 1, and the upper surface is opposite to the previous first module 1; The first solder ball 21, the first solder ball 21 of the previous first module 1 is attached to the second pad 13 of the next first module 1; or the second solder ball is formed on the second pad 13 21. The second solder balls 21 of the next first module 1 are attached to the first pads 12 of the previous first module 1 . In the described modular packaging method, attaching the second module 2 to the first module 1 includes: forming second solder balls 21 on the second pads 13 of the uppermost first module 1, the first The three bonding pads 14 are attached to the second solder balls 21 of the uppermost first module 1 ; or the third solder balls 21 are formed on the third bonding pads 14 , and the second bonding pads 13 of the uppermost first module 1 are attached to the third solder ball 21 .
在本发明提供的模块化封装结构及方法中，通过堆叠布置的至少一个第一模块1包括相互背对布置的第一芯片3及第二芯片4，附连于所述第一模块1上的第二模块2包括第三芯片5，且所述第三芯片5与一个或多个所述第一芯片3和/或所述第二芯片4中电性连接，实现了模块集成的封装结构，提高了芯片集成度，堆叠布置、相互背对布置避免了弯曲老化， 改善了封装体散热，且传输距离更短，电路寄生和损耗更小，本发明由于模块化设计，实现了多层三维堆叠。In the modular packaging structure and method provided by the present invention, at least one first module 1 arranged by stacking includes a first chip 3 and a second chip 4 arranged opposite to each other, and the chips attached to the first module 1 The second module 2 includes a third chip 5, and the third chip 5 is electrically connected to one or more of the first chips 3 and/or the second chips 4, so as to realize a module-integrated package structure, The chip integration is improved, the stacking arrangement and the arrangement facing each other avoid bending aging, improve the heat dissipation of the package, and the transmission distance is shorter, and the circuit parasitics and losses are smaller. The present invention realizes multi-layer three-dimensional stacking due to the modular design. .
本发明的模块化封装结构及方法具有更高的集成度和封装密度，体积更小；通过引入金属导电柱以及选择覆盖不同热膨胀系数的介质层，提高散热，控制翘曲，也避免了弯折老化的问题，可靠性更高；采用模块化设计，可通过堆叠至少一个第一模块1实现多层三维堆叠；三种芯片之间传输距离小，可有效降低损耗和寄生效应，提高性能。The modular packaging structure and method of the present invention have higher integration and packaging density and smaller volume; by introducing metal conductive columns and selecting dielectric layers covering different thermal expansion coefficients, heat dissipation is improved, warpage is controlled, and bending is avoided. The problem of aging is higher, and the reliability is higher; the modular design can realize multi-layer three-dimensional stacking by stacking at least one first module 1; the transmission distance between the three chips is small, which can effectively reduce the loss and parasitic effect and improve the performance.
本发明通过第一芯片3是射频系统中的数字芯片，其可以用来产生、放大和处理各种数字信号，第二芯片4是射频系统中射频收发芯片，用以对信号进行放大、移相、衰减，第三芯片5是不同的天线模块，用来传输和接受通讯信号，由此组成了射频-数字混合系统，相比于传统的在基板上集成射频元件的封装工艺，本发明不仅有着更高的集成度、更小的损耗，而且能够通过多个不同天线模块的设置满足多频段、多方向等不同的射频应用需求。In the present invention, the first chip 3 is a digital chip in the radio frequency system, which can be used to generate, amplify and process various digital signals, and the second chip 4 is a radio frequency transceiver chip in the radio frequency system, which is used to amplify and phase shift the signal. , attenuation, the third chip 5 is a different antenna module, which is used to transmit and receive communication signals, thus forming a radio frequency-digital hybrid system. Compared with the traditional packaging process of integrating radio frequency components on the substrate, the present invention not only has the advantages of Higher integration, smaller loss, and can meet different RF application requirements such as multi-band and multi-direction through the setting of multiple different antenna modules.
在本发明的一个实施例中，第一模块1的制作方法包括：In an embodiment of the present invention, the manufacturing method of the first module 1 includes:
如图1所示，提供一载片20，在载片20正面覆盖第一粘合层9，然后在第一粘合层9上形成第一焊盘12。As shown in FIG. 1 , a carrier sheet 20 is provided, the front side of the carrier sheet 20 is covered with the first adhesive layer 9 , and then the first pads 12 are formed on the first adhesive layer 9 .
如图2所示，然后覆盖第一介质层22，使得第一焊盘12露出，然后再第一介质层22上制作第一重布线层15。第一重布线层15和第一焊盘12连通。As shown in FIG. 2 , the first dielectric layer 22 is then covered to expose the first pads 12 , and then the first redistribution layer 15 is formed on the first dielectric layer 22 . The first redistribution layer 15 is communicated with the first pad 12 .
如图3所示，先在第一重布线层15上方覆盖第二层的第一介质层22，使得第一重布线层15露出，然后在第一重布线层15露出的位置形成第一导电柱18，第一导电柱18与第一重布线层15电连通。As shown in FIG. 3 , the first dielectric layer 22 of the second layer is first covered over the first redistribution layer 15 so that the first redistribution layer 15 is exposed, and then a first conductive layer is formed at the exposed position of the first redistribution layer 15 The pillar 18 , the first conductive pillar 18 is in electrical communication with the first redistribution layer 15 .
如图4所示，提供第一芯片3，将第一芯片3放置在第一重布线层15上方，第一芯片3通过焊球21与第一重布线层15电连通。然后覆盖第三层的第一介质层22，第三层介质层与第一芯片3背面持平，并且露出第一导电柱18。As shown in FIG. 4 , a first chip 3 is provided, placed over the first redistribution layer 15 , and the first chip 3 is electrically connected to the first redistribution layer 15 through solder balls 21 . Then, the first dielectric layer 22 of the third layer is covered, the third dielectric layer is flush with the back surface of the first chip 3 , and the first conductive pillars 18 are exposed.
如图5所示，先在上表面制作第二导电柱19，第二导电柱19与第一导电柱18连通，然后放置第二芯片4，第二芯片4焊盘面朝上，通过第二粘 合层10放置在第一芯片3上面，第二芯片4焊盘面与第二导电柱19表面持平。As shown in FIG. 5 , firstly, the second conductive pillar 19 is formed on the upper surface, and the second conductive pillar 19 is connected with the first conductive pillar 18 , and then the second chip 4 is placed, with the pads of the second chip 4 facing upward. The bonding layer 10 is placed on the first chip 3 , and the pad surface of the second chip 4 is flush with the surface of the second conductive pillar 19 .
如图6所示，先覆盖一层第二介质层23，第二介质层23与第二芯片4焊盘面和第二导电柱19上表面持平，然后制作第二重布线层16，第二重布线层16与第二芯片4焊盘和第二导电柱19电连通。As shown in FIG. 6 , a second dielectric layer 23 is firstly covered, and the second dielectric layer 23 is flush with the pad surface of the second chip 4 and the upper surface of the second conductive pillar 19 , and then the second redistribution layer 16 is fabricated. The wiring layer 16 is in electrical communication with the pads of the second chip 4 and the second conductive pillars 19 .
如图7所示，形成一层图形化的第二介质层23，然后制作第二焊盘13(或直接形成第二焊球21)，第二焊盘13(焊球21)与第二重布线层16电连通。As shown in FIG. 7 , a patterned second dielectric layer 23 is formed, and then the second pads 13 (or the second solder balls 21 are directly formed), the second pads 13 (solder balls 21 ) and the second layer of The wiring layer 16 is in electrical communication.
如图8所示，去除载片20和第一粘合层9。各个第一介质层22之间、和/或第二介质层23之间可选择不同膨胀系数的材料，使得各材料之间的应力匹配，减少翘曲。As shown in FIG. 8, the carrier sheet 20 and the first adhesive layer 9 are removed. Materials with different expansion coefficients can be selected between each of the first dielectric layers 22 and/or between the second dielectric layers 23, so that the stress between the materials can be matched and warpage can be reduced.
在本发明的一个实施例中，第二模块2的制作方法包括：In an embodiment of the present invention, the manufacturing method of the second module 2 includes:
如图9所示，在载片20上表面覆盖第三粘合层11，然后在第三粘合层11上制作第三介质层24。As shown in FIG. 9 , the upper surface of the carrier sheet 20 is covered with the third adhesive layer 11 , and then the third dielectric layer 24 is formed on the third adhesive layer 11 .
如图10、11所示，在第三介质层24上放置至少一个第三芯片5，第三芯片5焊盘面朝上，然后再覆盖一层第三介质层24，该层的第三介质层24的上表面与第三芯片5焊盘面持平。本实施例对第三芯片5的数量和位置不做限制，实际作业时可以根据实际需求放置不同数量的第三芯片5并根据需求任意排布第三芯片5的位置。As shown in FIGS. 10 and 11 , at least one third chip 5 is placed on the third dielectric layer 24 with the pads of the third chip 5 facing upward, and then a third dielectric layer 24 is covered. The upper surface of 24 is flush with the pad surface of the third chip 5 . This embodiment does not limit the number and position of the third chips 5 , and different numbers of the third chips 5 can be placed according to actual requirements and the positions of the third chips 5 can be arbitrarily arranged according to the actual operation.
如图12所示，制作第三重布线层17，第三重布线层17与第三芯片5焊盘电连通，然后覆盖一层图形化的第三介质层24，使得第三重布线层17露出。As shown in FIG. 12 , the third redistribution layer 17 is fabricated, the third redistribution layer 17 is electrically connected to the pads of the third chip 5 , and then a patterned third dielectric layer 24 is covered, so that the third redistribution layer 17 exposed.
如图13所示，制作第三焊盘14(或直接形成第三焊球21)，第三焊球21与第三重布线层17电连通。As shown in FIG. 13 , the third pads 14 are formed (or the third solder balls 21 are directly formed), and the third solder balls 21 are electrically connected to the third redistribution layer 17 .
如图14所示，去除载片20和第三粘合层11。As shown in FIG. 14, the carrier sheet 20 and the third adhesive layer 11 are removed.
一个或多个第一模块1集成、以及第一模块1与第二模块2集成如图15、16所示。将第一模块1堆叠，通过焊球21固定并在模块间实现电连接。在实际堆叠集成时，可先堆叠至少1个第一模块1，再堆叠一个第二模块2。本发明的一个射频领域的应用实例为：第一芯片3可以是射频系 统中的数字芯片，其可以用来产生、放大和处理各种数字信号；第二芯片4可以是射频系统中射频收发芯片，用以对信号进行放大、移相、衰减；第三芯片5可以是不同的天线模块，用来传输和接受通讯信号。由此可以组成射频-数字混合系统，相比于传统的在基板上集成射频元件的封装工艺，本封装实例不仅有着更高的集成度、更小的损耗，而且能够通过多个不同天线模块的设置满足多频段、多方向等不同的射频应用需求。The integration of one or more first modules 1 and the integration of the first module 1 and the second module 2 are shown in FIGS. 15 and 16 . The first modules 1 are stacked, fixed by solder balls 21 and electrically connected between the modules. During actual stacking and integration, at least one first module 1 may be stacked first, and then a second module 2 may be stacked. An application example of the present invention in the field of radio frequency is: the first chip 3 can be a digital chip in a radio frequency system, which can be used to generate, amplify and process various digital signals; the second chip 4 can be a radio frequency transceiver chip in the radio frequency system , used to amplify, shift, and attenuate the signal; the third chip 5 can be a different antenna module, used to transmit and receive communication signals. As a result, a radio frequency-digital hybrid system can be formed. Compared with the traditional packaging process of integrating radio frequency components on the substrate, this packaging example not only has a higher integration level and lower loss, but also can pass through multiple different antenna modules. The settings meet different RF application requirements such as multi-band and multi-direction.
现有技术的封装有叠层数限制，无法模块化作业，而本发明通过的第一模块正反面均有电路引脚，可以根据实际需求进行多次堆叠；本发明的第一模块在结构上几乎是上下对称的，通过这一点可以在不选取热膨胀系数匹配的介质层的情况下也能达到翘曲平衡的目的，增加最终封装提的可靠性。克服了现有技术中由于封装体内上下结构并不对称，因此只能通过选取热膨胀系数匹配的介质层材料来实现翘曲平衡的缺陷。The packaging of the prior art is limited in the number of layers and cannot be modularized, while the first module adopted by the present invention has circuit pins on the front and back, which can be stacked multiple times according to actual needs; the first module of the present invention is structurally It is almost symmetrical up and down. Through this, the warpage balance can be achieved without selecting a dielectric layer with a matching thermal expansion coefficient, and the reliability of the final package can be increased. It overcomes the defect in the prior art that warpage balance can only be achieved by selecting dielectric layer materials with matching thermal expansion coefficients because the upper and lower structures in the package are not asymmetrical.
综上，上述实施例对模块化封装结构及方法的不同构型进行了详细说明，当然，本发明包括但不局限于上述实施中所列举的构型，任何在上述实施例提供的构型基础上进行变换的内容，均属于本发明所保护的范围。本领域技术人员可以根据上述实施例的内容举一反三。To sum up, the above embodiments have described in detail the different configurations of the modular packaging structure and method. Of course, the present invention includes but is not limited to the configurations listed in the above embodiments, any configuration basis provided in the above embodiments The contents of the above transformation all belong to the scope of protection of the present invention. Those skilled in the art can draw inferences from the contents of the foregoing embodiments.
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的系统而言，由于与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the method.
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure all belong to the protection scope of the claims.

Claims (10)

  1. 一种模块化封装结构，其特征在于，包括：A modular packaging structure, characterized in that it includes:
    堆叠布置的至少一个第一模块，均包括相互背对布置的第一芯片及第二芯片，所述第一芯片电性引出至所述第一模块的第一表面和/或第二表面，所述第二芯片电性引出至所述第一模块的第一表面和/或第二表面；At least one first module arranged in a stack includes a first chip and a second chip arranged opposite to each other, the first chip is electrically led out to the first surface and/or the second surface of the first module, so the second chip is electrically led out to the first surface and/or the second surface of the first module;
    附连于所述第一模块上的第二模块，其包括第三芯片，所述第三芯片电性引出至所述第二模块的第一表面和/或第二表面；a second module attached to the first module, comprising a third chip, the third chip being electrically led out to the first surface and/or the second surface of the second module;
    所述第二模块与第一模块电性连接。The second module is electrically connected to the first module.
  2. 如权利要求1所述的模块化封装结构，其特征在于，The modular packaging structure of claim 1, wherein:
    所述第一芯片为射频系统数字芯片，用于产生、放大和处理数字信号；The first chip is a radio frequency system digital chip, used for generating, amplifying and processing digital signals;
    所述第二芯片为射频收发芯片，用于放大、移相和衰减射频信号；The second chip is a radio frequency transceiver chip, used for amplifying, phase shifting and attenuating radio frequency signals;
    所述第三芯片为天线模块，用于传输和接收射频信号。The third chip is an antenna module for transmitting and receiving radio frequency signals.
  3. 一种模块化封装方法，其特征在于，包括：A method for modular packaging, comprising:
    形成至少一个第一模块并将至少一个第一模块堆叠布置，将第二模块附连至所述第一模块上；forming at least one first module and arranging the at least one first module in a stack, attaching a second module to the first module;
    所述第一模块通过以下步骤制备：The first module is prepared by the following steps:
    形成将第一芯片电性引出的第一附连结构，将所述第一芯片附连至第一附连结构；forming a first attachment structure electrically leading out the first chip, and attaching the first chip to the first attachment structure;
    将第二芯片布置为与所述第一芯片相互背对；arranging the second chip facing away from the first chip;
    形成将所述第二芯片电性引出的第二附连结构，第二附连结构附连至所述第二芯片；forming a second attachment structure electrically leading out the second chip, the second attachment structure being attached to the second chip;
    所述第二模块通过以下步骤制备：The second module is prepared by the following steps:
    形成将第三芯片电性引出的第三附连结构，将所述第三芯片附连至第三附连结构；forming a third attachment structure electrically leading out the third chip, and attaching the third chip to the third attachment structure;
    所述第三附连结构与一个或多个所述第一附连结构和/或所述第二附连结构电性连接。The third attachment structure is electrically connected to one or more of the first attachment structure and/or the second attachment structure.
  4. 如权利要求3所述的模块化封装方法，其特征在于，形成将第一芯片电性引出的第一附连结构，将所述第一芯片附连至第一附连结构包括：3. The modular packaging method of claim 3, wherein forming a first attachment structure for electrically leading out the first chip, and attaching the first chip to the first attachment structure comprises:
    在载片上形成第一粘合层，在所述第一粘合层上依次形成相互电性连 接的第一焊盘、第一重布线层及第一导电柱；A first adhesive layer is formed on the carrier sheet, and the first bonding pad, the first redistribution layer and the first conductive column electrically connected to each other are sequentially formed on the first adhesive layer;
    第一芯片的焊盘附连至所述第一重布线层。The pads of the first chip are attached to the first redistribution layer.
  5. 如权利要求4所述的模块化封装方法，其特征在于，形成将第一芯片电性引出的第二附连结构，第二附连结构附连至所述第二芯片包括：5. The modular packaging method of claim 4, wherein forming a second attachment structure electrically leading out the first chip, the second attachment structure being attached to the second chip comprises:
    在第一芯片上上形成第二粘合层，forming a second adhesive layer on the first chip,
    将第二芯片放置于第二粘合层上；placing the second chip on the second adhesive layer;
    在所述第二粘合层上依次形成相互电性连接的第二导电柱、第二重布线层及第二焊盘；forming a second conductive column, a second redistribution layer and a second pad that are electrically connected to each other in sequence on the second adhesive layer;
    所述第二重布线层附连至第二芯片的焊盘；the second redistribution layer is attached to the pads of the second chip;
    所述第二导电柱与所述第一导电柱电性连接。The second conductive column is electrically connected to the first conductive column.
  6. 如权利要求5所述的模块化封装方法，其特征在于，还包括：The modular packaging method of claim 5, further comprising:
    在形成所述第一焊盘、所述第一重布线层及所述第一导电柱的步骤之前、之间及之后形成多个第一介质层，所述第一介质层暴露部分所述第一焊盘、所述第一重布线层及所述第一导电柱；A plurality of first dielectric layers are formed before, between, and after the steps of forming the first pad, the first redistribution layer, and the first conductive pillar, the first dielectric layers exposing a portion of the first dielectric layer. a pad, the first redistribution layer and the first conductive column;
    在形成所述第二导电柱、所述第二重布线层及所述第二焊盘的步骤之前、之间及之后形成多个第二介质层，所述第二介质层暴露部分所述第二焊盘、所述第二重布线层及所述第二导电柱；A plurality of second dielectric layers are formed before, between, and after the steps of forming the second conductive pillar, the second redistribution layer, and the second pad, the second dielectric layers exposing a portion of the first two bonding pads, the second redistribution layer and the second conductive pillar;
  7. 如权利要求5所述的模块化封装方法，其特征在于，还包括：去除所述载片和所述第一粘合层。6. The modular packaging method of claim 5, further comprising: removing the carrier sheet and the first adhesive layer.
  8. 如权利要求5所述的模块化封装方法，其特征在于，形成将第三芯片电性引出的第三附连结构，将所述第三芯片附连至第三附连结构包括：6. The modular packaging method of claim 5, wherein forming a third attachment structure for electrically leading out the third chip, and attaching the third chip to the third attachment structure comprises:
    在载片上形成第三粘合层，在所述第三粘合层上依次形成相互电性连接的第三芯片、第三重布线层及第三焊盘；forming a third adhesive layer on the carrier sheet, and sequentially forming a third chip, a third redistribution layer and a third pad that are electrically connected to each other on the third adhesive layer;
    所述第三重布线层附连至第三芯片的焊盘；the third redistribution layer is attached to the pads of the third chip;
    在形成所述第三芯片、所述第三重布线层及所述第三焊盘的步骤之前、之间及之后形成多个第三介质层，所述第三介质层暴露部分所述第三芯片、所述第三重布线层及所述第三焊盘；A plurality of third dielectric layers are formed before, between, and after the steps of forming the third chip, the third redistribution layer, and the third pad, the third dielectric layers exposing portions of the third a chip, the third redistribution layer and the third pad;
    去除所述载片和所述第三粘合层。The slide and the third adhesive layer are removed.
  9. 如权利要求8所述的模块化封装方法，其特征在于，形成至少一个 第一模块并将至少一个第一模块堆叠布置包括：The modular packaging method of claim 8, wherein forming the at least one first module and arranging the at least one first module in a stack comprises:
    将每个第一模块的第一焊盘所在的面作为下表面，第二焊盘所在的面作为上表面；Take the surface where the first pad of each first module is located as the lower surface, and the surface where the second pad is located as the upper surface;
    下表面相对下一个第一模块，上表面相对上一个第一模块；The lower surface is relative to the next first module, and the upper surface is relative to the previous first module;
    在所述第一焊盘上形成第一焊球，上一个第一模块的第一焊球附连至下一个第一模块的第二焊盘上；或forming first solder balls on said first pads, the first solder balls of the previous first module being attached to the second pads of the next first module; or
    在所述第二焊盘上形成第二焊球，下一个第一模块的第二焊球附连至上一个第一模块的第一焊盘上。A second solder ball is formed on the second pad, and the second solder ball of the next first module is attached to the first pad of the previous first module.
  10. 如权利要求9所述的模块化封装方法，其特征在于，将第二模块附连至所述第一模块上包括：10. The modular packaging method of claim 9, wherein attaching the second module to the first module comprises:
    最上一个第一模块的第二焊盘上形成第二焊球，所述第三焊盘附连至最上一个第一模块的第二焊球；或a second solder ball is formed on the second pad of the uppermost first module, and the third pad is attached to the second solder ball of the uppermost first module; or
    所述第三焊盘上形成第三焊球，最上一个第一模块的第二焊盘附连至所述第三焊球。A third solder ball is formed on the third pad, and the second pad of the uppermost first module is attached to the third solder ball.
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