CN113671444B - FPGA-based radar echo signal acquisition/playback microsystem circuit chip - Google Patents

Abstract

The invention belongs to the technical field of radar digital signal processing, and particularly discloses a radar echo signal acquisition/playback microsystem circuit chip based on an FPGA, wherein a system-level package is adopted, an internal substrate is a multilayer high-density ceramic cavity substrate, a signal acquisition/playback module is arranged on a left side panel of the substrate, and a signal preprocessing module is arranged on a right side panel of the substrate; the signal acquisition/playback module comprises four ADC chips and two DAC chips; during signal acquisition, the signal preprocessing module is used for performing down-conversion processing on data acquired by the ADC chip; when the signal is replayed, the signal preprocessing module is used for carrying out up-conversion processing on the medium-frequency radar signal; the signal preprocessing module comprises an FPGA, an ARM, four DDR3, a power chip and a FLASH. The invention realizes the collection/playback of the radar echo signals of 8 paths of channels and the localization of chips thereof, thereby realizing the miniaturization of the system.

Description

FPGA-based radar echo signal acquisition/playback microsystem circuit chip

Technical Field

The invention relates to the technical field of electronics, in particular to a radar echo signal acquisition/playback microsystem circuit chip based on an FPGA, which is designed by adopting the technologies of MST (Microsystems Technology), MCM (muti-chip module), siP (System In Package), TSV (Through-silicon Vias) and RDL (Re-Distribution Layer) to acquire or play back radar signals and can be used for acquiring and playing back the radar signals.

Background

With the development of electronic technology, the hardware implementation of a system is more and more complex, the integration level is higher and higher, and the microelectronic technology is also in the era of nano-electronics and integrated microsystems, so that new requirements are put forward for system design, and miniaturization and modularization become unavoidable requirements; moreover, most radar signal acquisition systems at present adopt foreign chips, so that the requirements of localization cannot be met, and the radar signal acquisition systems are always in the reach of people under the current international relation background.

In the method for realizing the microsystem, the most common method is the SiP technology, namely the system-in-package, which is a new technology developed on the basis of the SoC (system-in-chip), and compared with the SoC, the SiP technology has the advantages of short development period, low cost and low price, and simultaneously has the advantages of excellent performance, small volume and light weight.

Disclosure of Invention

Aiming at the problems existing in the prior art, the invention aims to provide a radar echo signal acquisition/playback microsystem circuit chip based on FPGA, which adopts MST (Microsystems Technology) and SiP (System In Package) technologies to realize the acquisition/playback of radar echo signals of 8 paths of channels, realizes the localization of chips for the acquisition/playback of multichannel radar echo signals, adopts bare chip design, has the whole volume of 40X 5mm, and realizes the miniaturization of the system; meanwhile, through packaging and filling, errors among signal wires are smaller, and the reliability of the system is improved.

In order to achieve the above purpose, the present invention is realized by the following technical scheme.

The radar echo signal acquisition/playback microsystem circuit chip based on the FPGA adopts system-level packaging, an external packaging mode adopts solder ball array packaging, an internal substrate is a multilayer high-density ceramic cavity substrate, the multilayer high-density ceramic cavity substrate is square, a signal acquisition/playback module is arranged on the left side panel of the multilayer high-density ceramic cavity substrate, and a signal preprocessing module is arranged on the right side panel of the multilayer high-density ceramic cavity substrate;

the signal acquisition/playback module is used for acquiring and playing back radar echo signals and comprises four ADC chips and two DAC chips, wherein each two ADC chips are stacked together to form an ADC chip laminated body, the first ADC chip laminated body is positioned at the upper left corner of the substrate, and the second ADC chip laminated body is positioned under the first ADC chip laminated body and aligned with the first ADC chip laminated body; two DAC chips are stacked together to form a DAC chip laminated body, and the DAC chip laminated body is positioned at the lower right corner of the substrate;

during signal acquisition, the signal preprocessing module is used for performing down-conversion processing on data acquired by the ADC chip; during signal playback, the signal preprocessing module is used for performing up-conversion processing on the intermediate frequency radar signal, and transmitting the signal to the DAC through the JESD 204B; the signal preprocessing module comprises an FPGA, an ARM, four DDR3, a power chip and a FLASH, wherein every two DDR3 are stacked together to form a DDR3 laminated body; the two DDR3 laminated bodies are arranged side by side and positioned at the upper right corner of the substrate, and FLASH and a power supply chip are respectively arranged under the two DDR3 laminated bodies; ARM is positioned at the lower right corner of the substrate, and FPGA is positioned between ARM and DAC chip lamination; four DDR3, a power chip and a FLASH are packaged by adopting MCM technology to form a DDR3 package body, a clock module is arranged between the package body and the FPGA, the clock module comprises at least two clock chips, one clock chip is respectively connected with the FPGA and the ARM in a unidirectional manner to provide a system clock and a high-speed interface clock for the FPGA, and one clock chip is respectively connected with the ADC chip and the two DAC chips in a unidirectional manner to provide a working clock for the FPGA and the ARM.

Further, a pad is arranged between adjacent laminated chips in the ADC chip laminated body, the DAC chip laminated body and the DDR3 laminated body, and the pad is connected with the substrate through a bonding wire.

Further, the 4 ADC chips respectively and correspondingly acquire the direction, distance, speed and target shape information of the radar signals.

Furthermore, the DDR3 package adopts a pyramid stacking structure, namely a first medium layer is arranged on the substrate, a power chip and FLASH are welded on the right surface of the first medium layer, a second medium layer is arranged on the left surface of the first medium layer, and two DDR3 stacks are welded on the second medium layer.

Further, a silicon adapter plate is arranged between the FPGA and the substrate, the FPGA is flip-chip welded on the silicon adapter plate, the silicon adapter plate is welded with the substrate, and the FPGA is directly communicated with the substrate through a silicon through hole.

Further, the crystal oscillator of the clock module is selected from an 8MHz passive crystal oscillator, a 50MHz active single-ended crystal oscillator and a 125MHz active differential crystal oscillator, wherein the 8MHz passive crystal oscillator is used for providing a system clock of ARM, the 50MHz active single-ended crystal oscillator is used for providing a system clock of an FPGA, the FPGA is internally provided with a PLL core, frequency multiplication and frequency division of the system clock are realized, the 125MHz active differential crystal oscillator is converted into an LVDS clock level from the LVPECL clock level through a fan-out chip by using a clock level conversion network, and the clock is used for providing a clock of a high-speed interface of the FPGA.

Further, the ARM selects GD32503 series, and part of ARM extraction IO is used for power-on and load control of the FPGA; ARM is connected with FPGA through GPIO; the FPGA adopts JFM VX690T, and the FPGA is externally hung with FLASH through an SPI bus, so that the FPGA externally leads out user IO, thereby providing convenience for subsequent circuit expansion of the user; the FPGA is externally led out of a high-speed interface and is used for outputting the preprocessed radar acquisition signals.

Further, the ADC selects GM4680, and the DAC adopts GMD9154C.

Compared with the prior art, the invention has the beneficial effects that:

(1) The microsystem chips are domestic chips, so that hundred percent domestic design is realized, and the problem that key chips of a radar signal acquisition and playback system are subject to foreign places is solved;

(2) The invention reduces the volume of the system and increases the reliability of the system through the lamination design and layout of the chips, adopts MCM technology to package DDR3, fully considers the capacity and bit width of DDR3, and further increases the integration level of the system; in addition, the bare chips are adopted for design, so that the whole volume reaches 40 multiplied by 5mm, the miniaturization of the system is realized, meanwhile, the errors among signal wires are smaller through further packaging and filling, and the reliability of the system is improved.

(3) The micro-system realizes the acquisition and playback of radar signals of more channels, integrates the AD acquisition and the DA playback, realizes the acquisition and the playback of radar echo signals with the bandwidth of 2GHz analog 3dB input signals of 8 channels, pre-processes the acquired data, transmits the data to a subsequent system through a high-speed interface, also inputs digital signals through a high-speed interface, realizes the playback output of the radar signals through a DAC after processing, encapsulates the board-level functions in the micro-system, and realizes the modularization of the system functions.

(4) In the invention, the FPGA and the ARM are interconnected through the GPIO, the system control function is completed by the ARM, including power-on control, current monitoring, temperature monitoring and control of the system working mode, and the system enters a low-power mode when not working or waiting, so as to reduce the power consumption and heating of the system, increase the stability and reliability of the system, prolong the service life of the system, and the hardware programmability of the FPGA can realize the customization of an ARM hardware interface, so that the system has the advantages of the FPGA in hardware and the ARM in software.

Drawings

The invention will now be described in further detail with reference to the drawings and to specific examples.

FIG. 1 is a schematic block diagram of an FPGA-based radar echo signal acquisition/playback microsystem circuit chip of the present invention;

FIG. 2 is a schematic block diagram of a clock circuit design of the present invention;

FIG. 3 is a schematic diagram of a microsystem package of the present invention;

FIG. 4 is a schematic diagram of a DDR3 package of the present invention;

FIG. 5 is a schematic diagram of the connection of an FPGA to a substrate according to the present invention;

FIG. 6 is a schematic diagram showing the connection between a laminate and a substrate according to the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to examples, but it will be understood by those skilled in the art that the following examples are only for illustrating the present invention and should not be construed as limiting the scope of the present invention.

With the development of modern integrated circuits, how to improve the integration level of the system and stability become the main problem of circuit system design, under the conditions that the system is more and more complex and the performance requirement is higher and higher, the structure and packaging form of the system are improved, and with the improvement of the requirement of the circuit system, various methods for improving the structure of the system and the packaging process are more and more mature, however, in the system design, due to the reasons of threshold and cost, the existing radar signal acquisition and playback system mostly adopts PCB board card design, and aiming at the current situation, the invention provides a microsystem design based on radar signal acquisition and playback.

Example 1

Aiming at the current situation, based on MST (Microsystems Technology) microsystem technology, an MCM (multi-chip module) multi-chip module, siP (System In Package) system level packaging technology, TSV (Through-silicon Vias) technology and RDL (Re-Distribution Layer) technology are utilized to design a microsystem circuit chip based on radar signal acquisition/playback, and referring to fig. 1-3, the microsystem circuit chip based on FPGA is provided, and adopts system level packaging, adopts solder ball array packaging for external packaging, and an inner substrate is a multilayer high-density ceramic cavity substrate, wherein the multilayer high-density ceramic cavity substrate is square, a signal acquisition/playback module is arranged on a left side panel and a signal preprocessing module is arranged on a right side panel;

the signal acquisition/playback module is used for acquiring and playing back radar echo signals and comprises four ADC chips and two DAC chips, wherein each two ADC chips are stacked together to form an ADC chip laminated body, the first ADC chip laminated body is positioned at the upper left corner of the substrate, and the second ADC chip laminated body is positioned under the first ADC chip laminated body and aligned with the first ADC chip laminated body; two DAC chips are stacked together to form a DAC chip laminated body, and the DAC chip laminated body is positioned at the lower right corner of the substrate;

during signal acquisition, the signal preprocessing module is used for performing down-conversion processing on data acquired by the ADC chip; during signal playback, the signal preprocessing module is used for performing up-conversion processing on the intermediate frequency radar signal, and transmitting the signal to the DAC through the JESD 204B; the signal preprocessing module comprises an FPGA, an ARM, four DDR3, a power chip and a FLASH, wherein every two DDR3 are stacked together to form a DDR3 laminated body; the two DDR3 laminated bodies are arranged side by side and positioned at the upper right corner of the substrate, and FLASH and a power supply chip are respectively arranged under the two DDR3 laminated bodies; ARM is positioned at the lower right corner of the substrate, and FPGA is positioned between ARM and DAC chip lamination; four DDR3, a power chip and a FLASH are packaged by adopting MCM technology to form a DDR3 package body, a clock module is arranged between the package body and the FPGA, the clock module comprises at least two clock chips, one clock chip is respectively connected with the FPGA and the ARM in a unidirectional manner to provide a system clock and a high-speed interface clock for the FPGA, and one clock chip is respectively connected with the ADC chip and the two DAC chips in a unidirectional manner to provide a working clock for the FPGA and the ARM.

In the microsystem circuit chip for radar signal acquisition/playback, the control function is completed by ARM, the matching of IO number and level is fully considered in the aspect of ARM type selection, the ARM selects GD32503 series, part of ARM extraction IOs are used for power-on and load control of an FPGA, and meanwhile, the ARM completes current monitoring, temperature monitoring and the like of a system and is connected with the FPGA through GPIO.

The processing chip of the core of the invention adopts the form of FPGA+ARM, so that the system has the advantages of the FPGA and the ARM in terms of hardware and software, the FPGA adopts JFM7VX690T, is a high-performance FPGA, has the field programmable characteristic, has a large number of programmable resources which can be flexibly configured, comprises programmable modules such as I/O, block RAM, DSP, MMCM, GTX and the like, is convenient for expansion design, the FPGA mainly completes the preprocessing of radar signals, the FPGA is externally hung with FLASH through an SPI bus, the FLASH is used as the final solidification of a system program, and is externally hung with 64-bit DDR3, in order to further increase the integration level of the system, the capacity and the bit width of the DDR3 are fully considered, the DDR3 is packaged by adopting the MCM technology, and particularly shown in FIG. 4, the FPGA is provided with a large number of user IOs for flexible application when a circuit is expanded, and meanwhile, the series of FPGAs have a large number of high-speed interfaces for outputting the acquisition signals after the preprocessing, can be used for interconnection with the data processing module, and the high-speed transmission of data can be realized, and the application in the system is convenient.

Referring to fig. 1, matching of the number of IOs and the level is fully considered in the aspect of ARM type selection, an ARM selects GD32503 series, an FPGA provides a programmable peripheral circuit for the ARM, the ARM can provide convenient software processing capacity, an ADC chip adopts 4 pieces of GM4680, GM4680 adopts a single core design, supports a 2GHz analog 3dB input signal bandwidth, supports a 1.4 to 2.2VP-P wide range input range, embeds a DDC frequency conversion path and a 1/200Cycle group delay filter, and can realize 8-channel AD conversion and 8-channel DDC (digital down conversion) output; the AD chip and the FPGA are connected through JESD 204B. The DAC chip adopts the GMD9154C, the GMD9154C is a 4-channel DAC, the bit width is 16 bits, the digital signal processor is connected with the FPGA through the JESD204B, the clock circuit fully considers the current situation of the current domestic clock chip, the current domestic immature configurable clock chip is not used, the chip with the clock fan-out and the clock circuit are adopted to provide the working clock for the micro system, all core chips required by the system adopt domestic bare chips, the whole system localization is realized, and the miniaturization and modularization of the radar signal acquisition and playback system are realized.

In the system, ARM control finishes the power-on and program loading of the FPGA, finishes the initialization of the system, a clock network provides a system clock and a reference clock of a high-speed link for the FPGA, and also provides working clocks for the ADC and the DAC chips, 4 ADC chips respectively finish the acquisition and the digitization of the direction, the distance, the speed and the target shape information of radar signals, digital information is transmitted to the FPGA through the JESD204B connection with the FPGA, the FPGA carries out DDC (digital down conversion) on the signals, and data is transmitted to a data processing module through a high-speed interface externally led out by the FPGA for further processing of the signals; meanwhile, the playback of the radar echo signal can also be performed by performing DUC (digital up-conversion) on digital information of the direction, distance, speed and target shape of the radar signal of the intermediate frequency, and then transmitting the signal to the DAC through JESD 204B.

Example 2

In order to realize localization of radar signal acquisition and playback microsystems, the current situation of a current domestic clock chip is considered, a clock chip with fan-out of a clock circuit and a clock network which is designed independently provide a system clock for an FPGA, a high-speed interface clock provides a system clock for an ARM, and a working clock for an ADC chip, referring to FIG. 2, the three types of the 8MHz passive crystal oscillator, the 50MHz active single-ended crystal oscillator and the 125MHz active differential crystal oscillator are considered, the 8MHz passive crystal oscillator is used for providing the system clock of the ARM, the 50MHz active single-ended crystal oscillator is used for providing the system clock of the FPGA, the FPGA is internally provided with a PLL core, frequency multiplication and frequency division of the system clock can be realized, the collected signals are preprocessed conveniently, the 125MHz active differential crystal oscillator is converted into the LVPECL clock level through a fan-out chip, the clock of a clock level is used for providing the clock of a high-speed interface of the FPGA, the current situation of a signal processing module is fully considered when the reference clock frequency of the high-speed interface is selected, and the 125M differential clock is selected as the reference clock of the high-speed interface, and the full-speed signal processing module can be used for carrying out compatible data transmission processing.

Example 3

Referring to fig. 4 and 6, in order to reduce the area of the circuit occupied by DDR3, MCM-C technology, i.e., MCM using a multi-layer ceramic substrate, is used for DDR3, and the MCM technology has high packaging efficiency, low cost and mature process technology, 4 CSP (chip size package) of DDR3 is assembled on the multi-layer ceramic substrate, the substrate is a low temperature co-fired ceramic substrate, wire Bonding process is used for on-chip interconnection, and the overall size of MCM package is 20×13mm. In the module packaging, besides DDR3, a power chip for supplying power to the DDR3 and a FLASH are also packaged, and are used for providing proper storage design for a suitable system, so that a module composed of 4 DDR3 meets the requirements of the system on DDR3 bit width and storage capacity and further improves the integration level of the system.

In order to meet the requirements of system-in-package on miniaturization and modularization, all chips are designed in a bare chip mode, referring to fig. 3, fig. 3 is a schematic diagram of a microsystem integral package, the microsystem adopts a system-in-package technology, the obvious advantage of the system-in-package is that different IC processes can be integrated together, in the invention, the SiP package comprises CSP, TSV, RDL, MCM and other package technologies, the integral package size is 40×40×5mm, the external package is BGA package, the internal circuit substrate is a multilayer high-density ceramic cavity substrate, in the schematic diagram of the package, pyramid stacked packages are adopted for the chips with different sizes, the upper layer and the lower layer are connected to the substrate by bonding wires, and in the invention, smaller chips including a clock network, conversion chips and the like are stacked in a pyramid stacked mode and stacked on the larger chips. For chips with the same size, gaskets are added between the chips, the height of an upper chip is increased, bonding space is reserved for a lower chip, in the invention, an ADC and a DAC are both in a stacking mode, for DDR3, DDR3 is further packaged in consideration of domestic chips, and the DDR3 is packaged by adopting a stacking and silicon adapter plate adding mode; the FPGA is connected to the silicon adapter plate in a flip-chip bonding mode, and is connected to the substrate Through a TSV (Through-silicon via), and the idle IO is led out Through an RDL (Re-Distribution Layer) technology, so that the original design of the idle IO of the FPGA can be changed, the interval between the IOs is increased, and the reliability of the system is improved; meanwhile, the design of partial IC circuits is replaced, the time of system design is reduced, and most importantly, the circuit has higher expandability due to the extraction of IO. FPGA and ARM are placed at the lower position, FLAH and MCM packaged DDR3 are placed at the upper position, and during placement, the critical wiring part for system signal transmission is avoided as much as possible, and the inside of the microsystem is interconnected with the external pins by adopting bonding wires.

In summary, the invention designs a micro system based on radar signal acquisition/playback by utilizing MCM and SiP packaging technology on the basis of adopting MST technology, the whole system comprises 4 AD chips with double channels and 2 DA chips with 4 channels, the AD conversion and DA conversion of 8 paths of signals can be realized, meanwhile, FPGA with a large number of programmable resources is packaged, a large number of user IOs are provided, the expansion of system functions and the pretreatment of signals are realized, in addition, the bare chips of the whole micro system are all made of domestic devices, the hundred percent localization of the whole system is realized, meanwhile, the requirements of the subsequent system localization are fully considered in the design, and the compatible design is also carried out for the current domestic signal processing module when the user interconnection resources are led out, so that the micro system is more suitable for the use of domestic radar systems.

In addition, the invention can replay radar echo data, store test data, conveniently replay radar image data in field experiments and simulate experiments, thereby greatly reducing test cost and time. In the test stage, a large number of field experiments are required to be carried out on the radar system according to the application scene, the functions and the performances of the radar system are verified, and the experiments are often high in cost and are not suitable for repeated verification for many times according to the application scene of the radar system; therefore, after the field experiment, if the radar system is required to be tested for multiple times, the collected and stored waveform data of the field experiment are only required to be played back for the simulation experiment.

While the invention has been described in detail in this specification with reference to the general description and the specific embodiments thereof, it will be apparent to one skilled in the art that modifications and improvements can be made thereto. Accordingly, such modifications or improvements may be made without departing from the spirit of the invention and are intended to be within the scope of the invention as claimed.

Claims (8)

1. The radar echo signal acquisition/playback microsystem circuit chip based on the FPGA is characterized in that a system level packaging mode is adopted, a solder ball array packaging mode is adopted for external packaging, an inner substrate is a multilayer high-density ceramic cavity substrate, the multilayer high-density ceramic cavity substrate is square, a signal acquisition/playback module is arranged on a left side panel of the multilayer high-density ceramic cavity substrate, and a signal preprocessing module is arranged on a right side panel of the multilayer high-density ceramic cavity substrate;

the signal acquisition/playback module is used for acquiring and playing back radar echo signals and comprises four ADC chips and two DAC chips, wherein each two ADC chips are stacked together to form an ADC chip laminated body, the first ADC chip laminated body is positioned at the upper left corner of the substrate, and the second ADC chip laminated body is positioned under the first ADC chip laminated body and aligned with the first ADC chip laminated body; two DAC chips are stacked together to form a DAC chip laminated body, and the DAC chip laminated body is positioned at the lower right corner of the substrate;

during signal acquisition, the signal preprocessing module is used for performing down-conversion processing on data acquired by the ADC chip; during signal playback, the signal preprocessing module is used for performing up-conversion processing on the intermediate frequency radar signal, and transmitting the signal to the DAC through the JESD 204B; the signal preprocessing module comprises an FPGA, an ARM, four DDR3, a power chip and a FLASH, wherein every two DDR3 are stacked together to form a DDR3 laminated body; the two DDR3 laminated bodies are arranged side by side and positioned at the upper right corner of the substrate, and FLASH and a power supply chip are respectively arranged under the two DDR3 laminated bodies; ARM is positioned at the lower right corner of the substrate, and FPGA is positioned between ARM and DAC chip lamination; four DDR3, a power chip and a FLASH are packaged by adopting MCM technology to form a DDR3 package body, a clock module is arranged between the package body and the FPGA, the clock module comprises at least two clock chips, one clock chip is respectively connected with the FPGA and the ARM in a unidirectional manner to provide a system clock and a high-speed interface clock for the FPGA, and one clock chip is respectively connected with the ADC chip and the two DAC chips in a unidirectional manner to provide a working clock for the FPGA and the ARM.

2. The FPGA-based radar return signal acquisition/playback microsystem circuit chip of claim 1, wherein a pad is disposed between adjacent stacked chips in the ADC chip stack, DAC chip stack, DDR3 stack, and is connected to the substrate by a bond wire.

3. The FPGA-based radar return signal acquisition/playback microsystem circuit chip of claim 1, wherein the 4 ADC chips respectively correspond to the direction, distance, speed, and target shape information of the acquired radar signals.

4. The FPGA-based radar echo signal acquisition/playback microsystem circuit chip of claim 1, wherein the DDR3 package adopts a pyramid stack structure, i.e., a first interposer is disposed on a substrate, a power chip and a FLASH are soldered on a right surface of the first interposer, a second interposer is disposed on a left surface of the first interposer, and two DDR3 laminates are soldered on the second interposer.

5. The radar echo signal acquisition/playback microsystem circuit chip based on the FPGA as claimed in claim 2, wherein a silicon adapter plate is arranged between the FPGA and the substrate, the FPGA is flip-chip bonded on the silicon adapter plate, the silicon adapter plate is welded with the substrate, and the FPGA is directly communicated with the substrate through a silicon through hole.

6. The FPGA-based radar echo signal acquisition/playback microsystem circuit chip of claim 1, wherein the clock module comprises an 8MHz passive crystal oscillator, a 50MHz active single-ended crystal oscillator and a 125MHz active differential crystal oscillator, wherein the 8MHz passive crystal oscillator is used for providing an ARM system clock, the 50MHz active single-ended crystal oscillator is used for providing an FPGA system clock, the FPGA is internally provided with a PLL core, frequency multiplication and frequency division of the system clock are realized, the 125MHz active differential crystal oscillator is converted from LVPECL clock level to LVDS clock level by a fan-out chip by using a clock level conversion network, and the clock is used for providing a clock of a high-speed interface of the FPGA.

7. The FPGA-based radar echo signal acquisition/playback microsystem circuit chip of any one of claims 1-6, wherein the ARM selects GD32503 series, and a portion of ARM outgoing IO is used as power-on and load control for the FPGA; ARM is connected with FPGA through GPIO; the FPGA adopts JFM VX690T, and the FPGA is externally hung with FLASH through an SPI bus, so that the FPGA externally leads out user IO, thereby providing convenience for subsequent circuit expansion of the user; the FPGA is externally led out of a high-speed interface and is used for outputting the preprocessed radar acquisition signals.

8. The FPGA-based radar return signal acquisition/playback microsystem circuit chip of claim 1, wherein the ADC selects GM4680 and the DAC uses GMD9154C.