CN113671444A

CN113671444A - Radar echo signal acquisition/playback micro-system circuit chip based on FPGA

Info

Publication number: CN113671444A
Application number: CN202110779151.1A
Authority: CN
Inventors: 肖国尧; 王太伟; 全英汇; 杨立轩; 柯华锋; 吴征程; 孙宗正
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2021-07-09
Filing date: 2021-07-09
Publication date: 2021-11-19
Anticipated expiration: 2041-07-09
Also published as: CN113671444B

Abstract

The invention belongs to the technical field of radar digital signal processing, and particularly discloses a radar echo signal acquisition/playback micro-system circuit chip based on an FPGA (field programmable gate array). A system-in-package is adopted, an internal substrate is a multilayer high-density ceramic cavity substrate, a signal acquisition/playback module is installed on a left panel of the substrate, and a signal preprocessing module is installed on a right panel of the substrate; the signal acquisition/playback module comprises four ADC chips and two DAC chips; when the signal is collected, the signal preprocessing module is used for carrying out down-conversion processing on the data collected by the ADC chip; during signal playback, the signal preprocessing module is used for carrying out up-conversion processing on the intermediate frequency radar signal; the signal preprocessing module comprises an FPGA, an ARM, four DDR3, a power supply chip and a FLASH. The invention realizes the acquisition/playback of radar echo signals of 8-channel channels and the localization of chips thereof, and realizes the miniaturization of a system.

Description

Radar echo signal acquisition/playback micro-system circuit chip based on FPGA

Technical Field

The invention relates to the technical field of electronics, In particular to a radar echo signal acquisition/playback micro-system circuit chip based on FPGA, which uses MST (microsystems technology), MCM (muti-chip module), SiP (System In Package), TSV (Through-silicon Vias) and RDL (Re-Distribution Layer) technologies to carry out the design of the radar signal acquisition or playback micro-system circuit chip and can be used for acquiring and playing back radar signals.

Background

With the development of electronic technology, the hardware implementation of a system is more and more complex, the integration level is higher and higher, and the microelectronic technology also steps into the era of nano-electronics and integrated micro-systems, which puts forward new requirements on system design, and the miniaturization and modularization become inevitable requirements; moreover, most of the existing radar signal acquisition systems adopt foreign chips, so that the requirement of localization cannot be realized, and the existing radar signal acquisition systems are often in a situation of being restricted by people under the current international relationship background.

In the method for realizing the microsystem, the most common method is the SiP technology, the SiP is a system-in-package technology, which is a new technology developed on the basis of SoC (system-on-chip), compared with SoC, the SiP technology has the advantages of short development period and low cost price, and meanwhile has the advantages of excellent performance, small volume and light weight.

Disclosure of Invention

Aiming at the problems In the prior art, the invention aims to provide a radar echo signal acquisition/playback micro-system circuit chip based on FPGA, MST (multiple system technology) and SiP (System In Package) technologies are adopted to realize radar echo signal acquisition/playback of 8-channel channels, the chip localization of multi-channel radar echo signal acquisition/playback is realized, bare chip design is adopted, the volume of the whole machine reaches 40 multiplied by 5mm, and the miniaturization of the system is realized; meanwhile, through packaging and filling, the error between signal lines is smaller, and the reliability of the system is improved.

In order to achieve the purpose, the invention is realized by adopting the following technical scheme.

The radar echo signal acquisition/playback micro-system circuit chip based on the FPGA adopts system-in-package, the external package form adopts solder ball array package, the internal substrate is a multi-layer high-density ceramic cavity substrate, the multi-layer high-density ceramic cavity substrate is square, the left side panel of the multi-layer high-density ceramic cavity substrate is provided with a signal acquisition/playback module, and the right side panel of the multi-layer high-density ceramic cavity substrate is provided with a signal preprocessing module;

the signal acquisition/playback module is used for acquiring and playing back radar echo signals and comprises four ADC chips and two DAC chips, wherein each two ADC chips are stacked together to form an ADC chip laminated body, the first ADC chip laminated body is positioned at the upper left corner of the substrate, the second ADC chip laminated body is positioned under the first ADC chip laminated body, and the two ADC chip laminated bodies are aligned; two DAC chips are stacked together to form a DAC chip laminated body, and the DAC chip laminated body is positioned at the lower right corner of the substrate;

when the signal is collected, the signal preprocessing module is used for carrying out down-conversion processing on the data collected by the ADC chip; during signal playback, the signal preprocessing module is used for performing up-conversion processing on the intermediate frequency radar signal and transmitting the signal to the DAC through the JESD 204B; the signal preprocessing module comprises an FPGA, an ARM, four DDR3, a power chip and a FLASH, wherein every two DDR3 are stacked together to form a DDR3 laminated body; the two DDR3 laminates are arranged side by side and are positioned at the upper right corner of the substrate, and the FLASH and the power supply chip are respectively arranged right below the two DDR3 laminates; the ARM is positioned at the lower right corner of the substrate, and the FPGA is positioned between the ARM and the DAC chip laminated body; the DDR3 packaging structure comprises four DDR3, a power supply chip and a FLASH, the DDR3 packaging structure is formed by packaging through an MCM technology, a clock module is arranged between the packaging structure and the FPGA and comprises at least two clock chips, one clock chip is respectively in one-way connection with the FPGA and the ARM and provides a system clock and a high-speed interface clock for the FPGA and the ARM, and the other clock chip is respectively in one-way connection with the ADC chip and the two DAC chips and provides a working clock for the ADC chip and the two DAC chips.

Furthermore, a gasket is arranged between adjacent stacked chips in the ADC chip stacked body, the DAC chip stacked body and the DDR3 stacked body, and the adjacent stacked chips are connected with the substrate through bonding wires.

Furthermore, 4 ADC chips respectively and correspondingly acquire the direction, distance, speed and target shape information of the radar signal.

Furthermore, the DDR3 package adopts a pyramid stack structure, that is, a first interposer is disposed on a substrate, a power chip and a FLASH are soldered to a right surface of the first interposer, a second interposer is disposed on a left surface of the first interposer, and two DDR3 laminates are soldered to the second interposer.

Further, be provided with the silicon keysets between FPGA and the base plate, the FPGA flip-chip welds on the silicon keysets, welds between silicon keysets and the base plate, and FPGA passes through the through-silicon via and realizes directly communicating with the base plate.

Furthermore, the crystal oscillator of the clock module selects an 8MHz passive crystal oscillator, a 50MHz active single-ended crystal oscillator and a 125MHz active differential crystal oscillator, wherein the 8MHz passive crystal oscillator is used for providing an ARM system clock, the 50MHz active single-ended crystal oscillator is used for providing an FPGA system clock, a PLL core is provided in the FPGA to realize frequency multiplication and frequency division of the system clock, and the 125MHz active differential crystal oscillator converts the LVPECL clock level into an LVDS clock level by a fan-out chip and using a clock level conversion network for providing a clock of a high-speed interface of the FPGA.

Furthermore, the ARM selects a GD32503 series, and one part of IO led out by the ARM is used for power-on and load control of the FPGA; the ARM is connected with the FPGA through a GPIO (general purpose input/output); the FPGA adopts JFM7VX690T, the FPGA is externally connected with FLASH through an SPI bus, and the FPGA leads out user IO to the outside, so that convenience is provided for subsequent circuit expansion of a user; and a high-speed interface is externally led out of the FPGA and used for outputting the preprocessed radar acquisition signals.

Further, the ADC selects GM4680 and the DAC uses GMD 9154C.

Compared with the prior art, the invention has the beneficial effects that:

(1) the microsystem chips are all domestic chips, so that a hundred percent of domestic design is realized, and the problem that a key chip of a radar signal acquisition playback system is restricted by foreign situations is solved;

(2) according to the invention, through the laminated design and layout of the chips, the volume of the system is reduced, the reliability of the system is increased, the DDR3 is packaged by adopting the MCM technology, the capacity and bit width of the DDR3 are fully considered, and the integration level of the system is further increased; in addition, the bare chips are adopted for design, so that the volume of the whole machine reaches 40 multiplied by 5mm, the miniaturization of the system is realized, meanwhile, the error between signal lines can be smaller through further packaging and filling, and the reliability of the system is improved.

(3) The micro-system realizes the acquisition and playback of radar signals of a plurality of channels, integrates AD acquisition and DA playback, realizes the acquisition and playback of radar echo signals with 2GHz analog 3dB input signal bandwidth of 8 channels, transmits the acquired data to a subsequent system through a high-speed interface after preprocessing, can also input digital signals through a high-speed interface, realizes the playback output of the radar signals through a DAC after processing, packages the plate-level functions into the micro-system, and realizes the modularization of the system functions.

(4) According to the invention, the FPGA and the ARM are interconnected through the GPIO, the system control function is completed by the ARM, the system control function comprises power-on control, current monitoring, temperature monitoring and system working mode control, and the system enters a low power consumption mode when not in work or in standby so as to reduce the power consumption and heat generation of the system, increase the stability and reliability of the system and prolong the service life of the system.

Drawings

The invention is described in further detail below with reference to the figures and specific embodiments.

FIG. 1 is a schematic block diagram of a micro-system circuit chip for collecting/replaying radar echo signals based on FPGA according to the present invention;

FIG. 2 is a schematic block diagram of the clock circuit design of the present invention;

FIG. 3 is a schematic view of the microsystem package of the present invention;

FIG. 4 is a diagram of a DDR3 package of the invention;

FIG. 5 is a schematic diagram of the connection between the FPGA and the substrate according to the present invention;

FIG. 6 is a schematic view showing the connection between the laminate and the substrate according to the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to examples, but it will be understood by those skilled in the art that the following examples are only illustrative of the present invention and should not be construed as limiting the scope of the present invention.

With the development of modern integrated circuits, how to improve the integration level of a system and the stability becomes the main problem of circuit system design, under the conditions of more and more complex systems and higher performance requirements, the problem that the structure and the packaging form of the system are required to be improved is solved, and with the improvement of the requirements of the circuit system, various methods for improving the structure of the system and packaging processes are more and more mature.

Example 1

Aiming at the current situation, based on the mst (systems technology) microsystem technology, a microsystem circuit chip based on radar signal acquisition/playback is designed by using an MCM (multi-chip module), a sip (system In package) system-level packaging technology, a TSV (Through-silicon Vias) silicon Through hole technology and an RDL (Re-Distribution Layer) technology, and referring to fig. 1-3, the invention provides a radar echo signal acquisition/playback microsystem circuit chip based on an FPGA, which adopts system-level packaging, adopts a solder ball array packaging mode for external packaging, an internal substrate is a multilayer high-density ceramic cavity substrate, the multilayer high-density ceramic cavity substrate is square, a signal acquisition/playback module is installed on a left side panel of the multilayer high-density ceramic cavity substrate, and a signal preprocessing module is installed on a right side panel of the multilayer high-density ceramic cavity substrate;

In the micro-system circuit chip for radar signal acquisition/playback, the control function is completed by an ARM, the matching of IO quantity and level is fully considered in the aspect of ARM model selection, the ARM selects a GD32503 series, one part of IO led out by the ARM is used for power-on and loading control of an FPGA, and meanwhile, the ARM completes current monitoring, temperature monitoring and the like of a system and is connected with the FPGA through a GPIO.

The core processing chip of the invention adopts the form of FPGA and ARM, so that the system has the advantages of FPGA and ARM in hardware and software, the FPGA adopts JFM7VX690T, is a high-performance FPGA, has field programmable characteristic, has a large number of programmable resources capable of being flexibly configured, comprises programmable modules such as I/O, Block RAM, DSP, MMCM, GTX and the like, is convenient for expansion design, the FPGA mainly completes the preprocessing of radar signals, the FPGA is externally connected with FLASH through an SPI bus, the FLASH is used as the final solidification of a system program, and simultaneously, 64-bit DDR3 is externally connected, in order to further increase the integration level of the system, the capacity and bit width of the DDR3 are fully considered, the DDR3 is packaged by adopting MCM technology, specifically shown in figure 4, the FPGA leads out a large number of user IOs, thereby providing convenience for the flexible application of users when expanding circuits, and simultaneously, the series of FPGAs have a large number of high-speed interfaces, and lead out the high-speed interfaces of the FPGA, the device is used for outputting the preprocessed acquisition signals, can be used for being interconnected with a data processing module, realizes high-speed transmission of data, and is convenient to apply in a system.

Referring to fig. 1, in the aspect of ARM type selection, matching of IO quantity and level is fully considered, an GD32503 series is selected for ARM, an FPGA provides a programmable peripheral circuit for ARM, ARM can provide convenient software processing capability, an ADC chip adopts 4 GM4680, GM4680 adopts a single-core design, 2GHz analog 3dB input signal bandwidth is supported, 1.4 to 2.2VP-P wide-range input range is supported, a DDC frequency conversion path and 1/200Cycle group delay filtering are built in, AD conversion of 8 channels can be realized, and DDC (digital down conversion) output of 8 channels can be realized; the AD chip and the FPGA are connected through the JESD 204B. The DAC chip adopts GMD9154C, GMD9154C is a 4-channel DAC, the bit width is 16 bits, the DAC chip is connected with the FPGA through JESD204B, a clock circuit fully considers the current situation of the current domestic clock chip, a configurable clock chip which is not mature in the current domestic is not used, a chip with a clock fan-out and the clock circuit are adopted to provide a working clock for a micro-system, all core chips required by the system adopt domestic bare chips, and the whole system localization and the miniaturization and modularization of a radar signal acquisition playback system are realized.

In the system, ARM controls to complete electrification and program loading of the FPGA, initialization of the system is completed, a clock network provides a system clock and a reference clock of a high-speed link for the FPGA and also provides a working clock for an ADC (analog to digital converter) and a DAC (digital to analog converter) chip, 4 ADC chips respectively complete collection and digitization of radar signal direction, distance, speed and target shape information, the digital information is transmitted to the FPGA through connection with JESD204B of the FPGA, the FPGA performs DDC (digital down conversion) on the signal, and data is transmitted to a data processing module through a high-speed interface externally led out by the FPGA for further processing of the signal; meanwhile, the playback of the radar echo signal can also be performed by performing DUC (digital up-conversion) on digital information of the direction, distance, speed and target shape of the radar signal at the intermediate frequency, and then transmitting the signal to the DAC through the JESD 204B.

Example 2

In order to realize the localization of a radar signal acquisition playback micro-system, in consideration of the current situation of the current domestic clock chip, a clock chip with fan-out of a clock circuit and a clock network which is designed autonomously provide a system clock for an FPGA, a high-speed interface clock for an ARM, and a working clock for an ADC chip, referring to FIG. 2, in consideration of the clock required by the system, a crystal oscillator selects three types, namely an 8MHz passive crystal oscillator, a 50MHz active single-ended crystal oscillator and a 125MHz active differential crystal oscillator, the 8MHz passive crystal oscillator is used for providing the system clock of the ARM, the 50MHz active single-ended crystal oscillator is used for providing the system clock of the FPGA, the FPGA can realize the frequency multiplication and frequency division of the system clock through an internal self-contained PLL core, the acquired signals are convenient to be preprocessed, the 125MHz active differential crystal oscillator passes through the fan-out chip, a conversion network of the clock level is used, and the LVPECL clock level is converted into the LVDS level, the clock for providing the high-speed interface of the FPGA fully considers the current situation of the current localization signal processing module when selecting the reference clock frequency of the high-speed interface, selects the 125M differential clock as the reference clock of the high-speed interface, and can be used for the signal processing module compatible with the national localization requirement to carry out high-speed data transmission.

Example 3

Referring to fig. 4 and 6, in order to reduce the circuit area occupied by the DDR3, an MCM-C technology, i.e., an MCM using a multilayer ceramic substrate, is used for the DDR3, the MCM technology has high packaging efficiency, low cost and a mature process technology, 4 pieces of DDR3 CSP (chip size package) are assembled on the multilayer ceramic substrate, the substrate uses a low-temperature co-fired ceramic substrate, the in-chip interconnection uses a Wire Bonding process, and the overall size of the MCM package is 20 × 13 mm. In the module package, except the DDR3, a power supply chip for supplying power to the DDR3 and a piece of FLASH are packaged to provide a suitable storage design for an applicable system, so that a module consisting of 4 pieces of DDR3 meets the requirements of the system on the bit width and storage capacity of the DDR3 and further improves the integration level of the system.

In order to meet the requirements of system-in-package on miniaturization and modularization, all chips in the invention are designed in a bare-chip mode, refer to fig. 3, fig. 3 is a schematic diagram of the overall package of a micro system, the micro system adopts a system-in-package technology, and the system-in-package has the obvious advantage that different IC processes can be integrated together, in the invention, the package of a SiP comprises the packaging technologies of CSP, TSV, RDL, MCM and the like, in the design of the micro system, the overall package size is 40 x 5mm, the external package is a BGA package, the internal circuit substrate is a multilayer high-density ceramic cavity substrate, in the schematic diagram of the package, the chips with different sizes adopt a pyramid stack package, the upper layer and the lower layer are connected to the substrate by bonding wires, in the invention, the smaller chips comprising a clock network, various conversion chips and the like adopt a pyramid stack mode, stacked on top of a larger chip. For chips with the same size, a gasket is added between the chips, the height of an upper layer of chip is increased, and a bonding space is reserved for a lower layer of chip, in the invention, an ADC and a DAC both adopt the stacking mode, for DDR3, in consideration of domestic chips, DDR3 is further packaged, and MCM packaging is carried out on DDR3 by adopting the modes of stacking and adding a silicon adapter plate; as for the FPGA connected to the silicon interposer by flip chip bonding and connected to the substrate by TSV (Through-silicon Vias), specifically as shown in fig. 5, the RDL (Re-Distribution Layer) technology is used to lead out the idle IO, so that the original design of the idle IO of the FPGA can be changed, the space between the IO can be increased, and the reliability of the system can be increased; meanwhile, the design of partial IC circuits is replaced, the time of system design is reduced, and most importantly, the circuit has high expandability due to the lead-out of IO. An FPGA and an ARM are arranged at the lower position, an FLAH and an MCM packaged DDR3 are arranged at the upper position, when the system is placed, the routing part which is crucial to system signal transmission is avoided as much as possible, and the interior of the microsystem is interconnected with external pins by adopting bonding wires.

In summary, the invention designs a micro system based on radar signal acquisition/playback by using MCM and SiP packaging technology based on MST technology, the whole system comprises 4 pieces of dual-channel AD chips and 2 pieces of 4-channel DA chips, can realize AD conversion and DA conversion of 8-channel signals, and is packaged with FPGA with a large amount of programmable resources, provides a large amount of user IO, realizes expansion of system functions and preprocessing of signals, in addition, the bare chips of the whole micro system all adopt home devices, realizes the localization of the whole system by one hundred percent, simultaneously fully considers the requirement of the subsequent system in the design, and carries out compatible design aiming at the signal processing module in the current country when leading out user interconnection resources, so that the micro system is more suitable for the use of the home-made radar system, the invention fully utilizes the advantages of the micro system technology and related packaging technology, so that the system has better signal quality, lower loss and higher stability.

In addition, the invention can replay radar echo data and store test data, and can conveniently replay radar image data in field experiments to carry out simulation experiments and reduce the field experiment times of the radar system, thereby greatly reducing the test cost and time. For a radar system, in a test stage, a large number of field experiments are required according to application scenes to verify the functions and the performance of the radar system, and according to the application scenes of the radar system, the experiments are usually high in cost and are not suitable for repeated verification for many times; therefore, after the field experiment, if the radar system needs to be tested for many times, only the collected and stored waveform data of the field experiment needs to be played back for simulation experiment.

Although the present invention has been described in detail in this specification with reference to specific embodiments and illustrative embodiments, it will be apparent to those skilled in the art that modifications and improvements can be made thereto based on the present invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.

Claims

1. The radar echo signal acquisition/playback micro-system circuit chip based on the FPGA is characterized in that system-in-package is adopted, external package is realized by adopting solder ball array package, an internal substrate is a multi-layer high-density ceramic cavity substrate, the multi-layer high-density ceramic cavity substrate is square, a signal acquisition/playback module is installed on the left panel of the multi-layer high-density ceramic cavity substrate, and a signal preprocessing module is installed on the right panel of the multi-layer high-density ceramic cavity substrate;

2. The FPGA-based radar echo signal acquisition/playback micro-system circuit chip of claim 1, wherein a gasket is disposed between adjacent stacked chips in the ADC chip stacked body, the DAC chip stacked body and the DDR3 stacked body, and is connected to the substrate through a bonding wire.

3. The FPGA-based radar echo signal acquisition/playback micro-system circuit chip of claim 1, wherein 4 ADC chips correspond to the direction, distance, speed and target shape information of the acquired radar signal, respectively.

4. The FPGA-based radar echo signal collecting/playback micro-system circuit chip of claim 1, wherein the DDR3 package is a pyramid stack structure, i.e. a first interposer is disposed on a substrate, a power chip and FLASH are soldered to a right surface of the first interposer, a second interposer is disposed on a left surface of the first interposer, and two DDR3 stacked layers are soldered to the second interposer.

5. The FPGA-based radar echo signal acquisition/playback micro-system circuit chip of claim 2, wherein a silicon interposer is disposed between the FPGA and the substrate, the FPGA is flip-chip welded to the silicon interposer, the silicon interposer is welded to the substrate, and the FPGA is directly connected to the substrate through a through-silicon via.

6. The FPGA-based radar echo signal acquisition/playback microsystem circuit chip of claim 1, wherein the crystal oscillator of the clock module is selected from an 8MHz passive crystal oscillator, a 50MHz active single-ended crystal oscillator and a 125MHz active differential crystal oscillator, wherein the 8MHz passive crystal oscillator is used for providing an ARM system clock, the 50MHz active single-ended crystal oscillator is used for providing a FPGA system clock, a PLL core is arranged in the FPGA to realize frequency doubling and frequency division of the system clock, and the 125MHz active differential crystal oscillator is converted into an LVDS clock level through a fan-out chip by using a conversion network of the clock level, so as to provide a clock of a high-speed interface of the FPGA.

7. The FPGA-based radar echo signal acquisition/playback micro-system circuit chip of any one of claims 1-6, wherein the ARM selects GD32503 series, and a part of the ARM lead-out IO is used for power-on and load control of the FPGA; the ARM is connected with the FPGA through a GPIO (general purpose input/output); the FPGA adopts JFM7VX690T, the FPGA is externally connected with FLASH through an SPI bus, and the FPGA leads out user IO to the outside, so that convenience is provided for subsequent circuit expansion of a user; and a high-speed interface is externally led out of the FPGA and used for outputting the preprocessed radar acquisition signals.

8. The FPGA-based radar echo signal acquisition/playback micro-system circuit chip of claim 1, wherein the ADC selects GM4680 and the DAC adopts GMD 9154C.