CN216719090U - Heterogeneous multi-cache high-performance digital signal processor based on double-SiP system - Google Patents

Abstract

The utility model discloses a heterogeneous multi-cache high-performance digital signal processor based on a double-SiP system, which comprises a DSP bare chip, an FPGA bare chip, a plurality of Flash bare chips, a plurality of DDR modules, a plurality of power chips and a plurality of resistance-capacitance devices, wherein all the bare chips, the DDR modules, finished chips and the plurality of resistance-capacitance discrete devices are packaged into a whole through the SiP technology and are packaged on a processor substrate, the devices arranged on the left side and the right side of the processor substrate are externally expanded to the edge of the processor substrate, and heat dissipation covers are of a through structure on the left side and the right side of the processor substrate. The digital signal processor provided by the utility model adopts a general calculation, calculation acceleration and high-speed memory access integrated architecture, has strong processing capability, large storage capacity and rich interface types, effectively saves the area of a signal processing board card, reduces the design difficulty of the board card and improves the overall performance of the board card.

Description

Heterogeneous multi-cache high-performance digital signal processor based on double-SiP system

Technical Field

The utility model relates to the technical field of digital signal processing and control chips, in particular to a heterogeneous multi-cache high-performance digital signal processor based on a double-SiP system.

Background

Signal processing systems of equipment such as radars, detection reconnaissance, electronic warfare, data chains and navigation are mostly constructed by high-performance digital chips such as a super-large-scale Field Programmable Gate Array (FPGA), a processor (DSP or CPU) and a large-capacity memory. With the rapid development of radar equipment toward short, light, small, thin, highly reliable, high-performance, and high-bandwidth directions, the requirements for digital signal processing array, integration, miniaturization, and modularization are more and more urgent. Therefore, it is urgently necessary to adopt a multi-chip module technology, and integrate ICs such as a high-performance DSP, a large-scale FPGA, a large-capacity memory and the like on a high-density multilayer interconnection substrate to form an electronic module with rich functions and reliable performance, so that the complexity of the design of a heterogeneous high-performance processing system is reduced while the high-speed access function and the high-efficiency high-density integrated array integration are realized, and the integrated circuit can be popularized to various general processing platforms.

At present, the SiP digital signal processor based on the FPGA + DSP architecture mainly has the following problems:

such as application number: 202010503853.2, the utility model name is a TMS320C 6748-based signal processing module, wherein the similar SiP chip adopts small-scale DSP or FPGA to realize integrated packaging, and the processing capability is general.

Such as the patent numbers: CN201620441192.4, the utility model name is, a high-performance miniaturized altimeter signal processing and control SiP module, the area of the similar SiP chip is reduced by adopting a stacking framework mode, but the stacking framework needs to adopt a mode of adding a lead bonding or TSV process on the basis of an FC (fiber channel) flip-chip process to realize the interconnection of an upper chip and a substrate, the number of upper and lower interconnection signals is limited, the packaging process is complex, the production cost is high, and the upper and lower stacking structures of a DSP (digital signal processor) and an FPGA (field programmable gate array) put higher requirements on the heat dissipation of a bottom processing device;

such as application number: 201811487484.1, the utility model relates to a high-integration high-performance digital signal processor based on SiP and a packaging structure thereof, which adopts positive and negative double-cavity ceramic packaging to realize the design of the SiP device with consideration of size, process maturity, production cost and interconnection performance, but the mixed design of the reverse cavity solder balls and the device reduces the number of externally-led signals, increases the times of reflow soldering, has strict requirements on the thickness of the back device, and is not beneficial to the design of the integrity of a power supply due to the distribution pattern of the signals around.

At present, similar SiP chips are limited by the size and the influence of a bare chip interface, only one group of DDR caches are arranged in DSPs inside the SiP, DDR memories are not designed in FPGAs, and the memories are all tiled by the bare chips, so that the occupied substrate area is large.

Therefore, a heterogeneous multi-cache high-performance signal processor based on the SiP technology is urgently needed, an integrated architecture integrating general calculation, calculation acceleration and high-speed memory access is adopted, the processing capacity is high, the storage capacity is large, the interface types are rich, the area of a signal processing board card is effectively saved, the board card design difficulty is reduced, and the overall performance of the board card is improved.

SUMMERY OF THE UTILITY MODEL

The utility model provides a heterogeneous multi-cache high-performance digital signal processor based on a double-SiP system, which adopts the following technical scheme:

a digital signal processor with isomerism and multiple caches and high performance based on a double-SiP system comprises a DSP bare chip, an FPGA bare chip, a plurality of Flash bare chips, a plurality of DDR modules, a plurality of power chips and a plurality of resistance-capacitance devices, wherein all the bare chips, the DDR modules, finished chips and the plurality of resistance-capacitance discrete devices are packaged into a whole through the SiP technology and are packaged on a processor base body, the devices arranged on the left side and the right side of the processor base body are externally expanded to the edge of the processor base body, and heat dissipation covers are of a through structure on the left side and the right side of the processor base body;

an EMIF interface of the DSP bare chip is connected with a Flash bare chip and used for storing a bootstrap program, an operating system image and an application program, and related signals are also internally interconnected with the FPGA bare chip and used for configuring power-on starting parameters of the DSP bare chip; the EMIF interface of the DSP bare chip is also led out to the outside of the processor, and a user is multiplexed into a LocalBus bus and a Nand Flash interface;

the BPI loading interface of the FPGA bare chip is connected with the other Flash bare chip and is used for logic program solidification; related signals are only interconnected internally and are not led out of the processor;

DDR interfaces on the DSP bare chip are connected with a part of the plurality of DDR modules one by one and used for general calculation caching, related signals are only interconnected internally and are not led out to the outside of the processor, and discrete resistors or IPD devices are placed at the topological tail ends of the address and control signals to realize terminal matching;

part of HPIO interfaces of the FPGA bare chip are connected with the other part of DDR module one by one and are used for calculating accelerated cache, related signals are only interconnected internally and are not led out to the outside of the processor, and a discrete resistor or an IPD device is placed at the topological tail end of an address and control signal to realize terminal matching;

the power supply chips are connected with the DSP bare chip, the FPGA bare chip and the DDR modules.

The signal processor adopts a general calculation, calculation acceleration and high-speed memory access integrated framework, has strong processing capability, large storage capacity and rich interface types, effectively saves the area of a signal processing board card, reduces the design difficulty of the board card and improves the overall performance of the board card.

The signal processor adopts a double-Sip system, a plurality of DDR modules are small systems, and the whole high-performance digital signal processor is a large system. The DDR bare chip is packaged into a DDR module through a three-dimensional stacking mode and then is connected with each processor through an SMT mode, the stacking mode is not limited to staggered stacking and wire bonding or TSV process stacking and interconnection, on one hand, the signal processor achieves high integration of multiple groups of caches under the condition that the layout areas of processor substrates are the same, on the other hand, the strong dependence of the yield of the digital signal processor on the stacking reliability of a memory is reduced, the packaging production process is simplified, and the product yield is improved.

Preferably, the DDR module is formed by interconnecting a plurality of DDR bare chips with a substrate after a three-dimensional stacking process; the DDR module adopts a three-dimensional stacking mode of staggered stacking and wire bonding or TSV process stacking and interconnection.

Preferably, the DSP bare chip and the FPGA bare chip are interconnected with the processor substrate through an FC (fiber channel) flip-chip process, the DDR modules, the power chips and the resistance-capacitance devices are interconnected with the processor substrate through an SMT (surface mount technology) bonding process, and the Flash bare chips are interconnected with the processor substrate through the FC flip-chip process after converting the Wire Bond lead bonding process through the RDL (remote data link) technology.

Preferably, the Flash die and the DDR module are arranged around the two sides of the DSP die and the FPGA die.

Preferably, the DSP die provides a plurality of high-speed interfaces and a plurality of low-speed interfaces to the outside, where the high-speed interfaces include a 2 × 4SRIO high-speed interface, a 1 × 4PCIe high-speed interface, and a 3 × 1 PCIe high-speed interface

SGMII high-speed interface, 2 × 4SRIO high-speed interface, the speed is more than or equal to 6.25 Gbps; 1 × 4PCIe high-speed interface with speed not less than 5 Gbps; 3 × 1SGMII high-speed interface with a rate of 1.25 Gbps; the low-speed interface comprises a 1-path EMIF interface, a 1-path NAND interface, a path LPC interface, a 2-path SPI interface, a 2-path UART interface, a 2-path I2C interface, a 2-path CAN interface, a 20-path GPIO interface, a 1-path JTAG interface and a 1-path EJTAG interface.

Preferably, the FPGA die provides interfaces to the outside, the interfaces comprise a 4 × 9GTX high-speed interface and a 600-path HPIO interface, and the high-speed interface has the highest speed supporting 12.5 Gbps/lane.

Preferably, the heat dissipation covers on the left side and the right side of the processor base body of the processor are not adhered to the processor base body. All devices of the processor are arranged above a processor substrate, the devices on the left side and the right side are expanded to the edge of the substrate, and the heat dissipation covers on the left side and the right side adopt a through structure, namely, the heat dissipation covers on the left side and the right side and the substrate do not have bonding areas; the area of the substrate is saved.

Compared with the prior art, the utility model has the beneficial effects that:

the digital signal processor integrates ICs such as a high-performance DSP, a large-scale FPGA, a large-capacity memory and the like into the SiP, thereby improving the overall performance of the processor. On one hand, the three-dimensional stacking module replaces the traditional DDR bare chip tiling mode, and high integration of multiple groups of caches is realized under the condition that the layout areas of the substrates are the same; in addition, the DDR module replaces the traditional Wirebond stacking wire bonding or direct interconnection mode of the TSV silicon adapter plate and the digital signal processor substrate with the SMT bonding mode, the dependence of the yield of the digital signal processor on the stacking reliability of the memory is reduced, the packaging production process is simplified, and the product yield is improved.

Drawings

Fig. 1 is a schematic diagram of a system architecture of a heterogeneous multi-cache high-performance digital signal processor based on a dual SiP system according to the present embodiment.

Fig. 2 is a schematic layout diagram of a heterogeneous multi-cache high-performance digital signal processor based on a dual SiP system according to this embodiment.

Fig. 3 is a schematic diagram of the dual system structure of the present embodiment.

Detailed Description

The technical solution of the present invention is described in detail below, but the scope of the present invention is not limited to the embodiments.

In order to make the disclosure of the present invention more comprehensible, the following description is further made in conjunction with fig. 1 to 3 and the detailed description.

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the utility model and are not intended to limit the utility model.

In this embodiment, an example of a heterogeneous, multi-cache high-performance digital signal processor formed by one DSP die 1, one FPGA die 2, three DDR modules, two Flash dies, two power chips, and a plurality of resistance-capacitance devices is described further.

As shown in fig. 1 and 2, the heterogeneous, multi-cache high-performance digital signal processor based on SiP technology of the present embodiment adopts an EHS-FCBGA packaging manner, and has a chip size of 52.5mm by 52.5 mm; the bottom structure of the PSoC chip packaging structure comprises 2704 signal balls, the diameter of the signal balls is 0.6mm, and the pitch distance of the signal balls is 1.0 mm. Specifically, three power supplies and ground of GTX signals, BANK 31-36 signals, BANK 12-13 signals, BANK 16-19 signals and corresponding reference voltages of the FPGA, common IO signals, PCIe signals, SRIO signals, SGMII signals and EMIF signals of the DSP, and VDD0V9, VDD1V0, VDD1V8 and VDD1V5 are distributed in the peripheral area.

As shown in fig. 2, in the embodiment, two Flash die are defined as a first Flash die 3 and a second Flash die 4, respectively; the three DDR3 modules are divided into a first DDR3 module 5, a second DDR3 module 6 and a third DDR3 module 7; the two power chips are respectively a first power chip 8 and a second power chip 9.

As shown in fig. 1 and 2, in this embodiment, based on a DSP die 1, an FPGA die 2, three DDR modules, two Flash die, two power chips, and a plurality of resistance-capacitance devices in a heterogeneous, multi-cache high-performance digital signal processor of a dual SiP system, all the die, the finished chip, and the plurality of resistance-capacitance discrete devices are packaged into a whole by a SiP technology, and the inside is integrated into a SiP chip by way of substrate interconnection or lead-out.

As shown in fig. 2, in the present embodiment, three DDR3 modules and two Flash die in the high performance digital signal processor are symmetrically arranged around the DSP die 1 and the FPGA die 2, and the three DDR3 module finished products are arranged around the processor substrate at positions close to the signal PAD positions corresponding to the DSP die 1 and the FPGA die 2.

As shown in fig. 2, the first DDR3 module 5 of the three DDR3 modules is distributed on the left side of the DSP die 1, the second DDR3 module 6 is distributed on the right side of the DSP die 1, and the third DDR3 module 7 is distributed on the right side of the FPGA die 2; the first power supply chips 8 in the two power supply chips are distributed in the lower area of the DDR module 5, and the second power supply chips 9 are distributed in the lower area of the DDR module 6; the first Flash bare chip 3 in the two Flash bare chips is distributed in the lower area of the power supply chip 8, and the second Flash bare chip 4 is distributed in the lower area of the first Flash bare chip 3; the arrangement areas of the DDR bare chips on the two sides are extended outward for a certain distance to the two sides of the substrate 11.

In the embodiment, the high-performance digital signal processor and the internal integrated circuit bare chip, namely, the DSP bare chip and the FPGA bare chip are both FC flip-chip welding processes based on the chip salient points; the Flash bare chip needs to be subjected to substrate design and packaging after converting a Wire Bond routing structure into an FC flip chip structure through RDL. The FC flip-chip bonding process mentioned in this embodiment is known to those skilled in the art.

As shown in fig. 1, in the present embodiment, the DSP die 1 itself is subjected to the FC soldering process, and the model of the DSP die 1 is preferably HRDSP2040 die sold by the fourteenth research institute of china electronic technology corporation, and the DSP die includes 4 DSP cores therein and has the highest dominant frequency of 800 MHz.

As shown in fig. 1, in the present embodiment, the FPGA die 2 itself is subjected to the FC soldering process, and the FPGA die 2 is preferably a model JFM7VX690T36 die sold by shanghai compound denier microelectronics group ltd.

As shown in fig. 1, in the present embodiment, the two Flash die themselves are subjected to a WireBond soldering process, and the first Flash die 3 and the second Flash die 4 are both preferably model JFM29GL256 die sold by shanghai repanda microelectronics corporation ltd, with a storage capacity of 256Mb, an operating voltage of 3.3V, and an IO voltage of 1.8V.

As shown in fig. 1, in the present embodiment, the three DDR3 modules are divided into a first DDR3 module 5, a second DDR3 module 6 and a third DDR3 module 7, and the three DDR3 modules themselves are subjected to the SMT soldering process; the first DDR3 module 5, the second DDR3 module 6, and the third DDR3 module 7 are preferably a module with a data bit width of 64 bits and a storage capacity of 2GB, which is formed by three-dimensionally stacking domestic DDR3 bare chips with a data bit width of 16 bits and a storage capacity of 512MB and packaging the bare chips.

As shown in fig. 2, three DDR3 modules are interconnected with a substrate after a plurality of DDR3 bare chips are subjected to a three-dimensional stacking process; in the embodiment, the three-dimensional stacking manner of the DDR3 module is preferably staggered stacked wire or TSV process stacked interconnection, but is not limited to staggered stacked wire or TSV process stacked interconnection.

As shown in fig. 1, in this embodiment, the EMIF interface of the DSP die 1 is connected to the first Flash die 3, and the parallel data bit is 16 bits wide and is used for boot program, operating system image, and application program storage.

As shown in fig. 1, in this embodiment, an EMIF interface of a DSP die 1 is interconnected with an FPGA die 2 for configuring power-on startup parameters of a DSP, and interconnection signals of the EMIF interface of the DSP die 1 and the FPGA die 2 in this embodiment are located in BANK14 and BANK15 of the FPGA die 2, and the BANK voltage is 1.8V.

As shown in fig. 1, a BPI loading interface of the FPGA die 2 is connected to the second Flash die 4, the parallel data bit is 16 bits wide, and is used for logic program solidification, and related signals are only interconnected internally and are not led out to the outside of the processor; in the embodiment, the loading signals of the FPGA bare chip 2 are positioned in the BANK14 and BANK15 of the FPGA bare chip 2, and the BANK voltage is 1.8V.

As shown in fig. 1, the DDR interface of the DSP die 1 is connected to the first DDR3 module 5 and the second DDR3 module 6 for general purpose computing cache, the relevant signals are only interconnected internally and are not led out to the outside of the processor, and a discrete resistor or an IPD device is placed at the end of the topology of the address and control signals to implement terminal matching.

As shown in fig. 1, a part of HPIO interfaces of the FPGA bare chip 2 are connected to the third DDR3 module 7 for calculating an accelerated cache, related signals are only interconnected internally and are not led out to the outside of the processor, and a discrete resistor or an IPD device is placed at the topological end of the address and control signals to implement terminal matching; in the embodiment, the interconnection signals of the FPGA bare chip 2 and the DDR module 7 are positioned at BANK37, BANK38 and BANK39 of the FPGA bare chip 2, and the BANK voltage is 1.5V.

As shown in fig. 1, the first power chip 8 is connected to the DSP die 1 and the first DDR3 module 5, and the first power chip 8 generates VTT and VREF required by the DSP DDR3 channel 1 and the DDR3 module inside the high performance digital signal processor.

As shown in fig. 1, the second power chip 9 is connected to the DSP die 1, the FPGA die 2, the second DDR3 module 6, and the third DDR3 module 7, and the second power chip 9 generates VTT and VREF required by the DSP DDR3 channel 2, the FPGA and DDR3 interconnected BANK, and the DDR3 module inside the high performance digital signal processor.

As shown in fig. 1, the DSP die 1 provides rich high-speed interfaces to the outside, including a 2 × 4SRIO high-speed interface, a 1 × 4PCIe high-speed interface, and a 3 × 1SGMII high-speed interface; the 2 × 4SRIO high-speed interface has the speed of more than or equal to 6.25Gbps, the 1 × 4PCIe high-speed interface has the speed of more than or equal to 5Gbps, the 3 × 1SGMII high-speed interface has the speed of 1.25 Gbps.

As shown in fig. 1, the DSP die 1 provides rich low-speed interfaces to the outside, including 1-way EMIF interface, 1-way NAND interface, one-way LPC interface, 2-way SPI interface, 2-way UART interface, 2-way I2C interface, 2-way CAN interface, 20-way GPIO interface, 1-way JTAG interface, and 1-way EJTAG interface.

As shown in fig. 1, the FPGA die 2 provides rich high-speed interfaces to the outside, including a 4 × 9GTX high-speed interface, with a maximum speed of 12.5 Gbps/lane.

As shown in FIG. 1, the FPGA die 2 provides rich HPIO interfaces to the outside, including 600 HPIO interfaces, and the HPIO led out from the FPGA die 2 in this embodiment is located in BANK 31-36, BANK 12-13, BANK 16-19 of the FPGA die 2.

As shown in fig. 1, the voltage varieties of partial devices are merged inside the processor, the VCCINT and VCCBRAM voltages of the FPGA die are merged into 1.0V inside the processor, the VCCIO voltage of the DSP die 1, the VCCAUX voltage of the FPGA die and the BANK0 reference voltage corresponding to the configuration signal, the BANK13 and BANK14 reference voltages corresponding to the loading signal, the IO voltage of the first Flash die 3 and the second Flash die 4 are merged into 1.8V inside the processor, the DDR VDDQ voltage of the DSP die 1, the VDD and VDDQ voltages of the first DDR3 module 5, the second DDR3 module 6 and the third DDR3 module 7, the reference voltage of the interconnection BANK of the FPGA 2 and DDR3 modules, the VLDOIN voltage of the power supply chip are merged into 1.5V inside the processor, the DDR VDDQ voltage of the DSP die 1, the first DDR3 module 5, the second DDR3 module 6 and the third DDR 387 module, and the DDR3 voltage of the FPGA die 28, and the DDR3 voltage of the FPGA die 26 and the DDR 387 of the first DDR 388, The VLDOIN voltage of the power supply chip is combined into 1.5V voltage in the processor, and the VCC voltage of the Flash and the VIN voltage of the power supply chip are combined into 3.3V voltage in the processor.

In this embodiment, the decoupling capacitors of the DSP die 1 and the FPGA die 2 select the low-ESL 8-pin capacitor and the flip-chip capacitor according to the power integrity simulation result.

As shown in fig. 2, the high performance digital signal processor of this embodiment is integrally packaged in a package substrate, the processor substrate adopts a single-cavity structure, all devices are disposed above the processor substrate, the left and right devices are extended to the edge of the substrate, and the heat dissipation covers adopt a through structure on the left and right sides, that is, the processor is located in the non-bonding region between the left and right heat dissipation covers of the processor substrate and the processor substrate; saving the area of the processor substrate. The heat dissipation covers of the processor are positioned at the left side and the right side of the processor base body and have no bonding area with the processor base body, namely, the bonding area of the heat dissipation covers is only left at the upper part and the lower part of the processor base plate, and the areas are not left at the left side and the right side, in other words, the resistance capacitance, the bare chip, the device and the like can be seen from the left side and the right side to the inside.

The high-performance digital signal processor of the embodiment adopts a general calculation, calculation acceleration and high-speed memory access integrated architecture, has strong processing capacity, large storage capacity and rich interface types, effectively saves the area of a signal processing board card, reduces the design difficulty of the board card and improves the overall performance of the board card.

The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the protection scope of the present invention.

Claims (7)

1. A heterogeneous, multi-cache high performance digital signal processor based on a dual SiP system, comprising: the chip comprises a DSP bare chip, an FPGA bare chip, a plurality of Flash bare chips, a plurality of DDR modules, a plurality of power chips and a plurality of resistance-capacitance discrete devices, wherein all the bare chips, the DDR modules, finished chips and the resistance-capacitance discrete devices are packaged into a whole through the SiP technology and are packaged on a processor base body, the devices arranged on the left side and the right side of the processor base body are extended to the edge of the processor base body, and the heat dissipation covers are of a through structure on the left side and the right side of the processor base body;

an EMIF interface of the DSP bare chip is connected with a Flash bare chip and used for storing a bootstrap program, an operating system image and an application program, and related signals are also internally interconnected with the FPGA bare chip and used for configuring power-on starting parameters of the DSP bare chip; the EMIF interface of the DSP bare chip is also led out to the outside of the processor, and a user is multiplexed into a LocalBus bus and a Nand Flash interface;

the BPI loading interface of the FPGA bare chip is connected with the other Flash bare chip and is used for logic program solidification; related signals are only interconnected internally and are not led out of the processor;

DDR interfaces on the DSP bare chip are connected with a part of the plurality of DDR modules one by one and used for general calculation caching, related signals are only interconnected internally and are not led out to the outside of the processor, and discrete resistors or IPD devices are placed at the topological tail ends of the address and control signals to realize terminal matching;

part of HPIO interfaces of the FPGA bare chip are connected with the other part of DDR module one by one and are used for calculating accelerated cache, related signals are only interconnected internally and are not led out to the outside of the processor, and a discrete resistor or an IPD device is placed at the topological tail end of an address and control signal to realize terminal matching;

the power supply chips are connected with the DSP bare chip, the FPGA bare chip and the DDR modules.

2. The dual-SiP system-based heterogeneous, multi-cache high-performance digital signal processor of claim 1, wherein: the DDR module is formed by interconnecting a plurality of DDR bare cores with a substrate after a three-dimensional stacking process; the DDR module adopts a three-dimensional stacking mode of staggered stacking and wire bonding or TSV process stacking and interconnection.

3. The dual-SiP system-based heterogeneous, multi-cache high-performance digital signal processor of claim 1, wherein: the DSP bare chip and the FPGA bare chip are mutually connected with the processor substrate through an FC (fiber channel) flip-chip process, the DDR modules, the power chips and the resistance-capacitance devices are mutually connected with the processor substrate through an SMT (surface mount technology) bonding process, and the Flash bare chips are mutually connected with the processor substrate through the FC flip-chip process after the Wire Bond lead bonding process is converted through an RDL (remote description) technology.

4. The dual-SiP system-based heterogeneous, multi-cache high-performance digital signal processor of claim 1, wherein: the Flash bare chips and the DDR modules are arranged around the two sides of the DSP bare chip and the FPGA bare chip.

5. The dual-SiP system-based heterogeneous, multi-cache high-performance digital signal processor of claim 1, wherein: the DSP bare chip provides a plurality of high-speed interfaces and a plurality of low-speed interfaces to the outside, the high-speed interfaces comprise a 2 x 4SRIO high-speed interface, a 1 x 4PCIe high-speed interface and a 3 x 1SGMII high-speed interface, the 2 x 4SRIO high-speed interface has the speed of more than or equal to 6.25 Gbps; 1 × 4PCIe high-speed interface with speed not less than 5 Gbps; 3 × 1SGMII high-speed interface with a rate of 1.25 Gbps; the low-speed interface comprises a 1-path EMIF interface, a 1-path NAND interface, a path LPC interface, a 2-path SPI interface, a 2-path UART interface, a 2-path I2C interface, a 2-path CAN interface, a 20-path GPIO interface, a 1-path JTAG interface and a 1-path EJTAG interface.

6. The dual-SiP system-based heterogeneous, multi-cache high-performance digital signal processor of claim 1, wherein: the FPGA die provides interfaces for the outside, and the interfaces comprise a 4 x 9GTX high-speed interface and a 600-path HPIO interface, and the high-speed interface has the highest speed supporting 12.5 Gbps/lane.

7. The dual-SiP system-based heterogeneous, multi-cache high-performance digital signal processor of claim 1, wherein: the processor is positioned in the bonding-free area between the left and right radiating covers of the processor base body and the processor base body.

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