CN114446924A - Semiconductor structure and chip packaging method - Google Patents

Semiconductor structure and chip packaging method Download PDF

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Publication number
CN114446924A
CN114446924A CN202210085984.2A CN202210085984A CN114446924A CN 114446924 A CN114446924 A CN 114446924A CN 202210085984 A CN202210085984 A CN 202210085984A CN 114446924 A CN114446924 A CN 114446924A
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chip
pins
packaging
semiconductor structure
substrate
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CN202210085984.2A
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舒伟峰
陈清华
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Hangzhou Clounix Technology Ltd
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Hangzhou Clounix Technology Ltd
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Priority to CN202210085984.2A priority Critical patent/CN114446924A/en
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

The invention provides a semiconductor structure and a chip packaging method, wherein the semiconductor structure comprises a substrate, a first chip and a second chip which are arranged on the substrate in parallel; the first chip and the second chip are directly connected with each other through a wire bonding process; and for the pins needing high-speed signals between the first chip and the second chip, the pins are configured to be arranged oppositely, and the pins are connected through parallel routing. The embodiment has the advantages of shorter wiring, small occupied space, better performance of high-speed signals, little change of cost and even lower performance by the wire bonding technology from the chip to the chip. Compared with 2.5D and 3D packaging, the cost of the embodiment is much lower, the requirement on manufacturing equipment is not high, and the method is very suitable for mass production.

Description

Semiconductor structure and chip packaging method
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a semiconductor structure and a chip packaging method.
Background
With the development of semiconductor technology, the size of chips is larger and larger, and the chips integrated on the package are more and more complex. When packaged, it is often necessary to integrate a plurality of different chips, such as memory + logic chips, optoelectronic + electronic components, etc., by packaging, 3D stacking, etc., so as to achieve smaller size and power consumption.
In some applications, for a chip with fewer input/output pins, if two chips need to be interconnected, the general method is:
1. wire bonding is used and then connected through the package Substrate (Substrate).
The wire bonding technology is the dominant technology of the traditional packaging at present, and has the advantages of low cost, high reliability, huge yield and the like. The principle of the method is that a thin metal wire is used, and heat, pressure and ultrasonic energy are used for enabling a metal lead wire to be tightly welded with a substrate bonding pad, so that the electrical interconnection between chips and a substrate and the information intercommunication between the chips are realized.
The connection is as shown in fig. 1, and the disadvantage of this method is that the wiring is long, the occupied space is large, and the performance is poor. Especially for many high performance chips, the requirement of high speed IO cannot be satisfied.
2. Flip chip technology is used and then connected through a package Substrate (Substrate).
The connection is as shown in fig. 2, the flip chip technology can meet the requirement of high-speed IO to a certain extent, the occupied space is small, the wiring is long, and the cost is high.
3. The two chips were connected using silicon interposer using 2.5D packaging technology.
As shown in fig. 3, the 2.5D package mainly arranges the chips in parallel on a Silicon Interposer (Silicon Interposer), and connects the chips through Micro bumps (Micro bumps), so that the metal wires in the Silicon Interposer can connect the electronic signals of different chips; then, the lower metal bumps (Solder Bump) are connected Through Silicon Vias (TSV), and the external metal balls are connected through the wire carrier plate, so that the chip, the chip and the package substrate are more closely interconnected.
The 2.5D packaging has the advantages of shorter wiring, smaller occupied space and higher high-speed signal performance. The disadvantage is the high cost.
4. Two chips are stacked up and down using a 3D packaging technique and then connected by TSVs.
The packaging technology has the advantages of shortest routing, minimum occupied space and highest high-speed signal performance. The disadvantage is that the cost is very high.
Several of the above approaches attempt to interconnect two or more chips, thereby reducing overall size and power consumption, and providing better high-speed performance, which can reduce overall system cost. There are also some methods that mix the above approaches, but in general, either the improvement is not enough or the complexity and cost of the system are greatly increased, and thus the use requirement cannot be met.
Disclosure of Invention
Accordingly, the present invention is directed to a semiconductor structure and a chip packaging method for improving the above-mentioned problems.
The embodiment of the invention provides a semiconductor structure, which comprises a substrate, a first chip and a second chip, wherein the first chip and the second chip are arranged on the substrate in parallel; the first chip and the second chip are directly interconnected through a wire bonding process; and for the pins needing high-speed signals between the first chip and the second chip, the pins are configured to be arranged oppositely, and the pins are connected through parallel routing.
Preferably, the pitch of the pins of the first chip or the second chip is equal.
Preferably, the high speed signal lines connecting opposing pins are parallel and equally spaced.
Preferably, the resistance between the oppositely configured pins is the characteristic impedance required for a high speed signal line.
Preferably, the resistance between the oppositely disposed pins is 100 ohms.
Preferably, the first chip is packaged onto the substrate by flip chip technology, 2.5D or 3D packaging technology.
Preferably, the first chip is packaged onto the substrate by flip chip technology, 2.5D or 3D packaging technology.
The embodiment of the invention also provides a chip packaging method, which comprises the following steps:
packaging a first chip on a substrate;
packaging a second chip on the substrate;
forming interconnection between the first chip and the second chip directly through a wire bonding process; and for the pins needing high-speed signals to be routed between the first chip and the second chip, the pins are configured to be arranged oppositely, and are connected through parallel routing.
Preferably, the pitches of the pins of the first chip or the second chip are equal; the high speed signal lines connected to the opposite pins are parallel and equally spaced.
Preferably, the resistance between the oppositely configured pins is the characteristic impedance required for a high speed signal line.
In summary, in the present embodiment, through the wire bonding technology from the chip to the chip, compared with the conventional wire bonding technology from the chip to the package as shown in fig. 1, the present embodiment has a shorter trace, occupies a smaller space, has a better performance of high-speed signals, does not change much in cost, and can even be made lower. Compared with 2.5D and 3D packaging, the cost of the embodiment is much lower, the requirement on manufacturing equipment is not high, and the method is very suitable for mass production.
In addition, the present embodiment can be mixed with flip chip 2.5D/3D packaging technology, and the packaging selection is more flexible.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a prior art design scheme for implementing chip interconnection through a wire bonding process.
Fig. 2 is a prior art design scheme for implementing chip interconnection by flip chip technology.
Fig. 3 is a prior art design scheme for implementing chip interconnection by 2.5D packaging technology.
Fig. 4 is a prior art design scheme for realizing chip interconnection by 3D packaging technology.
Fig. 5 is a schematic diagram of a semiconductor structure provided in this embodiment.
Fig. 6 is a top view of a semiconductor structure provided in this embodiment.
Fig. 7 is a schematic diagram of a connection of high-speed signals of the semiconductor structure provided in this embodiment.
Fig. 8 is another connection diagram of high-speed signals of the semiconductor structure provided in this embodiment.
Fig. 9 is a schematic diagram of a connection of the semiconductor structure provided in this embodiment with a hybrid flip-chip technology.
Fig. 10 is another connection diagram of the semiconductor structure provided in this embodiment mixed with the flip chip technology.
Fig. 11 is a connection diagram of the semiconductor structure provided in this embodiment and a 2.5D/3D packaging technology.
Fig. 12 is a process flow diagram of a chip packaging method according to a second embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
The invention is described in further detail below with reference to the following detailed description and accompanying drawings:
referring to fig. 5, a semiconductor structure according to a first embodiment of the present invention includes a substrate 10, and a first chip 20 and a second chip 30 disposed on the substrate 10 in parallel; wherein the first chip 20 and the second chip 30 are directly interconnected through a wire bonding process; moreover, the pins that need to carry high-speed signals between the first chip 20 and the second chip 30 are configured to be arranged oppositely, and are connected by parallel wires.
In the present embodiment, the substrate 10 may be, for example, a PCB board, which functions to support the semiconductor structure and to realize specific electrical connections.
In the present embodiment, the first chip 20 and the second chip 30 may be chips with a small number of pins, such as an optical module, a silicon optical chip, and a DSP chip, and other chips may be selected.
In addition, since it should be noted that in the embodiment of the present invention, the substrate 10 may further include more chips, the present invention is not limited in particular.
Compared with the traditional chip-to-package wire bonding technology shown in fig. 1, the wire bonding technology between the chip and the chip in the embodiment has the advantages of shorter wiring, small occupied space, better performance of high-speed signals, little change of cost and even lower possibility. Compared with 2.5D and 3D packaging, the cost of the embodiment is much lower, the requirement on manufacturing equipment is not high, and the method is very suitable for mass production.
Of course, for some high speed signals, especially >5Gbps high speed Serdes signals, the latter up to 50GHz, 100GHz analog signals, some special designs are required if this way of chip-to-chip wire bonding is to be employed.
Specifically, as shown in fig. 6 and 7, it can be seen that for high-speed interconnection between chips, differential signals need to be routed, wherein the middle high-speed signal lines are routed in parallel, which is more favorable for impedance control.
In particular, in the present embodiment, the pitch between the pins of the chip and the pitch between the high-speed signal lines are equally spaced, and the impedance needs to be controlled to the characteristic impedance required for the high-speed signal lines, for example, to 100 ohms.
In this embodiment, the high-speed signal can be set according to actual needs, and as shown in fig. 7, in one implementation, the signals of the four high-speed signal lines are distributed as follows: power or ground, signal (P), signal (N), power or ground. In another implementation, as shown in fig. 8, there may be more high-speed signal lines, which is specifically determined according to actual needs and is not described herein again.
It should be noted that, in this embodiment, the packaging process of the first chip 20 and the second chip 30 is not limited, and wire bonding, a flip chip technology, a 2.5D or 3D packaging technology may be adopted, and the present invention is not limited in particular.
Thus, the present embodiments may also enable hybrids with other packaging technologies.
As shown in fig. 9 and 10, fig. 9 and 10 show a design of the present embodiment mixed with the flip chip technology, and fig. 11 shows a design of the present embodiment mixed with the.5D/3D packaging technology.
In summary, in the present embodiment, through the wire bonding technology from the chip to the chip, compared with the conventional wire bonding technology from the chip to the package as shown in fig. 1, the present embodiment has a shorter trace, occupies a smaller space, has a better performance of high-speed signals, does not change much in cost, and can even be made lower. Compared with 2.5D and 3D packaging, the cost of the embodiment is much lower, the requirement on manufacturing equipment is not high, and the method is very suitable for mass production.
In addition, the present embodiment can be mixed with flip chip 2.5D/3D packaging technology, and the packaging selection is more flexible.
Referring to fig. 12, a second embodiment of the present invention further provides a chip packaging method, which includes:
s201, packaging a first chip on a substrate;
s202, packaging a second chip on the substrate;
s203, directly forming interconnection between the first chip and the second chip through a wire bonding process; and for the pins needing high-speed signals to be routed between the first chip and the second chip, the pins are configured to be arranged oppositely, and are connected through parallel routing.
Preferably, the pitches of the pins of the first chip or the second chip are equal; the high speed signal lines connected to the opposite pins are parallel and equally spaced.
Preferably, the resistance between the oppositely configured pins is the characteristic impedance required for a high speed signal line.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A semiconductor structure is characterized by comprising a substrate, a first chip and a second chip which are arranged on the substrate in parallel; the first chip and the second chip are directly interconnected through a wire bonding process; and for the pins needing high-speed signals between the first chip and the second chip, the pins are configured to be arranged oppositely, and the pins are connected through parallel routing.
2. The semiconductor structure of claim 1, wherein the pins of the first chip or the second chip are equally spaced.
3. The semiconductor structure of claim 1, wherein the high speed signal lines connecting opposing pins are parallel and equally spaced.
4. The semiconductor structure of claim 3, wherein the resistance between the oppositely disposed pins is a characteristic impedance required for the high speed signal line.
5. The semiconductor structure of claim 3, wherein the resistance between the oppositely disposed pins is 100 ohms.
6. The semiconductor structure of claim 1, wherein the first chip is packaged onto the substrate by flip chip technology, 2.5D or 3D packaging technology.
7. The semiconductor structure of claim 1, wherein the first chip is packaged onto the substrate by flip chip technology, 2.5D or 3D packaging technology.
8. A method of chip packaging, comprising:
packaging a first chip on a substrate;
packaging a second chip on the substrate;
forming interconnection between the first chip and the second chip directly through a wire bonding process; and for the pins needing high-speed signals to be routed between the first chip and the second chip, the pins are configured to be arranged oppositely, and are connected through parallel routing.
9. The chip packaging method according to claim 8, wherein the pitches of the pins of the first chip or the second chip are equal; the high speed signal lines connected to the opposite pins are parallel and equally spaced.
10. The chip packaging method according to claim 9, wherein a resistance between the pins arranged oppositely is a characteristic impedance required for the high-speed signal line.
CN202210085984.2A 2022-01-25 2022-01-25 Semiconductor structure and chip packaging method Pending CN114446924A (en)

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