CN219297149U - Three-dimensional packaging structure based on silicon-based microsystem and silicon-based micro-assembly device - Google Patents
Three-dimensional packaging structure based on silicon-based microsystem and silicon-based micro-assembly device Download PDFInfo
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- CN219297149U CN219297149U CN202223357456.2U CN202223357456U CN219297149U CN 219297149 U CN219297149 U CN 219297149U CN 202223357456 U CN202223357456 U CN 202223357456U CN 219297149 U CN219297149 U CN 219297149U
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Abstract
The utility model provides a three-dimensional packaging structure based on a silicon-based microsystem, which belongs to the technical field of silicon-based microsystem micro-assembly, and comprises a first layer of silicon substrate and a second layer of silicon substrate, wherein a functional element bonding area is arranged on the first layer of silicon substrate; the second layer of silicon substrate is arranged on the first layer of silicon substrate, a first window for avoiding the functional element is arranged on the second layer of silicon substrate, and the size of the first window is larger than that of the bonding area of the functional element; the first layer silicon substrate or/and the second layer silicon substrate is/are provided with a spacer ring, and the spacer ring surrounds the periphery of the first window and is connected between the first layer silicon substrate and the second layer silicon substrate. According to the utility model, the isolating ring is arranged around the chip, and when the chip is coated with the conductive adhesive for bonding, the isolating ring can play a role in blocking overflow of the conductive adhesive, so that the conductive adhesive can only be arranged in the isolating ring, and the problem of short circuit of a packaged device caused by overflow of the conductive adhesive and connection of surrounding signal holes or circuit patterns is avoided.
Description
Technical Field
The utility model belongs to the technical field of silicon-based micro-system micro-assembly, and particularly relates to a three-dimensional packaging structure based on a silicon-based micro-system and a silicon-based micro-assembly device.
Background
Currently, the size of the traditional TR module is close to that of a miniaturized ceiling due to the volume restriction of the functional element, and the development of a three-dimensional integration technology is an important direction. Three-dimensional integration oriented to silicon base is an important branch in three-dimensional integration technology.
The three-dimensional integration of the silicon substrate refers to stacking the silicon substrate and the functional elements in the Z-axis direction, and utilizing TSV silicon through holes to perform signal transmission, so that the transmission path is shortened, and the purposes of small volume and high integration are achieved.
The functional element is usually fixed above the silicon substrate in a bonding manner by conductive adhesive, and the operation process requires the conductive adhesive to slightly overflow the periphery of the functional element so as to prevent the insufficient adhesive amount and facilitate the inspection.
However, with the increase of integration level and complexity, the wiring density in the silicon substrate is greatly increased, and a plurality of signal holes are often arranged around the functional element cavity, so that the conductive adhesive is easy to overflow into gaps between silicon chips, and the signal holes are short-circuited with the ground.
There are two conventional approaches to solving this problem: firstly, the operation process is strictly controlled, namely, the glue amount and the force for placing the functional elements are controlled, which puts extremely high requirements on the process, on the premise of ensuring the reliability, the glue amount must be as little as possible and the smearing is very uniform, operators must carefully operate, and if overflow short circuit occurs, reworking is necessary, so that the production efficiency is greatly reduced. In addition, the signal holes are far away from the cavities of the functional elements by avoiding the design, but valuable space is wasted and the integration level of the microsystem is reduced.
In the ideal case of silicon-based packaging, the conductive paste should only be present under the functional elements. The actual operation flow is to coat conductive adhesive firstly, then put the functional element, in the course of putting the functional element, the conductive adhesive will be extruded to generate deformation, and overflow to the surrounding gaps. If the pectin quantity is proper, the extrusion force is proper, and the conductive adhesive cannot be extruded into the gap between the two silicon substrates. However, in order to make the conductive adhesive around overflow uniformly and meet the reliability requirement, a little more conductive adhesive is generally coated. At this time, the conductive paste is easily diffused into the gap between the two silicon substrates, and the conductive paste contacts the signal line hole, resulting in a nearby signal Kong Duanlu.
Disclosure of Invention
The embodiment of the utility model provides a three-dimensional packaging structure based on a silicon-based microsystem and a silicon-based micro-assembly device, and aims to solve the problem that a packaging circuit is short-circuited due to short circuit between a conductive adhesive and a nearby signal hole caused by overflow when functional elements are bonded.
In order to achieve the above object, the present utility model adopts the following technical scheme: provided is a three-dimensional packaging structure based on a silicon-based microsystem, comprising:
a first layer of silicon substrate, wherein a functional element bonding area is arranged on the first layer of silicon substrate; and
the second layer of silicon substrate is arranged on the first layer of silicon substrate, a first window for avoiding the functional element is arranged on the second layer of silicon substrate, and the size of the first window is larger than that of the functional element bonding area;
the first layer silicon substrate or/and the second layer silicon substrate is/are provided with an isolating ring, and the isolating ring surrounds the periphery of the first window and is connected between the first layer silicon substrate and the second layer silicon substrate.
In a first aspect, in one possible implementation manner, the width W of the isolation ring is 18-22um.
In a first aspect, in one possible implementation, the spacer ring has a height H of 4-6um.
In a first aspect, in a possible implementation manner, a shortest distance L between an inner side of the spacer ring and a side wall of the first window is 25-35um.
In a possible implementation manner of the first aspect, a lower micro-bump is disposed on an upper surface of the first layer of silicon substrate and outside the isolation ring, and an upper micro-bump opposite to the lower micro-bump is disposed on a lower surface of the second layer of silicon substrate.
In a first aspect, in a possible implementation manner, a shortest distance L1 from the spacer ring to the lower micro-bump or the upper micro-bump is 25-35um.
In a first aspect, in a possible implementation manner, the lower micro-bump and the upper micro-bump penetrate the first layer silicon substrate and the second layer silicon substrate up and down to form a metallized column for transmitting signals.
In a possible implementation manner of the first aspect, the semiconductor device further includes a third layer of silicon substrate and a packaging cover plate packaged on the third layer of silicon substrate, wherein a second window coaxial with the first window is arranged on the third layer of silicon substrate, and the size of the second window is larger than that of the first window.
In a possible implementation manner of the first aspect, the method further includes bonding a chip to the functional element bonding region, where the chip is bonded to the second layer silicon substrate.
In a second aspect, the embodiment of the utility model also provides a silicon-based micro-assembly device, which is provided with the three-dimensional packaging structure based on the silicon-based micro-system.
Compared with the prior art, the three-dimensional packaging structure based on the silicon-based microsystem and the silicon-based micro-assembly device have the beneficial effects that: by utilizing the characteristics of bump technology and wafer level bonding in the silicon-based MEMS technology, the isolation ring is arranged around the chip, and when the chip is coated with the conductive adhesive for bonding, the isolation ring can play a role in blocking overflow of the conductive adhesive, so that the conductive adhesive can only be arranged in the isolation ring, the problem of short circuit of a packaging device caused by overflow of the conductive adhesive and connection of surrounding signal holes or circuit patterns is avoided, meanwhile, the signal holes do not need to be avoided, and the structure can be applied to silicon-based packaging to greatly improve the production efficiency and the reliability of products.
Drawings
Fig. 1 is a schematic structural diagram of a first layer silicon substrate and a second layer silicon substrate according to an embodiment of the present utility model;
fig. 2 is a schematic bottom view of a second layer of silicon substrate according to an embodiment of the present utility model;
fig. 3 is a schematic top view of a first layer of silicon substrate according to an embodiment of the present utility model;
fig. 4 is a schematic structural diagram of a three-dimensional package structure based on a silicon-based microsystem according to an embodiment of the present utility model;
FIG. 5 is a schematic diagram of a dimension marking structure of a three-dimensional package structure based on a silicon-based microsystem according to an embodiment of the present utility model;
reference numerals illustrate:
1. a first layer of silicon substrate; 2. a second layer of silicon substrate; 3. a lower micro bump; 4. a lower spacer ring; 5. a first window; 6. applying micro bumps; 7. an upper isolation ring; 8. a functional element bonding region; 9. a third layer of silicon substrate; 10. packaging the cover plate; 11. a spacer ring; 12. a chip; 13. conducting resin; 14. and a second window.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the utility model is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.
Referring to fig. 1 to 4, a three-dimensional package structure based on a silicon-based microsystem according to the present utility model will be described. The three-dimensional packaging structure based on the silicon-based microsystem comprises a first layer of silicon substrate 1 and a second layer of silicon substrate 2, wherein a functional element bonding area 8 is arranged on the first layer of silicon substrate 1; the second layer silicon substrate 2 is arranged on the first layer silicon substrate 1, a first window 5 for avoiding the functional element is arranged on the second layer silicon substrate 2, and the size of the first window 5 is larger than that of the functional element bonding region 8; wherein, the first layer silicon substrate 1 and/or the second layer silicon substrate 2 are provided with isolation rings 11, and the isolation rings 11 encircle the periphery of the first window 5 and are connected between the first layer silicon substrate 1 and the second layer silicon substrate 2.
Compared with the prior art, the three-dimensional packaging structure based on the silicon-based microsystem and the silicon-based micro-assembly device have the beneficial effects that: by utilizing the convex point technology and the wafer level bonding characteristic in the silicon-based MEMS technology, the isolating ring 11 is arranged around the chip 12, and when the chip 12 is coated with the conductive adhesive 13 for bonding, the isolating ring 11 can play a role in blocking overflow of the conductive adhesive 13, so that the conductive adhesive 13 can only be arranged in the isolating ring 11, the problem of short circuit of a packaging device caused by overflow of the conductive adhesive 13 and connection of surrounding signal holes or circuit patterns is avoided, meanwhile, the signal holes do not need to be avoided, and the structure is applied to silicon-based packaging, so that the production efficiency and the reliability of products can be greatly improved.
For the "the first layer silicon substrate 1 or/and the second layer silicon substrate 2 is provided with the spacer ring 11", it should be explained that the arrangement of the spacer ring 11 can be divided into the following three cases: in the first case, the spacer 11 is provided on the first layer silicon substrate 1; in the second case, the spacer 11 is provided on the second layer silicon substrate 2; in the third case, the spacer ring 11 is divided into an upper spacer ring 7 and a lower spacer ring 4, the upper spacer ring 7 is arranged on the second layer silicon substrate 2, the lower spacer ring 4 is arranged on the first layer silicon substrate 1, and the upper spacer ring 7 and the lower spacer ring 4 are aligned during assembly. Wherein the upper spacer ring 7 and the lower spacer ring 4 have the same width and the height dimensions may be different.
The spacer 11 may be made of gold or tin.
In some embodiments, referring to fig. 2, 3 and 5, the spacer 11 has a width W of 18-22um. For example, the width W is any one of 19um, 20um, 21um, etc., 18-22um. The width W is a cross-sectional dimension of the spacer 11 in the left-right direction or the up-down direction.
In some embodiments, referring to fig. 2, 3 and 5, the height H of the spacer 11 is 4-6um. For example, the height H of the spacer 11 is any one of 4um, 4.5um, 5um, 5.5um, 6um, etc., 4 to 6um. The height H of the spacer 11 is the height in the stacking direction of the silicon substrates.
In some embodiments, referring to fig. 2, 3 and 5, the shortest distance L between the inner side of the spacer 11 and the sidewall of the first window 5 is 25-35um. For example, L is any one of 25um, 26um, 27um, 28um, 29um, 30um, 32um, 33um, 34um, etc., 25-35um.
In some embodiments, referring to fig. 1 to 5, the upper surface of the first layer silicon substrate 1 is provided with the lower micro-bump 3 on the outer side of the spacer 11, and the lower surface of the second layer silicon substrate 2 is provided with the upper micro-bump 6 opposite to the lower micro-bump 3. The upper micro-bump 6 and the lower micro-bump 3 play a role in alignment so as to facilitate accurate alignment of the upper spacer ring 7 and the lower spacer ring 4. The upper micro-bump 6 and the lower micro-bump 3 can be directly formed by protruding the metal pillars in the metallized vias.
In some embodiments, referring to fig. 1-5, the shortest distance L1 from the spacer ring 11 to the lower micro-bump 3 or the upper micro-bump 6 is 25-35um. For example, L1 is any one of 25um, 26um, 27um, 28um, 29um, 30um, 32um, 33um, 34um, etc., 25-35um.
In connection with the above dimensional limitations, the following is described: an annular metal pattern, namely, a spacer 11 is formed on the first silicon substrate 1 by etching, and theoretically, the thinner the spacer 11 is, the closer the spacer is to the edge of the first window 5, the more space-saving the more practical application value is. However, the accuracy of the actual silicon-based processing technology and the reliability of the butt joint determine the lower limit of the size of the spacer 11, and through repeated experiments, the size of the spacer 11 is 20um in width, 5um in height, and 30um from the first window 5 is optimal. If the isolating ring 11 is not arranged, the signal holes and the wirings of the second layer silicon substrate 2 can avoid short circuits only by hundreds of um at the edge of the first window 5, and the isolating ring 11 is arranged, so that the distance from the signal holes to the chip 12 is greatly reduced, the space is saved, the miniaturization of devices is facilitated, the yield is improved, and the silicon-based wiring area is also improved.
In some embodiments, referring to fig. 4, the lower micro-bump 3 and the upper micro-bump 6 penetrate up and down through the first layer silicon substrate 1 and the second layer silicon substrate 2, forming a metallized post for transmitting signals. When two layers of silicon substrates are stacked, micro-bumps which transmit signals near the isolation ring 11 are utilized for alignment, and a bonding power curve is adjusted, so that an offset value when upper and lower wafers are stacked can be controlled within 5um.
The three-dimensional packaging structure based on a silicon-based microsystem provided in this embodiment, as shown in fig. 4, further includes a third layer silicon substrate 9 and a packaging cover plate 10 packaged on the third layer silicon substrate 9, wherein a second window 14 coaxial with the first window 5 is provided on the third layer silicon substrate 9, and the size of the second window 14 is larger than the size of the first window 5. Wherein the first window 5 and the second window 14 form a chip 12 packaging cavity; the silicon substrate that can be provided in this embodiment is not limited to three, four or five layers, and the design of the number of layers and the layer height are determined according to the design requirement.
The three-dimensional package structure based on a silicon-based microsystem provided in this embodiment, as shown in fig. 4, further includes a chip 12 glued to the functional element gluing area 8, where the chip 12 is bonded to the second layer silicon substrate 2. In this embodiment, the chip 12 is used as a functional element, and the functional element may be a capacitor, a resistor, an inductor, or the like.
The first layer silicon substrate 1 is coated with conductive adhesive 13, the chip 12 is bonded, and the chip 12 on the second layer silicon substrate 2 is connected by gold wires. The conductive adhesive 13 cannot penetrate the area surrounded by the isolation ring 11, and will not cause short circuit of the peripheral circuit. After assembly is completed, the people do not need to worry about whether the glue amount is too large or not and whether the transmission of surrounding signals is affected, and the degree of assembly automation and the reliability are greatly improved.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Based on the same inventive concept, the embodiment of the application also provides a base micro-assembly device, which is provided with the three-dimensional packaging structure based on the silicon-based micro-system.
The foregoing description of the preferred embodiments of the utility model is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the utility model.
Claims (10)
1. A three-dimensional package structure based on a silicon-based microsystem, comprising:
a first layer of silicon substrate (1), wherein a functional element bonding area (8) is arranged on the first layer of silicon substrate (1); and
the second layer of silicon substrate (2) is arranged on the first layer of silicon substrate (1), a first window (5) for avoiding the functional element is arranged on the second layer of silicon substrate (2), and the size of the first window (5) is larger than that of the functional element bonding area (8);
the first layer silicon substrate (1) or/and the second layer silicon substrate (2) is/are provided with a spacer ring (11), and the spacer ring (11) surrounds the periphery of the first window (5) and is connected between the first layer silicon substrate (1) and the second layer silicon substrate (2).
2. The three-dimensional packaging structure based on silicon-based microsystems as claimed in claim 1, characterized in that the spacer ring (11) has a width W of 18-22um.
3. The three-dimensional packaging structure based on silicon-based microsystems as claimed in claim 1, characterized in that the spacer ring (11) has a height H of 4-6um.
4. The three-dimensional packaging structure based on silicon-based microsystems as claimed in claim 1, characterized in that the shortest distance L of the inner side of the spacer ring (11) from the side wall of the first window (5) is 25-35um.
5. The three-dimensional packaging structure based on the silicon-based microsystem as claimed in claim 1, wherein the upper surface of the first layer silicon substrate (1) is provided with a lower micro-bump (3) outside the isolating ring (11), and the lower surface of the second layer silicon substrate (2) is provided with an upper micro-bump (6) opposite to the lower micro-bump (3).
6. The three-dimensional packaging structure based on silicon-based microsystems as claimed in claim 5, characterized in that the shortest distance L1 of the spacer ring (11) to the lower micro-bump (3) or the upper micro-bump (6) is 25-35um.
7. The three-dimensional packaging structure based on silicon-based microsystems as claimed in claim 5, characterized in that the lower micro-bumps (3) and the upper micro-bumps (6) penetrate the first layer silicon substrate (1) and the second layer silicon substrate (2) up and down to form metallized columns for transmitting signals.
8. The three-dimensional packaging structure based on silicon-based microsystems as claimed in claim 1, further comprising a third layer of silicon substrate (9) and a packaging cover plate (10) packaged on the third layer of silicon substrate (9), wherein a second window (14) coaxial with the first window (5) is arranged on the third layer of silicon substrate (9), and the size of the second window (14) is larger than the size of the first window (5).
9. The three-dimensional packaging structure based on silicon-based microsystems as claimed in claim 8, further comprising a chip (12) glued to the functional element glue area (8), the chip (12) being bonded to the second layer of silicon substrate (2).
10. A silicon-based micro-assembly device, characterized by having a three-dimensional packaging structure based on a silicon-based micro-system as claimed in any one of claims 1-9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202223357456.2U CN219297149U (en) | 2022-12-13 | 2022-12-13 | Three-dimensional packaging structure based on silicon-based microsystem and silicon-based micro-assembly device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202223357456.2U CN219297149U (en) | 2022-12-13 | 2022-12-13 | Three-dimensional packaging structure based on silicon-based microsystem and silicon-based micro-assembly device |
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| CN219297149U true CN219297149U (en) | 2023-07-04 |
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