CN219842992U - Cell structure of semiconductor power device and semiconductor power device - Google Patents
Cell structure of semiconductor power device and semiconductor power device Download PDFInfo
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- CN219842992U CN219842992U CN202222580953.2U CN202222580953U CN219842992U CN 219842992 U CN219842992 U CN 219842992U CN 202222580953 U CN202222580953 U CN 202222580953U CN 219842992 U CN219842992 U CN 219842992U
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Abstract
The utility model discloses a cell structure of a semiconductor power device and the semiconductor power device. The cell structure comprises: a drift region of the first conductivity type having oppositely disposed first and second surfaces; a first doped region of a second conductivity type formed on the first surface of the drift region; a source region of the first conductivity type formed on a surface of the first doped region of the second conductivity type remote from the drift region; a cathode metal layer formed on a surface of the source region remote from the drift region; a trench gate structure extending from the surface of the source region into the drift region; an interlayer dielectric layer positioned between the trench gate structure and the cathode metal layer; an anode metal layer on the second surface of the drift region; and a plurality of well regions of the second conductivity type spaced apart from each other in the drift region and below the trench gate structure.
Description
Technical Field
The present utility model relates to the field of semiconductor technologies, and in particular, to a cell structure of a semiconductor power device and a semiconductor power device.
Background
In the related art, in a conventional trench gate semiconductor power device, electrons of a source are easily accumulated at the bottom of a trench gate structure in a drift region during injection of electrons into the drift region through a channel, and an electron accumulation phenomenon is aggravated at a bottom corner of the trench gate structure, which may cause electric field accumulation at the bottom of the trench gate structure, particularly at the bottom corner. The electric field concentration not only easily causes the gate oxide layer of the trench gate structure to be broken down, but also easily causes the charge amount of the gate to be increased, thereby causing the trench gate semiconductor power device to require a larger driving current. Further, a larger driving current causes an increase in the switching speed of the semiconductor power device, thereby causing excessive switching loss.
Disclosure of Invention
The present utility model aims to solve at least one of the technical problems existing in the prior art. To this end, an object of the present utility model is to provide a cell structure of a semiconductor power device. When the cell structure of the semiconductor power device is applied to the semiconductor power device, the electric field concentration effect at the bottom of the trench gate structure can be relieved, the breakdown voltage of the semiconductor power device is improved, the gate capacitance of the semiconductor power device is reduced, the gate charge quantity is reduced, and therefore the driving current of the semiconductor power device is reduced, and the switching loss is reduced.
Another object of the present utility model is to provide a semiconductor power device.
The cell structure of the semiconductor power device according to the embodiment of the first aspect of the utility model comprises: a drift region of a first conductivity type, the drift region having oppositely disposed first and second surfaces; a first doped region of a second conductivity type formed on the first surface of the drift region; a source region of a first conductivity type formed on a surface of the first doped region of the second conductivity type remote from the drift region; a cathode metal layer formed on a surface of the source region remote from the drift region; a trench gate structure extending from the surface of the source region into the drift region; the interlayer dielectric layer is positioned between the trench gate structure and the cathode metal layer; an anodic metal layer on the second surface of the drift region; and a plurality of well regions of the second conductivity type spaced apart from each other in the drift region and below the trench gate structure.
According to the cell structure of the semiconductor power device, through the arrangement of the drift region of the first conductivity type, the first doped region of the second conductivity type, the source region of the first conductivity type, the cathode metal layer, the trench gate structure, the interlayer dielectric layer, the anode metal layer and the plurality of well regions of the second conductivity type, the drift region is provided with the first surface and the second surface which are oppositely arranged, the first doped region of the second conductivity type is formed on the first surface of the drift region, the source region is formed on the surface of the first doped region of the second conductivity type, which is far away from the drift region, the cathode metal layer is formed on the surface of the source region, which is far away from the drift region, the surface of the trench gate structure extends into the drift region, the interlayer dielectric layer is located between the trench gate structure and the cathode metal layer, the anode metal layer is located on the second surface of the drift region, the well regions of the second conductivity type are located in the drift region at intervals, and below the trench gate structure, when the cell structure is applied to the semiconductor power device, and the semiconductor power device is applied with voltage, the second conductivity type is applied, the electric field concentration of the first conductivity type is reduced, the semiconductor power is reduced, the electric field concentration is carried out between the first conductivity type and the semiconductor power device is reduced, the drain region is reduced, the electric field concentration is reduced, the electric field effect is reduced, and the electric field effect is reduced. In addition, by a plurality of well regions of the second conductivity type being located in the drift region and below the trench gate structure with a spacing from each other, a material utilized for formation of the well regions of the second conductivity type can be reduced as compared to forming a continuous well region of the second conductivity type below the trench gate structure, thereby reducing costs.
According to some embodiments of the utility model, the trench gate structure includes a gate conductive material and a gate oxide layer formed on an outer periphery of the gate conductive material.
According to some embodiments of the utility model, a plurality of well regions of the second conductivity type are in contact with the gate oxide layer.
According to some embodiments of the utility model, a plurality of well regions of the second conductivity type are arranged in an array below the trench gate structure.
According to some embodiments of the utility model, the trench gate structure is U-shaped or semicircular in cross section.
According to some embodiments of the utility model, the trench gate structure has a U-shaped cross section, the outer periphery of the trench gate structure comprising a first surface portion extending from a surface of the source region remote from the drift region in a first direction towards the drift region, the first direction being parallel to a depth direction of the drift region, a second surface portion extending within the drift region in a second direction perpendicular to the first direction, and a third surface portion being a rounded slip surface and connected between the first and second surface portions, the well region of the second conductivity type being in contact with the second and/or third surface portions.
According to some embodiments of the utility model, the cell structure further comprises: a second doped region of a second conductivity type extending in the first doped region of the second conductivity type from a surface of the first doped region of the second conductivity type remote from the drift region, the second doped region of the second conductivity type being spaced apart from the trench gate structure.
According to some embodiments of the utility model, the source region of the first conductivity type is an N-type doped region having a doping concentration of 10 14 atom/cm 3 ～10 15 atom/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the And/or the second doped region of the second conductivity type is a P-type doped region with a doping concentration of 10 15 atom/cm 3 ～10 16 atom/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the And/or the first doped region of the second conductivity type is a P-type doped region with a doping concentration of 10 14 atom/cm 3 ～10 15 atom/cm 3 。
According to some embodiments of the utility model, the drift region comprises a first doped drift region of a first conductivity type and a second doped drift region of a first conductivity type stacked in a direction from the first surface to the second surface, the first surface being a surface of the first doped drift region of the first conductivity type and the second surface being a surface of the second doped drift region of the first conductivity type.
According to some embodiments of the utility model, the first doped drift region of the first conductivity type is an N-type doped region with a doping concentration of 10 13 atom/cm 3 ～10 14 atom/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the And/or the second doped drift region of the first conductivity type is an N-type doped region with a doping concentration of 10 15 atom/cm 3 ～10 16 atom/cm 3 。
According to some embodiments of the utility model, the well region of the second conductivity type is a P-type doped region with a doping concentration of 10 14 atom/cm 3 ～10 15 atom/cm 3 。
A semiconductor power device according to an embodiment of the second aspect of the present utility model includes a plurality of cell structures according to the embodiment of the first aspect of the present utility model, wherein the plurality of cell structures are connected in parallel.
According to some embodiments of the utility model, the semiconductor power device is a Metal Oxide Semiconductor (MOS) power device.
Additional aspects and advantages of the utility model will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the utility model.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:
fig. 1 is a cross-sectional view of a cell structure of a semiconductor power device according to an embodiment of the present utility model.
Fig. 2A-2L are schematic manufacturing process diagrams of a cell structure of a semiconductor power device according to an embodiment of the present utility model.
Reference numerals:
a cell structure 100; a drift region 1 of the first conductivity type; a first surface 11; a second surface 12;
a first doped drift region 13 of a first conductivity type; a second doped drift region 14 of the first conductivity type;
a doped region 15 of the first conductivity type; a first doped region 2 of a second conductivity type; a source region 3 of the first conductivity type;
a cathode metal layer 4; a trench gate structure 5; a gate conductive material 51; a gate oxide layer 52; an outer peripheral surface 53;
a first surface portion 531; a second surface portion 532; a third surface portion 533; an interlayer dielectric layer 6; an anode metal layer 7;
a well region 8 of the second conductivity type; a second doped region 9 of a second conductivity type; a substrate 10; a trench 101.
Detailed Description
For a more complete understanding of the nature and the technical content of the embodiments of the present utility model, reference should be made to the following detailed description of embodiments of the utility model, taken in conjunction with the accompanying drawings, which are meant to be illustrative only and not limiting of the embodiments of the utility model. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.
The following describes a cell structure 100 of a semiconductor power device according to an embodiment of the present utility model with reference to fig. 1 and fig. 2A to 2L.
As shown in fig. 1, a cell structure 100 of a semiconductor power device according to an embodiment of the first aspect of the present utility model includes: a drift region 1 of a first conductivity type, a first doped region 2 of a second conductivity type, a source region 3 of the first conductivity type, a cathode metal layer 4, a trench gate structure 5, an interlayer dielectric layer 6, and an anode metal layer 7. Specifically, the drift region 1 of the first conductivity type has a first surface 11 and a second surface 12 disposed opposite to each other, and the first doped region 2 of the second conductivity type is formed on the first surface 11 of the drift region 1 of the first conductivity type. The source region 3 is formed on a surface of the first doped region 2 of the second conductivity type remote from the drift region 1. A cathode metal layer 4 is formed on the surface of the source region 3 remote from the drift region 1, at which time an electrical contact is made between the source region 3 and the cathode metal layer 4 operates as a source electrode. For example, the cathode metal layer 4 may be a metal layer made of a metal such as metallic titanium or aluminum, but is not limited thereto. A trench gate structure 5 extends from the above-mentioned surface of the source region 3 into the drift region 1. An interlayer dielectric layer 6 is located between the trench gate structure 5 and the cathode metal layer 4 to form an electrical insulation between the trench gate structure 5 and the cathode metal layer 4. For example, the interlayer dielectric layer 6 is made of borophosphosilicate glass layer, but is not limited thereto. An anode metal layer 7 is located on the second surface 12 of the drift region 1, wherein the anode metal layer 7 is operable as a drain electrode. For example, the anode metal layer 7 may be a metal layer made of a metal such as metallic titanium or aluminum, but is not limited thereto.
The cell structure 100 further comprises a plurality of well regions 8 of the second conductivity type, the plurality of well regions 8 of the second conductivity type being located in the drift region 1 spaced apart from each other and below the trench gate structure 5. In the description of the present utility model, "plurality" means two or more than two. When the cell structure 100 is applied to a semiconductor power device and the semiconductor power device is applied with voltage, the well region 8 of the second conductivity type and the drift region 1 of the first conductivity type form a reverse PN junction to bear the voltage, and a space charge region is formed between the well region 8 of the second conductivity type and the drift region 1 of the first conductivity type, so that the electric field distribution at the bottom of the trench gate structure 5 is changed, the electric field concentration effect at the bottom of the trench gate structure 5 is relieved, the breakdown voltage of the semiconductor power device is improved, the gate capacitance of the semiconductor power device is reduced, the gate charge amount is reduced, the driving current of the semiconductor power device is reduced, and the switching loss is reduced. In addition, by a plurality of well regions 8 of the second conductivity type being located in the drift region 1 and below the trench gate structure 5 spaced apart from each other, the material utilized for formation of the well regions of the second conductivity type can be reduced as compared to forming a continuous well region of the second conductivity type below the trench gate structure, thereby reducing the cost.
According to the cell structure of the semiconductor power device, through the arrangement of the drift region of the first conductivity type, the first doped region of the second conductivity type, the source region of the first conductivity type, the cathode metal layer, the trench gate structure, the interlayer dielectric layer, the anode metal layer and the plurality of well regions of the second conductivity type, the drift region is provided with the first surface and the second surface which are oppositely arranged, the first doped region of the second conductivity type is formed on the first surface of the drift region, the source region is formed on the surface of the first doped region of the second conductivity type, which is far away from the drift region, the cathode metal layer is formed on the surface of the source region, which is far away from the drift region, the interlayer dielectric layer is located between the trench gate structure and the cathode metal layer, the anode metal layer is located on the second surface of the drift region, and the plurality of well regions of the second conductivity type are located in the drift region at intervals, and below the trench gate structure, when the cell structure is applied to the semiconductor power device, the second conductivity type first doped region is formed on the first surface of the drift region, the second conductivity type is far away from the surface of the drift region, the electric field loss of the semiconductor power device is reduced, the electric field concentration of the semiconductor power device is reduced, the drain region is reduced, and the drain region is reduced. In addition, by a plurality of well regions of the second conductivity type being located in the drift region and below the trench gate structure with a spacing from each other, a material utilized for formation of the well regions of the second conductivity type can be reduced as compared to forming a continuous well region of the second conductivity type below the trench gate structure, thereby reducing costs.
According to some embodiments of the present utility model, as shown in fig. 1, the trench gate structure 5 includes a gate conductive material 51 and a gate oxide layer 52, the gate oxide layer 52 being formed on an outer peripheral surface of the gate conductive material 51, wherein the gate conductive material 51 forms a gate electrode. For example, the gate oxide layer 52 is a silicon oxide layer, but is not limited thereto.
According to a further embodiment of the present utility model, as shown in fig. 1, a plurality of well regions 8 of the second conductivity type are in contact with the gate oxide layer 52. In other words, the plurality of well regions 8 of the second conductivity type are located on the lower surface of the gate oxide layer 52. At this time, the plurality of well regions 8 of the second conductivity type may directly form space charge regions between the lower surface of the gate oxide layer 52 and the drift region 1 of the first conductivity type, directly and more greatly change the electric field distribution at the bottom of the trench gate structure 5, and more greatly alleviate the electric field concentration effect at the bottom of the trench gate structure 5.
Alternatively, as shown in fig. 1, a plurality of well regions 8 of the second conductivity type are arranged in an array below the trench gate structure 5. In other words, a plurality of well regions 8 of the second conductivity type are arranged in a row below the trench gate structure 5. By such arrangement, the arrangement of the plurality of well regions 8 of the second conductivity type is regular, so that in the manufacturing process of the cellular structure 100, the plurality of well regions 8 of the second conductivity type can be prepared according to the predetermined layout rule, thereby improving the manufacturing efficiency of the plurality of well regions 8 of the second conductivity type, and further improving the manufacturing efficiency of the cellular structure 100.
Optionally, as shown in fig. 1, the cross section of the trench gate structure 5 is U-shaped; alternatively, the trench gate structure 5 may be semi-circular in cross-section. By the arrangement, the sharp angle does not exist in the trench gate structure 5, particularly, the sharp angle does not exist at the bottom of the trench gate structure 5, and the electric field concentration effect at the bottom of the trench gate structure 5 can be further relieved.
Of course, the present utility model is not limited thereto. The cross-section of the trench gate structure 5 may also be other shapes without sharp corners, such as semi-elliptical, etc.
According to some embodiments of the present utility model, as shown in fig. 1, the trench gate structure 5 has a U-shaped cross section, and the outer peripheral surface 53 of the trench gate structure 5 comprises a first surface portion 531, a second surface portion 532 and a third surface portion 533, the first surface 531 extending from the surface of the source region 3 remote from the drift region 1 in a first direction towards the drift region 1. The first direction is parallel to the depth direction of the drift region 1, and is then parallel to the stacking direction of the drift region 1 of the first conductivity type, the first doped region 2 of the second conductivity type, the source region 3 of the first conductivity type, the cathode metal layer 4, the interlayer dielectric layer 6 and the anode metal layer 7. The second surface portion 532 extends in a second direction perpendicular to the first direction within the drift region 1, the third surface portion 533 is rounded and is connected between the first surface portion 531 and the second surface portion 532, and the well region 8 of the second conductivity type is in contact with the second surface portion 532 and/or the third surface portion 533. For example, only the second surface portion 532 has the well region 8 of the second conductivity type disposed thereon; or only the third surface portion 533 has the well region 8 of the second conductivity type arranged thereon, while the bottom corner of the trench gate structure 5 has the well region 8 of the second conductivity type arranged thereon; further alternatively, the well region 8 of the second conductivity type is arranged on the second surface portion 532 and the third surface portion 533, and at this time, the well region 8 of the second conductivity type is arranged on the entire bottom outer surface of the trench gate structure 5. So arranged, it is possible to flexibly select on which portions of the bottom of the trench gate structure 5 the well region 8 of the second conductivity type is arranged, as required, while ensuring relief of the electric field concentration effect at the bottom of the trench gate structure 5.
According to some embodiments of the present utility model, as shown in fig. 1, the cellular structure 100 further comprises a second doped region 9 of the second conductivity type, the second doped region 9 of the second conductivity type extending in the first doped region 2 of the second conductivity type from a surface of the first doped region 2 of the second conductivity type remote from the drift region 1, the second doped region 9 of the second conductivity type being spaced apart from the trench gate structure 5.
Alternatively, as shown in fig. 1, the drift region 1 includes a first doped drift region 13 of the first conductivity type and a second doped drift region 14 of the first conductivity type stacked in a direction from the first surface 11 to the second surface 12, the first surface 11 being a surface of the first doped drift region 13 of the first conductivity type, the second surface 12 being a surface of the second doped drift region 14 of the first conductivity type. At this time, the second doped drift region 14 of the first conductivity type is an epitaxial layer of the first conductivity type.
In the description of the present utility model, the above-described "first conductivity type" may refer to an N-type conductivity type, and the "second conductivity type" may refer to a P-type conductivity type. For example, N-type conductivity refers to doping with phosphorus or nitrogen, etc., and P-type conductivity refers to doping with aluminum, etc.
Of course, the present utility model is not limited thereto. For example, the above-described "first conductivity type" may refer to a P-type conductivity, and the "second conductivity type" may refer to an N-type conductivity.
Alternatively, in the case where the "first conductivity type" is the N-type conductivity and the "second conductivity type" is the P-type conductivity, the respective regions of the cell structure 100 have respective doping concentrations.
Optionally, the source region 3 of the first conductivity type is an N-type doped region with a doping concentration of 10 14 atom/cm 3 ～10 15 atom/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the And/or the second doped region 9 of the second conductivity type is a P-type doped region with a doping concentration of 10 15 atom/cm 3 ～10 16 atom/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the And/or the first doped region 2 of the second conductivity type is a P-type doped region with a doping concentration of 10 14 atom/cm 3 ～10 15 atom/cm 3 。
For example, the doping element of the source region 3 of the first conductivity type is phosphorus with a doping concentration of 10 14 atom/cm 3 ～10 15 atom/cm 3 . For example, the doping element of the second doping region 9 of the second conductivity type is aluminum, the doping concentration is 10 15 atom/cm 3 ～10 16 atom/cm 3 . For example, the doping element of the first doped region 2 of the second conductivity type is aluminum with a doping concentration of 10 14 atom/cm 3 ～10 15 atom/cm 3 。
Optionally, the first doped drift region 13 of the first conductivity type is an N-type doped region with a doping concentration of 10 13 atom/cm 3 ～10 14 atom/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the And/or the second doped drift region 14 of the first conductivity type is an N-type doped region with a doping concentration of 10 15 atom/cm 3 ～10 16 atom/cm 3 。
For example, the doping concentration of the first doped drift region 13 of the first conductivity type is 10 13 atom/cm 3 ～10 14 atom/cm 3 . For example, the doping concentration of the second doped drift region 14 of the first conductivity type is 10 15 atom/cm 3 ～10 16 atom/cm 3 . For example, the doping element of the well region 8 of the second conductivity type is aluminum, the doping concentration is 10 14 atom/cm 3 ～10 15 atom/cm 3 。
An exemplary fabrication process flow for the above-described cell structure 100 for a semiconductor power device is described below in connection with fig. 2A-2L.
First, as shown in fig. 2A, a substrate 10 of a first conductivity type is provided, the substrate 10 comprising opposite first and second sides. For example, the substrate 10 is a single crystal silicon substrate or a silicon carbide substrate, but is not limited thereto.
Next, as shown in fig. 2B, trenches 101 are etched in the first side of the substrate 10. Optionally, before etching the trench 101, the first side of the substrate 10 is subjected to surface cleaning to remove impurity particles, then a thermal oxidation process is performed on the surface of the first side to form an oxide layer (e.g., a silicon dioxide layer), then photoresist is spin-coated on the oxide layer to form a mask, and then the trench 101 is etched on the first side of the substrate 10 through soft baking, exposure, development, and the like. For example, the trench 101 is formed in a semi-ellipsoidal shape or a hemispherical shape, but is not limited thereto.
Next, as shown in fig. 2C, ion doping of the second conductivity type is performed at a plurality of positions of the bottom wall of the trench 101 to form a plurality of well regions 8 of the second conductivity type spaced apart from each other under the trench 101. For example, ion compounds of the second conductivity type (e.g., aluminum-containing ion compounds) are implanted at a plurality of spaced apart locations of the bottom wall of the trench 101 by a high-energy ion implantation method, after which the photoresist is cleaned and subjected to a baking operation, and then impurities (e.g., aluminum-containing ion compounds) are activated by high-temperature diffusion push-junction in a diffusion furnace, forming a plurality of well regions 8 of the second conductivity type spaced apart from each other.
Next, as shown in fig. 2D, a gate oxide layer 52 is deposited and formed on the inner wall surface of the trench 101, and the gate conductive material 52 is filled in the trench 101 to form a gate material layer, wherein the gate oxide layer 52 and the gate material layer form a trench gate structure 5. For example, the gate oxide layer 52 (e.g., a silicon oxide layer) and the gate material layer (e.g., a polysilicon layer) are formed on the inner wall surfaces of the trench 101 by low pressure chemical vapor deposition (Low Pressure Chemical vapor Deposition, LPCVD) or atmospheric pressure chemical vapor deposition (Atmospheric Pressure Chemical Vapor Deposition, APCVD) or other deposition processes.
Next, as shown in fig. 2E, ion doping of the second conductivity type is performed at the surface of the first side of the substrate 10 except the trench 101 to form a first doped region 2 of the second conductivity type. For example, the regions of the first side of the substrate 10 other than the trenches 101 are surface-cleaned to remove impurity particles, then thermally oxidized to form an oxide layer (e.g., a silicon oxide layer), then spin-coated with photoresist to form a reticle, then subjected to soft baking, exposure, development, etc., and implanted with ions of a second conductivity type (e.g., an aluminum-containing ionic compound), the photoresist is cleaned, and a baking operation is performed. Finally, ions of the second conductivity type (e.g., aluminum-containing ionic compounds) are activated in the diffusion furnace by high-temperature diffusion junction pushing to form the first doped region 2 of the second conductivity type.
Next, as shown in fig. 2F, ion doping of the first conductivity type is performed at the surface of the first doped region 2 of the second conductivity type away from the second side to form a doped region 15 of the first conductivity type. For example, the region of the first side of the substrate 10 other than the trench 101 is surface-cleaned to remove impurity particles, then thermally oxidized to form an oxide layer (e.g., a silicon oxide layer), then spin-coated with photoresist to form a mask, then subjected to soft baking, exposure, development, etc., and ion implantation of the first conductivity type (e.g., a phosphorus-containing ion compound) by an ion implantation process, and the photoresist is cleaned and baked. Finally, ions of the first conductivity type (e.g., ion compounds containing phosphorus) are activated in the diffusion furnace by high temperature diffusion pushing to form doped regions 15 of the first conductivity type.
Next, as shown in fig. 2G, the first-conductivity-type-doped region 15 is etched to remove an edge portion of the first-conductivity-type-doped region to form the first-conductivity-type-source region 3.
Next, as shown in fig. 2I, an interlayer dielectric layer 6 is formed on the trench gate structure 5. The borophosphosilicate glass layer is formed, for example, by a deposition or thermal oxidation process.
Next, as shown in fig. 2J, a cathode metal layer 4 is formed on the first doped region 2 of the second conductivity type, the interlayer dielectric layer 6, and the side of the source region 3 of the first conductivity type remote from the first side of the substrate 10. The cathode metal layer 4 formed of an aluminum copper alloy or a titanium aluminum alloy is formed, for example, by a sputtering process such as sputtering aluminum or titanium, and then sputtering copper.
Next, as shown in fig. 2L, an anode metal layer 7 is formed on the second side of the first conductivity type substrate 10. For example, the second side of the substrate 10 of the first conductivity type is cleaned, and then the anode metal layer 7 composed of an aluminum copper alloy or a titanium silver alloy is formed by a sputtering process.
Optionally, after forming the source region 3 of the first conductivity type and before forming the interlayer dielectric layer 6 on the trench gate structure 5, as shown in fig. 2H, ion doping of the second conductivity type may be performed in the first doped region 2 of the second conductivity type to form a second doped region 9 of the second conductivity type. For example, an aluminum-containing ion compound is implanted into the first doped region 2 of the second conductivity type by an ion implantation method, and the aluminum-containing ion compound is activated by high-temperature diffusion pushing in a diffusion furnace to form the second doped region 9 of the second conductivity type.
Alternatively, before forming the anode metal layer 7 on the second side of the first conductive type substrate 10, as shown in fig. 2K, ion doping of the first conductive type may be performed on the second side of the first conductive type substrate 10 to form the second doped drift region 14 of the first conductive type. For example, in the case where the first conductivity type is the N-type conductivity type, the second doped drift region 14 of the N-type may be epitaxially grown by doping phosphorus or nitrogen by ion implantation at the second side of the substrate 10 of the first conductivity type.
A semiconductor power device according to an embodiment of the second aspect of the present utility model comprises a plurality of cell structures 100 according to an embodiment of the first aspect of the present utility model, wherein the plurality of cell structures 100 are connected in parallel.
According to the semiconductor power device provided by the embodiment of the utility model, the space charge region is formed between the well region of the second conductivity type and the drift region of the first conductivity type of each cell structure by the cell structure according to the embodiment of the first aspect of the utility model, so that the electric field distribution at the bottom of the trench gate structure is changed, the electric field concentration effect at the bottom of the trench gate structure is relieved, the breakdown voltage of the semiconductor power device is improved, the gate capacitance of the semiconductor power device is reduced, and the gate charge quantity is reduced, thereby reducing the driving current of the semiconductor power device and the switching loss.
Alternatively, the semiconductor power device is a metal oxide semiconductor (Metal Oxide Semiconductor, MOS) power device, but is not limited thereto.
The terminology used in the present utility model is used for the purpose of describing embodiments only and is not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a," "an," and "the" (the) are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this disclosure is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, when used in the present disclosure, the terms "comprises," "comprising," and/or variations thereof, mean that the recited features, integers, steps, operations, elements, and/or components are present, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The technical description above refers to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration implementations in accordance with the described embodiments. While these embodiments are described in sufficient detail to enable those skilled in the art to practice them, these embodiments are non-limiting; other embodiments may be used, and changes may be made without departing from the scope of the described embodiments. For example, the order of operations described in the process flow diagrams is non-limiting, and thus the order of two or more operations illustrated in the process flow diagrams and described in accordance with the process flow diagrams may be altered according to several embodiments. As another example, in several embodiments, one or more operations illustrated in and described in accordance with a process flow diagram are optional or are removable. In addition, certain steps or functions may be added to the disclosed embodiments or more than two of the step sequences may be substituted. All such variations are considered to be encompassed by the disclosed embodiments and the claims.
Additionally, terminology is used in the above technical description to provide a thorough understanding of the described embodiments. However, no overly detailed details are required to implement the described embodiments. Accordingly, the foregoing description of the embodiments has been presented for purposes of illustration and description. The embodiments presented in the foregoing description and examples disclosed in accordance with these embodiments are provided separately to add context and aid in the understanding of the described embodiments. The foregoing description is not intended to be exhaustive or to limit the described embodiments to the precise form of the utility model. Several modifications, alternative adaptations and variations are possible in light of the above teachings. In some instances, well known process steps have not been described in detail in order to avoid unnecessarily obscuring the described embodiments.
Claims (13)
1. A cell structure of a semiconductor power device, comprising:
a drift region of a first conductivity type, the drift region having oppositely disposed first and second surfaces;
a first doped region of a second conductivity type formed on the first surface of the drift region;
a source region of a first conductivity type formed on a surface of the first doped region of the second conductivity type remote from the drift region;
a cathode metal layer formed on a surface of the source region remote from the drift region;
a trench gate structure extending from the surface of the source region into the drift region;
the interlayer dielectric layer is positioned between the trench gate structure and the cathode metal layer;
an anodic metal layer on the second surface of the drift region; and
a plurality of well regions of a second conductivity type, the plurality of well regions of the second conductivity type being located in the drift region spaced apart from one another and below the trench gate structure.
2. The cell structure according to claim 1, wherein the trench gate structure includes a gate conductive material and a gate oxide layer formed on an outer peripheral surface of the gate conductive material.
3. The cell structure of claim 2, wherein a plurality of well regions of the second conductivity type are in contact with the gate oxide layer.
4. A cellular structure according to any of claims 1-3, wherein a plurality of well regions of said second conductivity type are arranged in an array below said trench gate structure.
5. A cellular structure according to any of claims 1-3, wherein the trench gate structure is U-shaped or semi-circular in cross section.
6. The cell structure according to claim 5, wherein the trench gate structure has a U-shaped cross section, and an outer peripheral surface of the trench gate structure includes a first surface portion extending from a surface of the source region away from the drift region in a first direction toward the drift region, the first direction being parallel to a depth direction of the drift region, a second surface portion extending in a second direction perpendicular to the first direction within the drift region, and a third surface portion being a rounded surface and connected between the first surface portion and the second surface portion, and a well region of the second conductivity type being in contact with the second surface portion and/or the third surface portion.
7. A cellular structure according to any of claims 1-3, further comprising:
a second doped region of a second conductivity type extending in the first doped region of the second conductivity type from a surface of the first doped region of the second conductivity type remote from the drift region, the second doped region of the second conductivity type being spaced apart from the trench gate structure.
8. The cell structure of claim 7, wherein the source region of the first conductivity type is an N-type doped region having a doping concentration of 10 14 atom/cm 3 ～10 15 atom/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the And/or
The second doped region of the second conductivity type is a P-type doped region with a doping concentration of 10 15 atom/cm 3 ～10 16 atom/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the And/or
The first doped region of the second conductivity type is a P-type doped region with a doping concentration of 10 14 atom/cm 3 ～10 15 atom/cm 3 。
9. A cellular structure according to any of claims 1-3, wherein the drift region comprises a first doped drift region of a first conductivity type and a second doped drift region of a first conductivity type stacked in a direction from the first surface to the second surface, the first surface being a surface of the first doped drift region of the first conductivity type and the second surface being a surface of the second doped drift region of the first conductivity type.
10. The cell structure of claim 9, wherein the first doped drift region of the first conductivity type is an N-type doped region having a doping concentration of 10 13 atom/cm 3 ～10 14 atom/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the And/or
The second doped drift region of the first conductivity type is an N-type doped region with a doping concentration of 10 15 atom/cm 3 ～10 16 atom/cm 3 。
11. A cell structure according to any one of claims 1-3, wherein the well region of the second conductivity type is a P-type doped region having a doping concentration of 10 14 atom/cm 3 ～10 15 atom/cm 3 。
12. A semiconductor power device comprising a plurality of cell structures according to any one of claims 1-11, wherein the plurality of cell structures are connected in parallel.
13. The semiconductor power device of claim 12, wherein the semiconductor power device is a metal oxide semiconductor power device.
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