CN219834123U - High-sensitivity receiving module - Google Patents

High-sensitivity receiving module Download PDF

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Publication number
CN219834123U
CN219834123U CN202320536003.1U CN202320536003U CN219834123U CN 219834123 U CN219834123 U CN 219834123U CN 202320536003 U CN202320536003 U CN 202320536003U CN 219834123 U CN219834123 U CN 219834123U
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China
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electric capacity
pin
inductor
chip
amplifier
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CN202320536003.1U
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Chinese (zh)
Inventor
毋振宇
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Shenzhen Kelvin Electronics Co ltd
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Shenzhen Kelvin Electronics Co ltd
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00Reducing energy consumption in communication networks
    • Y02D30/70Reducing energy consumption in communication networks in wireless communication networks

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Abstract

The utility model discloses a high-sensitivity receiving module, which comprises an integrated chip U1, wherein the integrated chip U1 adopts a radio frequency receiving chip, and the radio frequency receiving chip is electrically connected with an amplifier. The utility model has effective anti-shake property, greatly improves the overall sensitivity, and more importantly, the receiving distance in the space with electromagnetic wave interference is greatly improved, and the utility model can meet the use requirement.

Description

High-sensitivity receiving module
Technical Field
The utility model relates to the technical field of wireless receiving modules, in particular to a high-sensitivity receiving module.
Background
As known, a wireless receiving module is an indispensable module in a wireless transmission process by using a wireless technology, so that the wireless receiving module is widely applied to the fields of a computer wireless network, wireless communication, wireless control and the like so as to receive an external signal, thereby enabling people to realize a wireless control or transmission function. However, the whole operation process of the existing wireless receiving module is greatly affected by noise, especially the distance in the electromagnetic interference free space is greatly limited, the sensitivity of the system is greatly reduced, the use requirements of modern people cannot be met, and improvement is needed.
Disclosure of Invention
First, the technical problems to be solved
Aiming at the defects in the prior art, the utility model provides a high-sensitivity receiving module which has effective anti-shake performance, greatly improves the overall sensitivity, and more importantly, greatly improves the receiving distance in the space with electromagnetic wave interference and can meet the use requirement.
(II) technical problem to be solved
In order to achieve the above purpose, the technical scheme adopted by the utility model is as follows:
the high-sensitivity receiving module comprises an integrated chip U1, wherein the integrated chip U1 adopts a radio frequency receiving chip, and the radio frequency receiving chip is electrically connected with an amplifier.
Preferably, the radio frequency receiving chip is of the type CMT2210LH and the amplifier is of the type BFP420H6.
Preferably, the radio frequency receiving chip comprises a chip body, a ground wire pin of the chip body is connected with a ground wire end,the saidThe antenna pin of chip body is connected with electric capacity C1 and connects in series inductance L1, inductance two L2 and inductance three L3, electric capacity C1 is connected with the ground terminal, connect in parallel on the inductance two L2 and have electric capacity two C5, inductance three L3 is connected with resistance R1, electric capacity three C6 and electric capacity four C7, electric capacity four C7 electricity is connected with the amplifier, the power voltage lead pin cluster of chip body connects with electric capacity five C2, electric capacity six C3, electric capacity seven 13 and the amplifier, the empty foot of chip body is connected with power voltage lead pin, the output pin of chip body is connected with crystal resonator Y1, the digital output pin of chip body is connected with connector JP1, connector JP1 is connected with the amplifier.
Preferably, the crystal resonator Y1 is 27.1412MHz.
Preferably, the amplifier includes LNA amplifier Q1 and electronic components U2, the first pin of plug-in connector JP1 is connected with electrically electronic components U2, the second pin and the third pin of plug-in connector JP1 all are connected with electrically the digital output pin of chip body, the fourth pin and the fifth pin of plug-in connector JP1 all are connected with the ground terminal, electronic components U2 parallel connection has electric capacity eighth C4, electronic components U2 is connected with electric capacity ninth C15 and resistance second R5, resistance second R5 is connected with electric capacity tenth C14, electric capacity seventh 13 and resistance tri R4 respectively, resistance tri R4 is connected with resistance fourth L4 and electric capacity twelve C8 respectively, inductance fourth L4 is connected with the fourth pin and the electric capacity fourth C7 of LNA amplifier Q1 respectively, resistance fourth R3 is connected with electric capacity thirteen C10 and electric capacity five L6 respectively, inductance seven L7 is connected with electric capacity eight C8, inductance L7 is connected with electric capacity seven connects the electric capacity nine L6, the electric capacity connects the electric capacity seven L7 to the ground terminal, inductance nine L is connected with the electric capacity seven connects the electric capacity seven L8, the electric capacity connects the electric capacity nine L7 to the electric capacity connects the nine L, the electric capacity connects the nine L8 to the electric capacity connects.
Preferably, SSP6206-33NR is adopted for the electronic component U2.
(III) technical effects to be achieved
Compared with the prior art, the utility model has the beneficial effects that:
the utility model comprises an integrated chip U1, wherein the integrated chip U1 adopts a radio frequency receiving chip, the radio frequency receiving chip is electrically connected with an amplifier, the radio frequency receiving chip adopts a model of CMT2210LH, and the amplifier adopts a model of BFP420H6, so that the integrated chip U1 has effective anti-shake performance, the integral sensitivity is greatly improved, and more importantly, the receiving distance in an electromagnetic wave interference space is greatly improved, and the use requirement can be met.
Drawings
FIG. 1 is a schematic diagram of the structure of the present utility model.
Description of the embodiments
In the description of the present utility model, it will be understood that when an element is referred to as being "fixed" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
In the description of the present utility model, it should be noted that the terms "center", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, or orientations or positional relationships in which the inventive product is conventionally placed in use, are merely for convenience in describing the present utility model and simplifying the description, and do not indicate or imply that the apparatus or element to be referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present utility model. Furthermore, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present utility model, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. The meaning of "a number" is one or more than one unless specifically defined otherwise.
In the description of the present utility model, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.
The present utility model will be further described in detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present utility model more apparent. It should be understood that the detailed description and specific examples, while indicating the utility model, are intended for purposes of illustration only and are not intended to limit the scope of the utility model. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the present utility model.
Embodiment one: referring to fig. 1, a high-sensitivity receiving module includes an integrated chip U1, where the integrated chip U1 is a radio frequency receiving chip, and the radio frequency receiving chip is electrically connected to an amplifier. The utility model has effective anti-shake property, greatly improves the overall sensitivity, and more importantly, the receiving distance in the space with electromagnetic wave interference is greatly improved, and the utility model can meet the use requirement.
Embodiment two: as shown in fig. 1, it can be illustrated that, based on the first embodiment, the type of the rf receiving chip is CMT2210LH, the receiving sensitivity of the rf receiving chip through the CMT2210LH is effectively improved by 11dB gain (actually measured by using a signal generator), and the type of the amplifier is BFP420H6 (low noise high gain LNA amplifier of infliximab technology corporation), so that the receiving sensitivity of the rf receiving chip can be effectively improved by 11dB gain (actually measured by using a signal generator), the highest sensitivity is improved from-111 dBm to-122 dBm, and the receiving distance can be increased by three times in the electromagnetic wave interference free space, thereby being capable of more meeting the use requirement.
Embodiment III: as shown in fig. 1, it can be explained on the basis of the first embodiment or the second embodiment that the radio frequency receiving chip includes a chip body, a ground pin (GND) of the chip body is connected with a ground pin, an antenna pin (ANT) of the chip body is connected with a capacitor C1 and is connected with an inductor L1, an inductor L2 and an inductor tri L3 in series, the capacitor C1 is connected with a ground wire end, the inductor di L2 is connected with a capacitor C5 in parallel, the inductor tri L3 is connected with a resistor R1, a capacitor tri C6 and a capacitor tetra C7, the capacitor tetra C7 is electrically connected with an amplifier, a power voltage pin (VCC) of the chip body is connected with a capacitor pentac 2, a capacitor hexa C3, a capacitor hepta 13 and an amplifier in series, an air pin (NC) of the chip body is connected with a power voltage pin, an output pin (RO) of the chip body is connected with a crystal resonator Y1, wherein the crystal resonator Y1 adopts 27.1412MHz, a digital output pin (DO) of the chip body is connected with a plug JP1, and the plug JP1 is connected with the amplifier.
Embodiment four: as shown in fig. 1, it can be explained on the basis of the third embodiment that the amplifier includes an LNA amplifier Q1 and an electronic component U2, a first pin of the connector JP1 is electrically connected with the electronic component U2, a second pin and a third pin of the connector JP1 are both electrically connected with a digital output pin (DO) of the chip body, a fourth pin and a fifth pin of the connector JP1 are both electrically connected with a ground terminal, the electronic component U2 is connected with a capacitor eight C4 in parallel, the electronic component U2 is connected with a capacitor nine C15 and a resistor two R5, the resistor two R5 is respectively connected with a capacitor ten C14, a capacitor seven 13 and a resistor three R4, the resistor three R4 is respectively connected with a resistor four R3, a capacitor eleven C9 and a resistor five R2, the resistor five R2 is connected with an inductor four L4 and a capacitor twelve C8 respectively, the inductor four L4 is connected with a first pin of the LNA amplifier Q1 and a capacitor four C7 respectively, the resistor four R3 is connected with a capacitor thirteen C10 and an inductor five L6 respectively, a second pin of the LNA amplifier Q1 is sequentially connected with an inductor six L5, an inductor seven L7, a capacitor fourteen C12 and an antenna in series, the antenna is connected with a grounding end, the inductor seven L7 is electrically connected with an inductor eight L8, the inductor eight L8 is connected with a grounding end, the capacitor fourteen C12 is electrically connected with an inductor nine L9, the inductor nine L9 is connected with a grounding end, and a third pin of the LNA amplifier Q1 is connected with the grounding end. It is also contemplated that SSP6206-33NR is employed for electronic component U2.
The utility model comprises an integrated chip U1, wherein the integrated chip U1 adopts a radio frequency receiving chip, the radio frequency receiving chip is electrically connected with an amplifier, the radio frequency receiving chip adopts a model of CMT2210LH, the receiving sensitivity of the radio frequency receiving chip through the CMT2210LH is effectively improved by 11dB gain (actually measured by a signal generator), and the amplifier adopts a model of BFP420H6 (low noise high gain LNA amplifier of Infei-Ling science and technology company), and the radio frequency receiving chip has the advantages of low price, low power consumption, wide input voltage and longer receiving distance, uses the same antenna for receiving comparison, effectively increases the distance by 2.5 times, and has the effects of higher sensitivity and anti-jitter.
The chip and the internal components of the element used in the document of the present utility model are all of the type conventional in the prior art, and the internal construction thereof belongs to the prior art structure, so that the worker can perform normal operation according to the prior art manual, and the circuit connection adopts the conventional connection mode in the prior art, and no specific description will be made here.
It should be noted that, although the foregoing embodiments have been described herein, the scope of the present utility model is not limited thereby. Therefore, based on the innovative concepts of the present utility model, alterations and modifications to the embodiments described herein, or equivalent structures or equivalent flow transformations made by the present description and drawings, apply the above technical solutions directly or indirectly to other relevant technical fields, all of which are included in the scope of protection of the present patent.

Claims (4)

1. The utility model provides a high sensitivity receiving module, includes integrated chip U1, its characterized in that: the integrated chip U1 adopts a radio frequency receiving chip, the radio frequency receiving chip is electrically connected with an amplifier, the radio frequency receiving chip adopts a CMT2210LH, the amplifier adopts a BFP420H6, the radio frequency receiving chip comprises a chip body, a ground wire pin of the chip body is connected with a ground wire end, an antenna pin of the chip body is connected with a capacitor C1 and is connected with an inductor L1, an inductor L2 and an inductor tri L3 in series, the capacitor C1 is connected with the ground wire end, the inductor L2 is connected with an inductor C5 in parallel, the inductor tri L3 is connected with a resistor R1, an inductor tri C6 and an inductor tri C7, the inductor tri C7 is electrically connected with the amplifier, a power supply voltage pin string of the chip body is connected with a capacitor five C2, an inductor six C3, an inductor seven 13 and the amplifier, an empty pin of the chip body is connected with a power supply voltage pin, an output pin of the chip body is connected with a crystal body Y1, and the output pin of the chip body is connected with a digital amplifier JP 1.
2. A high sensitivity receiving module according to claim 1, wherein: the crystal resonator Y1 adopts 27.1412MHz.
3. A high sensitivity receiving module according to claim 1, wherein: the amplifier includes LNA amplifier Q1 and electronic components U2, the first pin electricity of grafting ware JP1 is connected with electronic components U2, the second pin and the third pin electricity of grafting ware JP1 are all connected with the digital output pin of chip body, the fourth pin and the fifth pin electricity of grafting ware JP1 are all connected with the ground terminal, electronic components U2 parallel connection has electric capacity eighth C4, electronic components U2 is connected with electric capacity nine C15 and resistance two R5, resistance two R5 is connected with electric capacity ten C14 respectively, electric capacity seven 13 and resistance three R4 respectively, resistance three R4 is connected with electric capacity four R3, electric capacity eleven C9 and resistance five R2 respectively, resistance five R2 is connected with electric capacity four L4 and electric capacity twelve C8 respectively, electric capacity four L4 is connected with the first pin of amplifier Q1 and electric capacity four C7 respectively, resistance four R3 is connected with electric capacity thirteen C10 and electric capacity five L6 respectively, electric capacity seven L6 are connected with electric capacity seven L7, electric capacity seven L7 is connected with electric capacity nine L8, electric capacity seven L7 is connected with electric capacity seven L6, electric capacity seven connects L7 is connected with the electric capacity nine L8, electric capacity seven connects L7 is connected with the electric capacity nine L6 in proper order, electric capacity connects, and the electric capacity connects nine L8 is connected with the electric capacity nine L.
4. A high sensitivity receiving module according to claim 3, wherein: the electronic component U2 adopts SSP6206-33NR.
CN202320536003.1U 2023-03-20 2023-03-20 High-sensitivity receiving module Active CN219834123U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202320536003.1U CN219834123U (en) 2023-03-20 2023-03-20 High-sensitivity receiving module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202320536003.1U CN219834123U (en) 2023-03-20 2023-03-20 High-sensitivity receiving module

Publications (1)

Publication Number Publication Date
CN219834123U true CN219834123U (en) 2023-10-13

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202320536003.1U Active CN219834123U (en) 2023-03-20 2023-03-20 High-sensitivity receiving module

Country Status (1)

Country Link
CN (1) CN219834123U (en)

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