CN111313856A - Chip integrated with DC coupling capacitor - Google Patents
Chip integrated with DC coupling capacitor Download PDFInfo
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- CN111313856A CN111313856A CN202010233196.4A CN202010233196A CN111313856A CN 111313856 A CN111313856 A CN 111313856A CN 202010233196 A CN202010233196 A CN 202010233196A CN 111313856 A CN111313856 A CN 111313856A
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- capacitor
- matching unit
- chip
- impedance matching
- inductor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/38—Impedance-matching networks
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Abstract
The application discloses a chip integrated with a DC coupling capacitor. The chip is provided with a first end and a second end, the first end is electrically connected with one end of the first impedance matching unit, the other end of the first impedance matching unit is electrically connected with one end of the first capacitor, and the other end of the first capacitor is connected with the third end; the second end of the second impedance matching unit is electrically connected with one end of a second capacitor, the other end of the second matching unit is connected with one end of the second capacitor, and the other end of the second capacitor is connected with a fourth end; a first resistor and a second resistor which are connected in series are arranged between a first connecting point at which the other end of the first impedance matching unit is connected with one end of the first capacitor and a second connecting point at which the other end of the second impedance matching unit is connected with one end of the second capacitor, the connecting end of the first resistor and the second resistor is connected with one end of a third capacitor, and the other end of the third capacitor is electrically grounded. The chip integrates a DC coupling structure of the capacitor, so that the packaging size of the chip is small, the broadband impedance continuity is good, and the cost is low.
Description
Technical Field
The application relates to the technical field of chips, in particular to a chip integrated with a DC coupling capacitor.
Background
With the rapid development of optical communication, higher requirements including bandwidth, integration level, low power consumption and the like are put forward on high-speed electric chips. When the chip is applied, the internal and external DC voltages of the chip are not consistent, and at this time, the capacitor is usually used to block the internal and external DC voltages of the chip, as shown in fig. 1, an AC coupling architecture in which the blocking capacitor is configured outside the chip is used, the capacitor C _ PCB is configured on the PCB, the capacitance value of the capacitor C _ PCB is about 100nF, and the volume of the packaged chip is large.
Since the overall electrical chip is broadband, as the bandwidth increases, the capacitance (C _ pcb) must also be broadband, requiring multiple capacitors to be configured for impedance matching, resulting in further simultaneous poor device package size economy. Also the capacitance on the PCB board deteriorates the impedance continuity of the broadband system.
Therefore, a chip having a novel capacitive coupling structure is required.
Disclosure of Invention
To overcome the above-mentioned drawbacks, the present application aims to: the chip is small in packaging size, good in impedance continuity and low in cost when being applied to broadband (100 KHz-30 GHz) occasions.
In order to solve the technical problem, the following technical scheme is adopted in the application:
a chip integrated with a DC coupling capacitor, comprising: the chip has:
a first end and a second end, wherein,
the first end of the first impedance matching unit is electrically connected with one end of the first capacitor, the other end of the first impedance matching unit is electrically connected with one end of the first capacitor, and the other end of the first capacitor is connected with the third end;
the second end of the second impedance matching unit is electrically connected with one end of a second capacitor, the other end of the second matching unit is connected with one end of the second capacitor, and the other end of the second capacitor is connected with a fourth end;
a first resistor and a second resistor which are connected in series are arranged between a first connecting point at which the other end of the first impedance matching unit is connected with one end of the first capacitor and a second connecting point at which the other end of the second impedance matching unit is connected with one end of the second capacitor, the connecting end of the first resistor and the second resistor is connected with one end of a third capacitor, and the other end of the third capacitor is electrically grounded. Through the design, peripheral elements of the chip are reduced, the packaging size is further reduced, and when the chip operates in a broadband, the impedance continuity is good.
Preferably, the first end is electrically connected to the connection point of the first impedance matching unit by a fourth capacitor;
and the second end is electrically connected with the connecting point of the second impedance matching unit and is connected with a fifth capacitor.
Preferably, the first impedance matching unit and the second impedance matching unit have the same circuit topology.
Preferably, an inductor is disposed in the first impedance matching unit, and the inductance value of the inductor is 10 to 800 pH.
Preferably, the first impedance matching unit includes: the inductor comprises a first inductor, a second inductor and a sixth capacitor, wherein one end and a first end of the first inductor are connected with one end of the sixth capacitor, the other end of the sixth capacitor is connected with one end of the second inductor, the other end of the second inductor is connected with the first inductor, and the second inductor and the first inductor connecting end are electrically connected with one end B of the first capacitor.
Preferably, the first resistor R1 and the second resistor R2 are integrated on the chip, and the resistance values thereof are respectively between 30 Ω and 80 Ω.
Preferably, the resistances of the first resistor R1 and the second resistor R2 are respectively 50 Ω.
Advantageous effects
For the scheme among the prior art, the beneficial effect of this application:
according to the chip integrated with the DC coupling capacitor, the DC coupling capacitor of the differential structure is integrated on the chip, so that the chip does not need to be provided with a large-size broadband capacitor on a PCB, the packaging size of the chip is effectively reduced, and the continuity of broadband impedance is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a schematic topology of an AC coupling method in which a DC blocking capacitor is configured outside a conventional chip;
FIG. 2 is a schematic diagram of a DC topology with a differential structure for a chip according to an embodiment of the present application;
fig. 3 is a schematic diagram of a DC topology with a differential structure for a chip according to an embodiment of the present application;
fig. 4 is a schematic diagram of a DC topology with a differential structure for a chip according to another embodiment of the present application.
Detailed Description
The above-described scheme is further illustrated below with reference to specific examples. It should be understood that these examples are for illustrative purposes and are not intended to limit the scope of the present application. The conditions used in the examples may be further adjusted according to the conditions of the particular manufacturer, and the conditions not specified are generally the conditions in routine experiments. In the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.
The application provides a chip integrated with a DC coupling capacitor, and a DC coupling architecture of the capacitor is integrated on the chip. By the implementation structure, the chip can be matched with a high bandwidth range (range), and the capacitor is integrated on the chip, so that the packaging size of the chip (chip module) is reduced, and the requirement of chip miniaturization is met.
The chip of the integrated differential structure DC coupling capacitor proposed in the present application is described in detail below with reference to the accompanying drawings. The drawings include schematic drawings, and the scale and the aspect ratio of each component may be different from those of the actual components.
Referring to fig. 2, fig. 2 is a diagram of a chip according to the present application, which employs an integrated differential structure DC coupling capacitor.
The chip has a first terminal (Vip), a second terminal (Vin),
the first terminal (Vip) is electrically connected to one terminal of the first impedance matching unit 11a, the other terminal of the first impedance matching unit 11a is connected to one terminal of the first capacitor C1, and the other terminal of the first capacitor C1 is connected to the third terminal (Voutp);
the second end (Vin) is electrically connected to one end of the impedance second matching unit 11b, the other end of the second matching unit 11b is connected to one end of the second capacitor C2, the other end of the second capacitor C2 is connected to the fourth end (Voutn), a first connection point between the other end of the first impedance matching unit 11a and one end of the first capacitor C1 and a second connection point between the other end of the second impedance matching unit 11b and one end of the second capacitor C2 are configured with a first resistor R1 and a second resistor R2 which are connected in series, a connection end of the first resistor R1 and the second resistor R2 is connected to one end of the third capacitor C3, and the other end of the third capacitor C3 is electrically grounded. The first terminal (Vip) is electrically connected to the connection point of the first impedance matching unit 11a through the fourth capacitor C4, and the second terminal (Vin) is electrically connected to the connection point of the second impedance matching unit 11b through the fifth capacitor C5. The first impedance matching unit 11a and the second impedance matching unit 11b have the same circuit, and the first impedance matching unit 11a is taken as an example for description, and an inductor L _ eq is arranged in the first impedance matching unit 11a, and the inductance value range thereof is between 10pH and 800 pH. The devices described above are all integrated On-chip i.e. used (On-chip integrated circuit devices), without the need for PCB devices.
For this reason, the first impedance matching unit/the second impedance matching unit is further improved, as shown in fig. 3, which is a topological schematic diagram of the chip differential structure DC coupling proposed in the present application;
in this embodiment, the first impedance matching unit and the second impedance matching unit have the same structure, and the first impedance matching unit is taken as an example for description.
The first impedance matching unit includes: a first inductor L1, a second inductor Lp, a (sixth) capacitor Cp,
one end of the sixth capacitor Cp is connected to one end of the first inductor L1 and the first end (Vip) (a), the other end of the sixth capacitor Cp is connected to one end of the second inductor Lp, the other end of the second inductor Lp is connected to the first inductor L1, and the connection end between the second inductor Lp and the first inductor L1 is electrically connected to one end (B) of the first capacitor C1. By such a design, the first inductor L1 is connected in parallel with the capacitor Cp and the second inductor Lp, thereby extending the flatness of the high-frequency impedance. Isolation of the DC level is achieved by the on-chip capacitance C1/C2. R1/R2 is an on-chip load, the resistance value is about 30-80 omega, the typical value is 50 ohm, and the combination of R1/R2 and C3 realizes a relatively low-frequency cut-off frequency (less than 100K Hz); by the virtual ground effect of C3 (no dc path to ground), power consumption of the rf characteristic impedance linked to ground is saved. In addition, the isolation of the DC level inside/outside the chip is realized through the first capacitor C1/the second capacitor C2 inside the chip.
In an embodiment, the first impedance matching unit may adjust a connection sequence of the second inductor Lp and the (sixth) capacitor Cp as shown in fig. 4, in which one end of the second inductor Lp is electrically connected to one end of the first inductor L1. In the embodiment of fig. 3, one end of the capacitor Cp is electrically connected to one end of the first inductor L1. Thus, when the impedance continuity is good in high frequency application, the cost of the chip (chip module) is low.
In an embodiment, the first impedance matching unit is configured as a transmission line. Thus being directly connected by a transmission line.
It should be noted that, in the present application, the terms "upper", "lower", "inner", "middle", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings. These terms are used primarily to better describe the present application and its embodiments, and are not used to limit the indicated devices, elements or components to a particular orientation or to be constructed and operated in a particular orientation. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
The above embodiments are merely illustrative of the technical concepts and features of the present application, and the purpose of the embodiments is to enable those skilled in the art to understand the content of the present application and implement the present application, and not to limit the protection scope of the present application. All equivalent changes and modifications made according to the spirit of the present application are intended to be covered by the scope of the present application.
Claims (7)
1. A chip integrated with a DC coupling capacitor, comprising: the chip has:
a first end and a second end, wherein,
the first end of the first impedance matching unit is electrically connected with one end of the first capacitor, the other end of the first impedance matching unit is electrically connected with one end of the first capacitor, and the other end of the first capacitor is connected with the third end;
the second end of the second impedance matching unit is electrically connected with one end of a second capacitor, the other end of the second matching unit is connected with one end of the second capacitor, and the other end of the second capacitor is connected with a fourth end;
a first resistor and a second resistor which are connected in series are arranged between a first connecting point at which the other end of the first impedance matching unit is connected with one end of the first capacitor and a second connecting point at which the other end of the second impedance matching unit is connected with one end of the second capacitor, the connecting end of the first resistor and the second resistor is connected with one end of a third capacitor, and the other end of the third capacitor is electrically grounded.
2. The integrated DC coupling capacitance chip of claim 1, wherein:
the first end is electrically connected with a connection point of the first impedance matching unit and a fourth capacitor;
and the second end is electrically connected with the connecting point of the second impedance matching unit and is connected with a fifth capacitor.
3. The integrated DC coupling capacitance chip of claim 1, wherein: the circuit topology of the first impedance matching unit is the same as that of the second impedance matching unit.
4. The integrated DC coupling capacitance chip of claim 1, wherein:
an inductor is arranged in the first impedance matching unit, and the inductance value of the inductor is between 10 and 800 pH.
5. The integrated DC coupling capacitance chip of claim 1, wherein:
the first impedance matching unit includes: a first inductor, a second inductor and a sixth capacitor,
one end of the sixth capacitor is connected with one end of the first inductor and the first end A, the other end of the sixth capacitor is connected with one end of the second inductor, the other end of the second inductor is connected with the first inductor, and the connecting end of the second inductor and the first inductor is electrically connected with one end B of the first capacitor.
6. The integrated DC coupling capacitance chip of claim 1, wherein:
the first resistor R1 and the second resistor R2 are integrated on the chip, and the resistance values of the first resistor R1 and the second resistor R2 are respectively 30-80 omega.
7. The integrated DC coupling capacitance chip of claim 6, wherein:
the resistances of the first resistor R1 and the second resistor R2 are respectively 50 Ω.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010233196.4A CN111313856A (en) | 2020-03-29 | 2020-03-29 | Chip integrated with DC coupling capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010233196.4A CN111313856A (en) | 2020-03-29 | 2020-03-29 | Chip integrated with DC coupling capacitor |
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| Publication Number | Publication Date |
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| CN111313856A true CN111313856A (en) | 2020-06-19 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202010233196.4A Pending CN111313856A (en) | 2020-03-29 | 2020-03-29 | Chip integrated with DC coupling capacitor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114244308A (en) * | 2021-12-27 | 2022-03-25 | 苏州芈图光电技术有限公司 | kHz-100 GHz on-chip integrated capacitor DC coupling circuit |
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2020
- 2020-03-29 CN CN202010233196.4A patent/CN111313856A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114244308A (en) * | 2021-12-27 | 2022-03-25 | 苏州芈图光电技术有限公司 | kHz-100 GHz on-chip integrated capacitor DC coupling circuit |
| CN114244308B (en) * | 2021-12-27 | 2022-12-16 | 苏州芈图光电技术有限公司 | 100 kHz-100 GHz on-chip integrated capacitor DC coupling circuit |
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