CN209184569U - A kind of novel medium ceramics low-pass filter - Google Patents
A kind of novel medium ceramics low-pass filter Download PDFInfo
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- CN209184569U CN209184569U CN201822072125.1U CN201822072125U CN209184569U CN 209184569 U CN209184569 U CN 209184569U CN 201822072125 U CN201822072125 U CN 201822072125U CN 209184569 U CN209184569 U CN 209184569U
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- 239000000919 ceramic Substances 0.000 title claims abstract description 37
- 239000003990 capacitor Substances 0.000 claims abstract description 164
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 239000011159 matrix material Substances 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 152
- 239000004020 conductor Substances 0.000 claims description 52
- 239000002184 metal Substances 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 230000005611 electricity Effects 0.000 claims description 7
- 238000009826 distribution Methods 0.000 claims description 6
- 238000007639 printing Methods 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 abstract description 20
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000008878 coupling Effects 0.000 abstract description 2
- 238000010168 coupling process Methods 0.000 abstract description 2
- 238000005859 coupling reaction Methods 0.000 abstract description 2
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 15
- 238000005516 engineering process Methods 0.000 description 2
- 230000005764 inhibitory process Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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Abstract
A kind of novel medium ceramics low-pass filter, is related to media ceramic low-pass filter, including matrix, and intrinsic silicon is equipped with five layers of circuit layer；The fourth order low-pass filter circuit that equivalent circuit on circuit layer is constituted, symmetrical structure, and a transmission zero is generated in high band by inductance L1 and capacitor C2 parallel resonance, another transmission zero is generated in high band by inductance L2 and capacitor C7 parallel resonance, transmission line SL1 and capacitor C4, transmission line SL2 and capacitor C5 difference parallel resonance generates zero point in high band, four zero points of high-end formation reach high inhibitory effect, by adjusting transmission line SL1 and capacitor C4, the parallel resonator that transmission line SL2 and capacitor C5 is constituted can control the 3dB cutoff frequency point of low-pass filter, it adjusts transmission line SL1 and the transmission line SL2 degree of coupling and capacitor C9 can control the steepness of low-pass filter.Have many advantages, such as low-loss, high reliability, low cost and is suitable for producing on a large scale.
Description
Technical field
The utility model relates to arrive media ceramic low-pass filter, more particularly to it is applied to satellite television tuner LNB
The media ceramic low-pass filter of (Low Noise Block).
Background technique
Low-temperature co-fired ceramics (Low Temperature Co-fired Ceramic, LTCC) technology in electronic component and
Encapsulation field has unique advantage, because its high reliability, filter with low insertion loss, it is high inhibit, it is small in size, light-weight, be easily integrated, it is low at
Originally, it is suitble to the advantages that large-scale production, is widely used in the fields such as communication, automobile and medical instrument.
With the raising of people's life consumption level, the demand to live telecast is more and more, it is desirable that also higher and higher.
For LNB tuner as key component indispensable in satellite TV reception module, the influence to signal quality is most important, and
Filter is then particularly critical in LNB tuner.
Summary of the invention
In conclusion the utility model aim is to solve to lack in existing LNB tuner with low-temperature co-fired ceramics skill
The technical issues of high performance requirements media ceramic low-pass filter based on art, and propose a kind of novel medium ceramics low pass filtered
Wave device.
To solve the technical issues of the utility model is proposed, the technical solution of use are as follows:
A kind of novel medium ceramics low-pass filter, including matrix, base bottom are equipped with first port P1, second port
P2 and third port P3, intrinsic silicon are equipped with circuit layer；It is characterized by: the circuit layer one of the intrinsic silicon shares five
Layer, is respectively as follows:
First layer is printed with three pieces of mutually insulated metal flat conductors on ceramic dielectric substrate, it is flat to be respectively as follows: the 30th
Face conductor (30), the 33rd planar conductor (33) and the first planar conductor (1)；30th planar conductor (30) and the first plane
Conductor (1) is respectively distributed to the two sides of the 33rd planar conductor (33)；Three pieces of mutually insulated metal flat conductors respectively correspond
First port P1, second port P2 and third port P3；Wherein, the 30th planar conductor (30) is connected with the 26th column
(26), the first planar conductor (1) is connected with second point column (2), and the 33rd planar conductor (33) is connected with the 32nd column
(32), the 34th column (34) and the 35th column (35)；
The second layer is printed with one piece of insulated metal planar conductor on ceramic dielectric substrate, the insulated metal planar conductor
Include: third capacitor substrate (3), the 25th capacitor substrate (25), the 6th capacitor substrate (6) and the 31st capacitor substrate
(31)；6th capacitor substrate (6) is overlapped for one side with the 31st capacitor substrate (31) and constitutes figure of eight structure, and the 25th
Capacitor substrate (25) and third capacitor substrate (3) are distributed in the two sides of figure of eight structure；6th capacitor substrate (6) and the 30th
Public the first public capacitance substrate (6c) connection of one capacitor substrate (31) the 32nd column (32), the 34th point
Column (34) and the 35th column (35)；
Third layer is printed with four pieces of metal flat conductors on ceramic dielectric substrate, be respectively as follows: the 4th capacitor substrate (4),
7th capacitor substrate (7), the 24th capacitor substrate (24) and the 28th capacitor substrate (28)；7th capacitor substrate (7) with
28th capacitor substrate (28) Relative distribution, the 4th capacitor substrate (4) and the 24th capacitor substrate (24) Relative distribution；The
One end of four capacitor substrates (4) is connected with the 8th column (8), the opposite other end connection second point column (2)；7th electricity
Hold substrate (7) one end and be connected with the 23rd column (23), the other end is connected with the ten three column (13)；24th capacitor base
One end of piece (24) is connected with the ten seven column (17), and the other end is connected with the 26th column (26)；28th
Capacitor substrate (28) is connected with the 21st column (21) and the 29th column (29)；
4th layer, the metal flat conductor there are three mutually insulated, two of them metal are printed on ceramic dielectric substrate
Planar conductor is respectively the 5th capacitor substrate (5) and the 22nd capacitor substrate (22), and a remaining metal flat conductor is
Assembly comprising the 9th capacitor substrate (9), the tenth capacitor substrate (10) and the 27th capacitor substrate (27)；5th capacitor base
Piece (5) and the 22nd capacitor substrate (22) are distributed in the two sides of assembly；Tenth capacitor substrate (10) is distributed in the 9th capacitor
Between substrate (9) and the 27th capacitor substrate (27)；One end of 5th capacitor substrate (5) is connected with the ten one column (11),
The other end connects the 29th column (29)；The 23rd point described in one end connection of 22nd capacitor substrate (22)
Column (23), the other end are connected with the ten nine column (19)；9th capacitor substrate (9) is connected with the ten five column (15)；20th
Seven capacitor substrates (27) are connected with the 20th column (20)；
Layer 5, there are four mutually insulated wire coils, respectively the 12nd inductor wire for printing on ceramic dielectric substrate
Enclose (12), the 16th inductance coil (16), the 18th inductance coil (18) and the 14th inductance coil (14)；12nd inductor wire
The both ends of circle (12) are separately connected the ten one column (11) and the 8th column (8)；The both ends of 16th inductance coil (16)
It is separately connected the ten five column (15) and the ten three column (13)；The both ends of 18th inductance coil (18) are separately connected institute
State the ten seven column (17) and the ten nine column (19)；The both ends of 14th inductance coil (14) are separately connected at described 20th point
Column (20) and the 21st column (21).
12nd inductance coil (12) and the 18th inductance coil (18) are symmetrically distributed in ceramic dielectric substrate or so two
Side, the 16th inductance coil (16) and the 14th inductance coil (14) are symmetrically distributed in anteroposterior position in the middle part of ceramic dielectric substrate
It sets, the 16th inductance coil (16) and the 14th inductance coil (14) are the opposite U-shaped structure of opening direction.
The beneficial effect of the utility model are as follows: the utility model is based on LTCC Technology, using half collection Headquarters of the General Staff
The high performance requirements of novel medium ceramics low-pass filter are realized in exponential model design.The utility model is effectively realized with outer high suppression
System, has many advantages, such as low-loss, high reliability, low cost and is suitable for producing on a large scale, be in addition also adapted to new electronics
Miniaturization of components development trend.
Detailed description of the invention
Fig. 1 is the schematic equivalent circuit of the utility model；
Fig. 2 is the utility model surface structure stereoscopic schematic diagram；
Fig. 3 is the utility model outer bottom port schematic diagram；
Fig. 4 is the utility model schematic diagram of internal structure；
Fig. 5 is the utility model first layer circuit layer planar structure schematic diagram；
Fig. 6 puts column between the utility model first layer and the second layer and connects planar structure schematic diagram；
Fig. 7 is the utility model second layer circuit planes structural schematic diagram；
Fig. 8 puts column between the utility model second layer and third layer and connects planar structure schematic diagram；
Fig. 9 is the utility model third layer circuit planes structural schematic diagram；
Figure 10 puts column between the utility model third layer and the 4th layer and connects planar structure schematic diagram
Figure 11 is the 4th layer of circuit planes structural schematic diagram of the utility model；
Figure 12 is the 4th layer of the utility model and puts column connection planar structure schematic diagram between layer 5；
Figure 13 is the utility model layer 5 circuit planes structural schematic diagram.
Specific embodiment
The structure of the utility model is made below in conjunction with attached drawing and the utility model preferred embodiment further
Ground explanation.
Referring to figs. 1 to shown in Fig. 3, novel medium ceramics low-pass filter disclosed by the utility model, including matrix, base
Body bottom is equipped with first port P1, second port P2 and third port P3, and intrinsic silicon is equipped with circuit layer；On circuit layer etc.
Imitate circuit diagram it is as shown in fig. 1, by inductance L1, inductance L2, transmission line SL1, transmission line SL2, capacitor C1, capacitor C2, capacitor C3,
The fourth order low-pass filter circuit that capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8, capacitor C9 are constituted, it is symmetrical
Structure, and a transmission zero is generated in high band by inductance L1 and capacitor C2 parallel resonance, pass through inductance L2 and capacitor C7
Parallel resonance generates another transmission zero in high band, at the same time transmission line SL1 and capacitor C4, transmission line SL2 and electricity
Hold C5 difference parallel resonance and generate zero point in high band, thus four zero points of the high-end formation of low-pass filter reach high inhibition effect
Fruit.And it can control low pass by adjusting the parallel resonator that transmission line SL1 and capacitor C4, transmission line SL2 and capacitor C5 are constituted
The 3dB cutoff frequency point of filter, in addition adjusting transmission line SL1 can control low with the transmission line SL2 degree of coupling and capacitor C9
The steepness of bandpass filter.It is wherein 1. input/output end port, 2. first port P1 in corresponding diagram 3 is then input/output end
Mouthful, third port P3 in corresponding diagram 3, second port P2 are grounding ports.
Referring to shown in Fig. 3 to Figure 13, intrinsic silicon is equipped with circuit layer one and shares five layers, is respectively as follows:
First layer is printed with three pieces of mutually insulated metal flat conductors on ceramic dielectric substrate, it is flat to be respectively as follows: the 30th
Face conductor 30, the 33rd planar conductor 33 and the first planar conductor 1；30th planar conductor 30 and the first planar conductor 1 divide
It is not distributed in the two sides of the 33rd planar conductor 33；Three pieces of mutually insulated metal flat conductors respectively correspond first port P1,
Second port P2 and third port P3；Wherein, the 30th planar conductor 30 is connected with the 26th column 26, the first planar conductor
1, which is connected with the 2, the 33rd planar conductor 33 of second point column, is connected with the 32nd column column 34 and thirds at 32, the 34th
Ten five columns 35；
The second layer is printed with one piece of insulated metal planar conductor on ceramic dielectric substrate, the insulated metal planar conductor
Include: third capacitor substrate 3, the 25th capacitor substrate 25, the 6th capacitor substrate 6 and the 31st capacitor substrate 31；The
Six capacitor substrates 6 are that one side is overlapped composition figure of eight structure, 25 He of the 25th capacitor substrate with the 31st capacitor substrate 31
Third capacitor substrate 3 is distributed in the two sides of figure of eight structure；6th capacitor substrate 6 and the 31st capacitor substrate 31 are public
First public capacitance substrate 6c connection described the 32nd column 32, the 34th columns 34 and the 35th columns 35；
Third layer is printed with four pieces of metal flat conductors on ceramic dielectric substrate, is respectively as follows: the 4th capacitor substrate 4,
Seven capacitor substrates 7, the 24th capacitor substrate 24 and the 28th capacitor substrate 28；The 7 and the 28th electricity of 7th capacitor substrate
Hold 28 Relative distribution of substrate, the 4th capacitor substrate 4 and 24 Relative distribution of the 24th capacitor substrate；The one of 4th capacitor substrate 4
End 4a is connected with the 8th column 8, the opposite other end 4b connection second point column 2；One end 7a of 7th capacitor substrate 7 connects
It is connected to the 23rd column 23, other end 7b is connected with the ten three column 13；One end 24a connection of 24th capacitor substrate 24
There is the ten seven column 17, other end 24b is connected with the 26th column 26；28th capacitor substrate, 28 right side upper end
28a and right side lower end 28b are connected with the 21st column 21 and the 29th column 29；
4th layer, the metal flat conductor there are three mutually insulated, two of them metal are printed on ceramic dielectric substrate
Planar conductor is respectively the 5th capacitor substrate 5 and the 22nd capacitor substrate 22, a remaining metal flat conductor be comprising
The assembly of 9th capacitor substrate 9, the tenth capacitor substrate 10 and the 27th capacitor substrate 27；5th capacitor substrate 5 and second
12 capacitor substrates 22 are distributed in the two sides of assembly；Tenth capacitor substrate 10 is distributed in the 9th capacitor substrate 9 and the 27th
Between capacitor substrate 27；One end of 5th capacitor substrate 5 is connected with the ten one column 11, and the other end connects at described 29th point
Column 29；One end connection of 22nd capacitor substrate 22 the 23rd column 23, the other end are connected with the ten nine column
19；9th capacitor substrate 9 is connected with the ten five column 15；27th capacitor substrate 27 is connected with the 20th column 20；
Layer 5, there are four mutually insulated wire coils, respectively the 12nd inductor wire for printing on ceramic dielectric substrate
Enclose the 12, the 16th inductance coil 16, the 18th inductance coil 18 and the 14th inductance coil 14；12nd inductance coil 12 and
18 inductance coils 18 are symmetrically distributed at left and right sides of ceramic dielectric substrate, the 16th inductance coil 16 and the 14th inductor wire
Circle 14 is symmetrically distributed in front-rear position in the middle part of ceramic dielectric substrate, and the 16th inductance coil 16 and the 14th inductance coil 14 are
The opposite U-shaped structure of opening direction；
Head and the tail both ends 12a, 12b of 12nd inductance coil 12 are separately connected the ten one column 11 and the 8th column 8；
Head and the tail both ends 16a, 16b of 16th inductance coil 16 are separately connected the ten five column 15 and the ten three column 13；Tenth
Head and the tail both ends 18a, 18b of eight inductance coils 18 are separately connected the ten seven column 17 and the ten nine column 19；14th electricity
Head and the tail both ends 14a, 14b of sense coil 14 are separately connected the 20th column 20 and the 21st column 21.
The corresponding relationship that intrinsic silicon is equipped with each component and each element in equivalent circuit in circuit layer is respectively as follows: the first plane
Conductor 1 is low-pass filter input/output port P3, and third capacitor substrate 3 is a wherein capacitor substrate of capacitor C8, the 4th electricity
Holding substrate 4 is capacitor C7 and capacitor C8 public capacitance substrate, and the 5th capacitor substrate 5 is a wherein capacitor substrate of capacitor C7, the
Six capacitor substrates 6 are a wherein capacitor substrate of capacitor C3, and the 7th capacitor substrate 7 is capacitor C3 and capacitor C4 public capacitance base
Piece, the 9th capacitor substrate 9 are a capacitor C4 wherein capacitor substrate, and the tenth capacitor substrate 10 is a wherein capacitor base of capacitor C9
Piece, the 12nd inductance coil 12 are the inductance wire coil of inductance L2, and the 14th inductance coil 14 is metal transmission line SL1, the
16 inductance coils 16 be metal transmission line SL1, the 18th inductance coil 18 be inductance L1 inductance wire coil, the 20th
Two capacitor substrates 22 are a wherein capacitor substrate of capacitor C5, and the 24th capacitor substrate 24 is capacitor C1 and capacitor C2 common electrical
Hold substrate；25th capacitor substrate 25 is a wherein capacitor substrate of capacitor C1, and the 27th capacitor substrate 27 is capacitor C5
A wherein capacitor substrate；28th capacitor substrate 28 is the public capacitance substrate of capacitor C5 and capacitor C6, the 30th plane
Conductor 30 is low-pass filter input/output port P1；31st capacitor substrate 31 is a wherein capacitor substrate of capacitor C6,
33rd planar conductor 33 is low-pass filter ground plane port P2.
The utility model is integrated into identity element using LTCC forming technique, then using 900 DEG C it is low temperature co-fired form,
It effectively realizes with outer high inhibition, has many advantages, such as low-loss, high reliability, low cost and be suitable for producing on a large scale, separately
It has been also adapted to new electronic component miniaturization trend outside.
Claims (2)
1. a kind of novel medium ceramics low-pass filter, including matrix, base bottom is equipped with first port P1, second port P2
With third port P3, intrinsic silicon is equipped with circuit layer；It is characterized by: the circuit layer one of the intrinsic silicon shares five layers,
It is respectively as follows:
First layer is printed with three pieces of mutually insulated metal flat conductors on ceramic dielectric substrate, is respectively as follows: the 30th plane and leads
Body (30), the 33rd planar conductor (33) and the first planar conductor (1)；30th planar conductor (30) and the first planar conductor
(1) two sides of the 33rd planar conductor (33) are respectively distributed to；Three pieces of mutually insulated metal flat conductors respectively correspond first
Port P1, second port P2 and third port P3；Wherein, the 30th planar conductor (30) is connected with the 26th column (26),
First planar conductor (1) is connected with second point column (2), the 33rd planar conductor (33) be connected with the 32nd column (32),
34th column (34) and the 35th column (35)；
The second layer is printed with one piece of insulated metal planar conductor on ceramic dielectric substrate, which includes
Have: third capacitor substrate (3), the 25th capacitor substrate (25), the 6th capacitor substrate (6) and the 31st capacitor substrate
(31)；6th capacitor substrate (6) is overlapped for one side with the 31st capacitor substrate (31) and constitutes figure of eight structure, and the 25th
Capacitor substrate (25) and third capacitor substrate (3) are distributed in the two sides of figure of eight structure；6th capacitor substrate (6) and the 30th
Public the first public capacitance substrate (6c) connection of one capacitor substrate (31) the 32nd column (32), the 34th point
Column (34) and the 35th column (35)；
Third layer is printed with four pieces of metal flat conductors on ceramic dielectric substrate, is respectively as follows: the 4th capacitor substrate (4), the 7th
Capacitor substrate (7), the 24th capacitor substrate (24) and the 28th capacitor substrate (28)；7th capacitor substrate (7) and second
18 capacitor substrate (28) Relative distributions, the 4th capacitor substrate (4) and the 24th capacitor substrate (24) Relative distribution；4th electricity
The one end for holding substrate (4) is connected with the 8th column (8), the opposite other end connection second point column (2)；7th capacitor base
Piece (7) one end is connected with the 23rd column (23), and the other end is connected with the ten three column (13)；24th capacitor substrate
(24) one end is connected with the ten seven column (17), and the other end is connected with the 26th column (26)；28th electricity
Hold substrate (28) and is connected with the 21st column (21) and the 29th column (29)；
4th layer, the metal flat conductor there are three mutually insulated, two of them metal flat are printed on ceramic dielectric substrate
Conductor is respectively the 5th capacitor substrate (5) and the 22nd capacitor substrate (22), a remaining metal flat conductor be comprising
The assembly of 9th capacitor substrate (9), the tenth capacitor substrate (10) and the 27th capacitor substrate (27)；5th capacitor substrate
(5) and the 22nd capacitor substrate (22) is distributed in the two sides of assembly；Tenth capacitor substrate (10) is distributed in the 9th capacitor base
Between piece (9) and the 27th capacitor substrate (27)；One end of 5th capacitor substrate (5) is connected with the ten one column (11), separately
One end connects the 29th column (29)；One end connection of 22nd capacitor substrate (22) the 23rd column
(23), the other end is connected with the ten nine column (19)；9th capacitor substrate (9) is connected with the ten five column (15)；27th
Capacitor substrate (27) is connected with the 20th column (20)；
Layer 5, there are four mutually insulated wire coils, respectively the 12nd inductance coil for printing on ceramic dielectric substrate
(12), the 16th inductance coil (16), the 18th inductance coil (18) and the 14th inductance coil (14)；12nd inductance coil
(12) both ends are separately connected the ten one column (11) and the 8th column (8)；The both ends of 16th inductance coil (16) point
The ten five column (15) and the ten three column (13) are not connected；The both ends of 18th inductance coil (18) are separately connected described
Ten seven column (17) and the ten nine column (19)；The both ends of 14th inductance coil (14) are separately connected the 20th column
(20) and the 21st column (21).
2. a kind of novel medium ceramics low-pass filter according to claim 1, it is characterised in that: the 12nd inductance coil
(12) be symmetrically distributed at left and right sides of ceramic dielectric substrate with the 18th inductance coil (18), the 16th inductance coil (16) and
14th inductance coil (14) is symmetrically distributed in front-rear position in the middle part of ceramic dielectric substrate, the 16th inductance coil (16) and the
14 inductance coils (14) are the opposite U-shaped structure of opening direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822072125.1U CN209184569U (en) | 2018-12-11 | 2018-12-11 | A kind of novel medium ceramics low-pass filter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822072125.1U CN209184569U (en) | 2018-12-11 | 2018-12-11 | A kind of novel medium ceramics low-pass filter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209184569U true CN209184569U (en) | 2019-07-30 |
Family
ID=67376325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201822072125.1U Withdrawn - After Issue CN209184569U (en) | 2018-12-11 | 2018-12-11 | A kind of novel medium ceramics low-pass filter |
Country Status (1)
| Country | Link |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109286383A (en) * | 2018-12-11 | 2019-01-29 | 深圳市麦捷微电子科技股份有限公司 | A kind of novel medium ceramics low-pass filter |
| CN111010106A (en) * | 2019-12-20 | 2020-04-14 | 深圳市麦捷微电子科技股份有限公司 | Miniaturized lamination formula low pass filter |
-
2018
- 2018-12-11 CN CN201822072125.1U patent/CN209184569U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109286383A (en) * | 2018-12-11 | 2019-01-29 | 深圳市麦捷微电子科技股份有限公司 | A kind of novel medium ceramics low-pass filter |
| CN109286383B (en) * | 2018-12-11 | 2023-11-17 | 深圳市麦捷微电子科技股份有限公司 | Novel dielectric ceramic low-pass filter |
| CN111010106A (en) * | 2019-12-20 | 2020-04-14 | 深圳市麦捷微电子科技股份有限公司 | Miniaturized lamination formula low pass filter |
| CN111010106B (en) * | 2019-12-20 | 2023-02-28 | 深圳市麦捷微电子科技股份有限公司 | Miniaturized lamination formula low pass filter |
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