CN117200729A - Ultra-small band-pass filter for 5G module based on LTCC technology - Google Patents
Ultra-small band-pass filter for 5G module based on LTCC technology Download PDFInfo
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Abstract
A band-pass filter for a miniature 5G module based on LTCC technology comprises a high-dielectric low-loss ceramic substrate, a bonding pad electrode arranged at the bottom of the substrate and a circuit layer arranged inside the substrate, wherein the circuit layer inside the substrate is of a laminated structure. The filter is manufactured by adopting an LTCC technology and then co-firing at a low temperature of about 900 ℃, and the size of the finished product is 1.0mm*0.5mm*0.39mm Max. The invention is based on LTCC technology, adopts a four-order coupling model design, and the coupling transmission line improves the Q value of the transmission line through a double-layer winding technology and the special electrical performance requirement of the ultra-small band-pass filter for 5G module based on the LTCC technology is realized by high dielectric and low-loss materials. The invention effectively realizes the characteristics of the band-pass filter for the 5G module, and has the advantages of low loss, high inhibition, high reliability, small size suitable for modularization, low cost, suitability for large-scale production and the like.
Description
Technical Field
The invention discloses a filter, in particular to a band-pass filter for a microminiature 5G module based on LTCC technology, which is mainly applied to various 5G mobile communication equipment.
Background
The low temperature co-fired Ceramic (LTCC) is a high density packaging technology with a wide application range, and has become the preferred mode for integrating and modularizing electronic components due to its excellent electronic, mechanical and thermal properties. Radio frequency microwave elements and modules designed and produced based on LTCC technology include balun filters, multiplexers, diplexers, antennas, couplers, balun, receive front-end modules, antenna switch modules, etc., which have many advantages in terms of wiring linewidth and spacing, impedance matching, diversity of designs, high frequency performance, etc., in addition to advantages in terms of cost and integrated packaging, etc. As modern electronic devices continue to evolve toward miniaturization and high frequency, they have been largely utilized in miniaturized electronic devices.
In the field of mobile communication, with the development of 5G technology, the radio frequency front end of a 5G mobile terminal is more and more crowded and complex, and the modularity becomes an ideal design scheme of the 5G radio frequency front end, that is, separate devices such as a radio frequency switch, a low noise amplifier, a filter, a power amplifier and the like are integrated into a single module, so that the integration level and the performance are improved, and the volume is miniaturized. The modular design with high integration saves the areas of peripheral devices and the layout plates, reduces the volume and the size, improves the performance, reduces the cost and shortens the engineering period of the terminal product. The ultra-small filter based on LTCC becomes the first choice of the 5G module.
Disclosure of Invention
Aiming at the problem that the radio frequency front end of the 5G mobile terminal in the prior art is crowded and complex more and more, the invention provides a band-pass filter for a miniature 5G module based on the LTCC technology, which comprises a high dielectric low-loss ceramic substrate, a bonding pad electrode arranged at the bottom of the substrate and a circuit layer arranged in the substrate, wherein the circuit layer in the substrate is of a laminated structure.
The technical scheme adopted for solving the technical problems is as follows: a band-pass filter for ultra-small 5G module based on LTCC technology comprises a circuit structure layer sequentially arranged inside a ceramic matrix from bottom to top,
a first layer, a first input/output port, a second input/output port and a grounding electrode printed on the ceramic dielectric substrate;
the second layer is printed with three mutually independent metal plane conductors which are a main capacitor substrate, a first connecting through hole and a third connecting through hole respectively, wherein the main capacitor substrate is connected with the first grounding electrode through the second connecting through hole, and the first connecting through hole and the third connecting through hole are connected with the first input/output port and the second output/input port respectively;
the third layer is formed by printing seven mutually independent metal plane conductors on the ceramic dielectric substrate, wherein the seven mutually independent metal plane conductors are respectively a first capacitor substrate, a second capacitor substrate, a third capacitor substrate, a fourth connecting through hole, a fifth connecting through hole and a sixth connecting through hole;
a fourth layer, wherein seven mutually independent metal plane conductors are printed on the ceramic dielectric substrate, and are respectively a fifth capacitor substrate, a sixth capacitor substrate, a fourth connecting through hole, a fifth connecting through hole, a sixth connecting through hole, a seventh connecting through hole and an eighth connecting through hole, wherein a third internal connecting endpoint is arranged in connection with the fifth capacitor substrate, the fifth capacitor substrate is connected with the first connecting through hole through the third internal connecting endpoint, a fourth internal connecting endpoint is arranged in connection with the sixth capacitor substrate, and the sixth capacitor substrate is connected with the third connecting through hole through the fourth internal connecting endpoint;
the fifth layer is formed by printing eight mutually independent metal plane conductors on the ceramic dielectric substrate, namely a capacitor substrate, a first connecting through hole, a third connecting through hole, a fourth connecting through hole, a fifth connecting through hole, a sixth connecting through hole, a seventh connecting through hole and an eighth connecting through hole;
a sixth layer, wherein seven mutually independent metal plane conductors are printed on the ceramic dielectric substrate, and are respectively a first metal inductance coil, a second metal inductance coil, a first connecting through hole, a third connecting through hole, a fifth connecting through hole, a seventh connecting through hole and an eighth connecting through hole, wherein a fifth internal connecting endpoint and a sixth internal connecting endpoint are connected with the first metal inductance coil, the fifth internal connecting endpoint and the sixth internal connecting endpoint jointly form a U-shaped structure, the first metal inductance coil is connected with the sixth connecting through hole through the fifth internal connecting endpoint, and the first metal inductance coil is connected with the tenth connecting through hole through the sixth internal connecting endpoint; the second metal inductance coil, the seventh internal connection terminal and the eighth internal connection terminal are connected with the fourth connection through hole through the seventh internal connection terminal, and the second metal inductance coil is connected with the ninth connection through hole through the internal connection terminal;
a seventh layer having the same structure as the sixth layer;
an eighth layer, wherein three mutually independent metal plane conductors, namely a third metal inductance coil, a fourth metal inductance coil and a fifth metal inductance coil, are printed on the ceramic dielectric substrate, wherein a ninth internal connection terminal and a tenth internal connection terminal are connected with the third metal inductance coil, the ninth internal connection terminal and the tenth internal connection terminal jointly form a' shape structure, the third metal inductance coil is connected with the first connection through hole through the ninth internal connection terminal, and the third metal inductance coil is connected with the tenth connection through hole through the tenth internal connection terminal; the fourth metal inductance coil is connected with a third connecting through hole through the eleventh internal connecting terminal, and the fourth metal inductance coil is connected with a ninth connecting through hole through the twelfth internal connecting terminal; the fifth metal inductance coil comprises a sixth metal inductance coil and a seventh metal inductance coil, the sixth metal inductance coil and the seventh metal inductance coil are connected, a thirteenth internal connection terminal, a fourteenth internal connection terminal and a fifteenth internal connection terminal are connected with the fifth metal inductance coil, the thirteenth internal connection terminal, the fourteenth internal connection terminal and the fifteenth internal connection terminal form a U-shaped structure together, the fourteenth internal connection terminal and the fifteenth internal connection terminal are respectively arranged at two ends of the fifth metal inductance coil, the fourteenth internal connection terminal is arranged in the middle of the fifth metal inductance coil, the fifth metal inductance coil is connected with the fifth connection through hole through the thirteenth internal connection terminal, the sixth metal inductance coil is connected with the seventh connection through hole through the fourteenth internal connection terminal, and the seventh metal inductance coil is connected with the eighth connection through hole through the fifteenth internal connection terminal;
and a ninth layer, the structure of which is identical to that of the eighth layer.
The technical scheme adopted by the invention for solving the technical problems further comprises the following steps:
the first layer is formed by printing six mutually independent metal plane conductors on a ceramic dielectric substrate, and the six mutually independent metal plane conductors are respectively a first input/output port, a second output/input port, a first grounding electrode, a second grounding electrode, a first NC port and a second NC port.
The capacitor substrates in the fifth layer comprise a seventh capacitor substrate and an eighth capacitor substrate, and the seventh capacitor substrate and the eighth capacitor substrate are arranged at the middle position, are mutually connected and are symmetrically arranged.
The circuit structure layer also comprises a tenth layer, and the tenth layer is formed by printing a nonmetal pattern on the ceramic dielectric substrate.
The beneficial effects of the invention are as follows: the invention relates to a band-pass filter for a miniature 5G module based on an LTCC technology, which adopts a coupling structure design and is composed of four-stage resonators. The filter is manufactured by adopting an LTCC technology and then co-firing at a low temperature of about 900 ℃, and the size of the finished product is 1.0mm*0.5mm*0.39mm Max. According to the invention, the insertion loss is less than or equal to 1.6dB in the 4.4-5 GHz frequency band, the out-of-band suppression is carried out, the DC-3G is more than or equal to 25dB in the frequency range of DC-2.69 GHz, the 10dB in the frequency range of WiFi 5.49-5.67 GHz, the 12dB in the frequency range of 5.67-5.95 GHz, and the 12dB in the pass band of return loss. The invention is based on LTCC (low temperature co-fired ceramic) technology, adopts a four-order coupling model design, and the coupling transmission line improves the Q value of the transmission line and the special electrical property requirement of the ultra-small band-pass filter for 5G module based on the LTCC technology by a double-layer winding technology. The invention effectively realizes the characteristics of the band-pass filter for the 5G module, has the advantages of low loss, high inhibition, high reliability, small size suitable for modularization, low cost, suitability for large-scale production and the like, and meets the development requirements of integration and miniaturization of electronic elements in the 5G era.
The invention will be further described with reference to the drawings and detailed description.
Drawings
Fig. 1 is a schematic diagram of an equivalent circuit of a filter for a 5G module according to the present invention.
Fig. 2 is a schematic perspective view of the appearance structure of the filter for 5G module according to the present invention.
Fig. 3 is a schematic diagram of the internal structure of the filter for 5G module according to the present invention.
Fig. 4 is an electrical characteristic curve of a band-pass filter for a subminiature 5G module based on LTCC technology according to the present invention.
Fig. 5 is a schematic diagram of a planar structure of a first layer circuit according to the present invention.
FIG. 6 is a schematic plan view of a connecting via between a first layer and a second layer according to the present invention.
Fig. 7 is a schematic diagram of a second-layer circuit plane structure according to the present invention.
Fig. 8 is a schematic plan view of a connection via between a second layer and a third layer according to the present invention.
Fig. 9 is a schematic diagram of a third layer of circuit plane structure according to the present invention.
Fig. 10 is a schematic plan view of a connecting via between a third layer and a fourth layer according to the present invention.
Fig. 11 is a schematic diagram of a fourth layer circuit plane structure according to the present invention.
Fig. 12 is a schematic plan view of a connecting via between a fourth layer and a fifth layer according to the present invention.
Fig. 13 is a schematic diagram of a fifth layer circuit plane structure according to the present invention.
Fig. 14 is a schematic plan view of a connecting through hole between a fifth layer and a sixth layer according to the present invention.
Fig. 15 is a schematic diagram of a sixth and seventh layer circuit plane structure according to the present invention.
Fig. 16 is a schematic plan view of a connecting via between a seventh layer and an eighth layer according to the present invention.
Fig. 17 is a schematic diagram of a planar structure of an eighth and a ninth layers of circuit according to the present invention.
Fig. 18 is a schematic plan view of a tenth layer circuit according to the present invention.
In the figure, a 1-first layer circuit planar structure, a 2-second layer circuit planar structure, a 3-third layer circuit planar structure, a 3-1-first capacitance substrate, a 3-1 a-first internal connection terminal, a 3-2-second capacitance substrate, a 3-2 a-second internal connection terminal, a 3-3-third capacitance substrate, a 3-4-fourth capacitance substrate, a 4-fourth layer circuit planar structure, a 4-1-fifth capacitance substrate, a 4-2-sixth capacitance substrate, a 4-1 a-third internal connection terminal, a 4-2 a-fourth internal connection terminal, a 5-fifth layer circuit planar structure, a 5-1-seventh capacitance substrate, a 5-2-eighth capacitance substrate, a 6A-sixth layer circuit planar structure, a 6-1-first metal inductor coil, a 6-1 a-fifth internal connection terminal, a 6-1B-sixth internal connection terminal, a 6-2-second metal inductor coil, a 6-2 a-seventh internal connection terminal, a 6-2B-eighth internal connection terminal, a 6-7-second internal connection terminal, a 7-first internal connection terminal, a 7-7A-third internal connection terminal, a 7-first internal connection terminal, 7-3 a-thirteenth internal connection terminal, 7-3B-fourteenth internal connection terminal, 7-3 c-fifteenth internal connection terminal, 7-3-1-sixth metal inductor, 7-3-2-seventh metal inductor, 7B-ninth circuit planar structure, 8-tenth circuit planar structure, 9-first connection via, which is a connection via between electrode port P1 and first capacitor substrate 3-1, fifth capacitor substrate 4-1 and third metal inductor 7-1, 10-second connection via, which is a connection via between electrode port P2 and capacitor substrate 2, 11-third connection via, which is a connection via between electrode port P2 and second capacitor substrate 3-2, sixth capacitor substrate 4-2 and fourth metal inductor 7-2, 12-fourth connection via, which is a connection via between capacitor substrate 2 and second metal inductor 6-2, 13-fifth connection via, which is a connection via between capacitor substrate 2 and fifth capacitor substrate 7-3, which is a connection via between capacitor substrate 7-3 and fifth capacitor substrate 3, which is a connection via between electrode port P2 and capacitor substrate 3-2, 11-third connection via, which is a connection via between capacitor substrate 7-3 and capacitor substrate 3-6-fourth metal inductor, which is a connection via between capacitor substrate 3-3 and capacitor substrate 3, which is a connection via between capacitor substrate 3-fourth capacitor substrate 3-3 and capacitor substrate 2 and capacitor substrate is a, which is a connection via between capacitor substrate 3-fourth metal inductor is connected between capacitor substrate 3-7-2, 17-ninth connecting through holes, which are connecting through holes between the inner end 6-2b of the second metal induction coil 6-2 and the inner end 7-2b of the fourth metal induction coil 7-2, 18-tenth connecting through holes, which are connecting through holes between the inner end 6-1a of the first metal induction coil 6-1 and the inner end 7-1a of the third metal induction coil 7-1, P1-first input/output port, P2-first grounding electrode, P3-second output/input port, P4-first NC port, P5-second grounding electrode, P6-second NC port.
Detailed Description
This example is a preferred embodiment of the present invention, and other principles and basic structures are the same as or similar to those of this example, and all fall within the scope of the present invention.
Referring to fig. 1, fig. 1 is an equivalent circuit diagram of a band-pass filter for a subminiature 5G module based on LTCC technology. When the band-pass filter is used, a signal is output from a port (1) to a port (2) after entering, and the band-pass filter is formed by an inductor L1, an inductor L2, an inductor L3, an inductor L4, an inductor L5, an inductor L6, an inductor L7, a coupling transmission line SL1, a coupling transmission line SL2, a coupling transmission line SL3, a coupling transmission line SL4, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C6 and a capacitor C7, wherein the inductor L1, the coupling transmission line SL1, the inductor L5 and the capacitor C1 form first-stage parallel resonance; the inductor L2, the coupling transmission line SL3, the inductor L6 and the capacitor C2 form a second-stage parallel resonator; the inductor L3, the coupling transmission line SL4, the inductor L6 and the capacitor C3 form a third-stage parallel resonator; the inductor L4, the coupling transmission line SL2, the inductor L7 and the capacitor C4 form a fourth-stage parallel resonator, wherein the first-stage parallel resonator and the second-stage parallel resonator are connected through a capacitor C5, the third-stage parallel resonator and the fourth-stage parallel resonator are connected through a capacitor C6, and the input port (1) and the output port (2) are connected through a capacitor C7.
Fig. 2 is an external appearance structure of a band-pass filter for a subminiature 5G module based on LTCC technology according to the present invention, wherein bottom electrode P1 is a signal input/output terminal, bottom electrode P3 is a signal output/input terminal, bottom electrode P2 and bottom electrode P5 are ground ports, and bottom electrode P4 and bottom electrode P6 are NC ports; the top Mark is the filter directivity identification. The internal structure of the ultra-small band-pass filter for 5G module based on LTCC technology is shown in fig. 3 and 5-18, the circuit structure is distributed in the ceramic matrix, and ten layers of circuit structures are all arranged in the invention. This will be described in order from bottom to top:
six mutually independent metal plane conductors, namely a first input/output port P1, a second output/input port P3, a first grounding electrode P2, a second grounding electrode P5, a first NC port P4 and a second NC port P6, are printed on the ceramic dielectric substrate.
And the second layer is formed by printing three mutually independent metal plane conductors, namely a capacitor substrate 21, a first connecting through hole 9 and a third connecting through hole 11, on a ceramic dielectric substrate, wherein the capacitor substrate 21 is connected with a first grounding electrode P2 through a second connecting through hole 10, and the first connecting through hole 9 and the third connecting through hole 11 are respectively connected with a first input/output port P1 and a second output/input port P3.
And the third layer is formed by printing seven mutually independent metal plane conductors on a ceramic dielectric substrate, namely a first capacitor substrate 3-1, a second capacitor substrate 3-2, a third capacitor substrate 3-3, a fourth capacitor substrate 3-4, a fourth connecting through hole 12, a fifth connecting through hole 13 and a sixth connecting through hole 14, wherein a first internal connecting terminal 3-1a is connected with the first capacitor substrate 3-1, the first internal connecting terminal 3-1a of the capacitor substrate is connected with the first connecting through hole 9, a second internal connecting terminal 3-2a is connected with the second capacitor substrate 3-2, the second internal connecting terminal 3-2a of the capacitor substrate is connected with the third connecting through hole 11, the third capacitor substrate 3-3 is connected with the seventh connecting through hole 15, and the fourth capacitor substrate 3-4 is connected with the eighth connecting through hole 16.
And a fourth layer, wherein seven mutually independent metal plane conductors are printed on the ceramic dielectric substrate, namely a fifth capacitor substrate 4-1, a sixth capacitor substrate 4-2, a fourth connecting through hole 12, a fifth connecting through hole 13, a sixth connecting through hole 14, a seventh connecting through hole 15 and an eighth connecting through hole 16, wherein a third internal connecting terminal 4-1a is arranged in connection with the fifth capacitor substrate 4-1, the fifth capacitor substrate 4-1 is connected with the first connecting through hole 9 through the third internal connecting terminal 4-1a, a fourth internal connecting terminal 4-2a is arranged in connection with the sixth capacitor substrate 4-2, and the sixth capacitor substrate 4-2 is connected with the third connecting through hole 11 through the fourth internal connecting terminal 4-2 a.
And the fifth layer is formed by printing eight mutually independent metal plane conductors, namely a capacitor substrate, a first connecting through hole 9, a third connecting through hole 11, a fourth connecting through hole 12, a fifth connecting through hole 13, a sixth connecting through hole 14, a seventh connecting through hole 15 and an eighth connecting through hole 16, on a ceramic dielectric substrate, wherein the capacitor substrate comprises a seventh capacitor substrate 5-1 and an eighth capacitor substrate 5-2, and the seventh capacitor substrate 5-1 and the eighth capacitor substrate 5-2 are arranged at the middle position, are mutually connected and are symmetrically arranged.
A sixth layer, seven mutually independent metal plane conductors are printed on the ceramic dielectric substrate, and are respectively a first metal induction coil 6-1, a second metal induction coil 6-2, a first connecting through hole 9, a third connecting through hole 11, a fifth connecting through hole 13, a seventh connecting through hole 15 and an eighth connecting through hole 16, wherein a fifth internal connecting endpoint 6-1a and a sixth internal connecting endpoint 6-1b are connected with the first metal induction coil 6-1, the fifth internal connecting endpoint 6-1a and the sixth internal connecting endpoint 6-1b jointly form a U-shaped structure, the first metal induction coil 6-1 is connected with the sixth connecting through hole 14 through the fifth internal connecting endpoint 6-1a, and the first metal induction coil 6-1 is connected with the tenth connecting through hole 18 through the sixth internal connecting endpoint 6-1 b; the second metal inductor 6-2 is connected with a seventh internal connection terminal 6-2a and an eighth internal connection terminal 6-2b, the second metal inductor 6-2, the seventh internal connection terminal 6-2a and the eighth internal connection terminal 6-2b together form a U-shaped structure, the second metal inductor 6-2 is connected with the fourth connection through hole 12 through the seventh internal connection terminal 6-2a, and the second metal inductor 6-2 is connected with the ninth connection through hole 17 through the internal connection terminal 2-1 b.
The seventh layer is a sixth repeated layer, i.e. the structure is identical to that of the sixth layer, and will not be described here again.
An eighth layer, three mutually independent metal plane conductors are printed on the ceramic dielectric substrate, namely a third metal inductance coil 7-1, a fourth metal inductance coil 7-2 and a fifth metal inductance coil 7-3, wherein a ninth internal connection terminal 7-1a and a tenth internal connection terminal 7-1b are connected with the third metal inductance coil 7-1, the ninth internal connection terminal 7-1a and the tenth internal connection terminal 7-1b jointly form a C-shaped structure, the third metal inductance coil 7-1 is connected with the first connecting hole 9 through the ninth internal connection terminal 7-1a, and the third metal inductance coil 7-1 is connected with the tenth connecting hole 18 through the tenth internal connection terminal 7-1 b; the fourth metal inductance coil 7-2 is connected with an eleventh internal connection terminal 7-2a and a twelfth internal connection terminal 7-2b, the fourth metal inductance coil 7-2, the eleventh internal connection terminal 7-2a and the twelfth internal connection terminal 7-2b together form a C-shaped structure, the fourth metal inductance coil 7-2 is connected with the third connection through hole 11 through the eleventh internal connection terminal 7-2a, and the fourth metal inductance coil 7-2 is connected with the ninth connection through hole 17 through the twelfth internal connection terminal 7-2 b; the fifth metal induction coil 7-3 comprises a sixth metal induction coil 7-3-1 and a seventh metal induction coil 7-3-2, the sixth metal induction coil 7-3-1 and the seventh metal induction coil 7-3-2 are connected and symmetrically arranged, the thirteenth inner connection terminal 7-3a, the fourteenth inner connection terminal 7-3b and the fifteenth inner connection terminal 7-3c are connected with the fifth metal induction coil 7-3, the thirteenth inner connection terminal 7-3a, the fourteenth inner connection terminal 7-3b and the fifteenth inner connection terminal 7-3c together form a U-shaped structure, the fourteenth inner connection terminal 7-3b and the fifteenth inner connection terminal 7-3c are respectively arranged at two ends of the fifth metal induction coil 7-3, the fourteenth inner connection terminal 7-3b is arranged at the middle position of the fifth metal induction coil 7-3, namely, the inductor 7-3-1 and the fifteenth inner connection terminal 7-3c are connected with the thirteenth inner connection terminal 7-3c through the thirteenth inner connection terminal 7-3b and the fifteenth inner connection terminal 7-3c, the thirteenth inner connection terminal 7-3b and the fifteenth inner connection terminal 7-3c are connected with the seventh metal induction coil 7-3 through a through hole 15 through the thirteenth inner connection terminal 7-3.
The ninth layer is an eighth layer, that is, the structure is identical to that of the eighth layer, and the description is omitted here.
And a tenth layer, wherein a block of non-metal pattern is printed on the ceramic dielectric substrate to distinguish Mark of the electrode pin direction of the product.
Wherein, the inductor L1 in the equivalent circuit is formed by the first connecting hole 9, the inductor L2 in the equivalent circuit is formed by the seventh connecting hole 15, the inductor L3 in the equivalent circuit is formed by the eighth connecting hole 16, the inductor L4 in the equivalent circuit is formed by the third connecting hole 11, the inductor L5 in the equivalent circuit is formed by the sixth connecting hole 14, the inductor L6 in the equivalent circuit is formed by the fifth connecting hole 13, and the inductor L7 in the equivalent circuit is formed by the fourth connecting hole 12; the capacitor C1 in the equivalent circuit is composed of a first capacitor substrate 3-1 and a capacitor substrate 2, the capacitor C2 in the equivalent circuit is composed of a third capacitor substrate 3-3 and a capacitor substrate 2, the capacitor C3 in the equivalent circuit is composed of a fourth capacitor substrate 3-4 and a capacitor substrate 2, the capacitor C4 in the equivalent circuit is composed of a second capacitor substrate 3-2 and a capacitor substrate 2, the capacitor C5 in the equivalent circuit is composed of a fifth capacitor substrate 4-1 and a third capacitor substrate 3-3, the capacitor C6 in the equivalent circuit is composed of a sixth capacitor substrate 4-2 and a fourth capacitor substrate 3-4, and the capacitor C7 in the equivalent circuit is composed of a seventh capacitor substrate 5-1, an eighth capacitor substrate 5-2, a fifth capacitor substrate 4-1 and a sixth capacitor substrate 4-2; the coupling transmission line SL1 is composed of a double-layer metal conductor coil 6-1 and a metal conductor coil 7-1, the coupling transmission line SL2 is composed of a double-layer metal conductor coil 7-3-1 in an eighth layer and a ninth layer, the coupling transmission line SL3 is composed of a double-layer metal conductor coil 7-3-2 in the eighth layer and the ninth layer, and the coupling transmission line SL4 is composed of a double-layer metal conductor coil 6-2 and a metal conductor coil 7-2.
When the filter is used, referring to FIG. 4, FIG. 4 is an electrical characteristic curve of a 5G module filter, and as can be seen from FIG. 4, the insertion loss is less than or equal to 1.6dB in a 4.4-5 GHz frequency band, the out-of-band suppression is carried out, DC is more than or equal to 25dB in Sub-3G, DC is more than or equal to 25dB in WiFi5.49-5.67 GHz is more than or equal to 10dB, 5.67-5.95 GHz is more than or equal to 12dB, and the return loss in a passband is more than or equal to 12dB.
The invention relates to a band-pass filter for a miniature 5G module based on an LTCC technology, which adopts a coupling structure design and is composed of four-stage resonators. The filter is manufactured by adopting an LTCC technology and then co-firing at a low temperature of about 900 ℃, and the size of the finished product is 1.0mm*0.5mm*0.39mm Max. The invention is based on LTCC (low temperature co-fired ceramic) technology, adopts a four-order coupling model design, and the coupling transmission line improves the Q value of the transmission line and the special electrical property requirement of the ultra-small band-pass filter for 5G module based on the LTCC technology by a double-layer winding technology. The invention effectively realizes the characteristics of the band-pass filter for the 5G module, has the advantages of low loss, high inhibition, high reliability, small size suitable for modularization, low cost, suitability for large-scale production and the like, and meets the development requirements of integration and miniaturization of electronic elements in the 5G era.
Claims (4)
1. A kind of ultra-small type 5G module uses the band-pass filter based on LTCC technology, characterized by that: the filter comprises a circuit structure layer which is sequentially arranged inside a ceramic matrix from bottom to top,
a first layer, a first input/output port (P1), a second input/output port (P3) and a ground electrode (P2) printed on a ceramic dielectric substrate;
the second layer is formed by printing three mutually independent metal plane conductors, namely a main capacitor substrate (21), a first connecting through hole (9) and a third connecting through hole (11), on a ceramic dielectric substrate, wherein the main capacitor substrate (21) is connected with a first grounding electrode (P2) through a second connecting through hole (10), and the first connecting through hole (9) and the third connecting through hole (11) are connected with a first input/output port (P1) and a second output/input port (P3) respectively;
the third layer is formed by printing seven mutually independent metal plane conductors on a ceramic dielectric substrate, wherein the seven mutually independent metal plane conductors are respectively a first capacitor substrate (3-1), a second capacitor substrate (3-2), a third capacitor substrate (3-3), a fourth capacitor substrate (3-4), a fourth connecting through hole (12), a fifth connecting through hole (13) and a sixth connecting through hole (14), a first internal connecting terminal (3-1 a) is arranged on the first capacitor substrate (3-1), the first internal connecting terminal (3-1 a) of the first capacitor substrate (3-1) is connected with the first connecting through hole (9), a second internal connecting terminal (3-2 a) is arranged on the second capacitor substrate (3-2), the second internal connecting terminal (3-2 a) of the second capacitor substrate (3-2) is connected with the third connecting through hole (11), the third capacitor substrate (3-3) is connected with the seventh connecting through hole (15), and the fourth capacitor substrate (3-4) is connected with the eighth connecting through hole (16);
a fourth layer, seven mutually independent metal plane conductors are printed on the ceramic dielectric substrate, namely a fifth capacitor substrate (4-1), a sixth capacitor substrate (4-2), a fourth connecting through hole (12), a fifth connecting through hole (13), a sixth connecting through hole (14), a seventh connecting through hole (15) and an eighth connecting through hole (16), wherein a third internal connecting endpoint (4-1 a) is arranged on the fifth capacitor substrate (4-1), the fifth capacitor substrate (4-1) is connected with the first connecting through hole (9) through the third internal connecting endpoint (4-1 a), a fourth internal connecting endpoint (4-2 a) is arranged on the sixth capacitor substrate (4-2), and the sixth capacitor substrate (4-2) is connected with the third connecting through hole (11) through the fourth internal connecting endpoint (4-2 a);
the fifth layer is formed by printing eight mutually independent metal plane conductors, namely a capacitor substrate, a first connecting through hole (9), a third connecting through hole (11), a fourth connecting through hole (12), a fifth connecting through hole (13), a sixth connecting through hole (14), a seventh connecting through hole (15) and an eighth connecting through hole (16), on a ceramic dielectric substrate;
a sixth layer, seven mutually independent metal plane conductors are printed on the ceramic dielectric substrate, namely a first metal inductance coil (6-1), a second metal inductance coil (6-2), a first connecting through hole (9), a third connecting through hole (11), a fifth connecting through hole (13), a seventh connecting through hole (15) and an eighth connecting through hole (16), wherein a fifth internal connecting endpoint (6-1 a) and a sixth internal connecting endpoint (6-1 b) are connected with the first metal inductance coil (6-1), the fifth internal connecting endpoint (6-1 a) and the sixth internal connecting endpoint (6-1 b) form a U-shaped structure together, the first metal inductance coil (6-1) is connected with the sixth connecting through hole (14) through the fifth internal connecting endpoint (6-1 a), and the first metal inductance coil (6-1) is connected with the tenth connecting through hole (18) through the sixth internal connecting endpoint (6-1 b); a seventh internal connection end point (6-2 a) and an eighth internal connection end point (6-2 b) are connected with the second metal induction coil (6-2), the seventh internal connection end point (6-2 a) and the eighth internal connection end point (6-2 b) form a U-shaped structure together, the second metal induction coil (6-2) is connected with the fourth connection through hole (12) through the seventh internal connection end point (6-2 a), and the second metal induction coil (6-2) is connected with the ninth connection through hole (17) through the internal connection end point (2-1 b);
a seventh layer having the same structure as the sixth layer;
an eighth layer, three mutually independent metal plane conductors are printed on the ceramic dielectric substrate, namely a third metal inductance coil (7-1), a fourth metal inductance coil (7-2) and a fifth metal inductance coil (7-3), wherein a ninth internal connection terminal (7-1 a) and a tenth internal connection terminal (7-1 b) are connected with the third metal inductance coil (7-1), the ninth internal connection terminal (7-1 a) and the tenth internal connection terminal (7-1 b) form a C-shaped structure together, the third metal inductance coil (7-1) is connected with the first connection through hole (9) through the ninth internal connection terminal (7-1 a), and the third metal inductance coil (7-1) is connected with the tenth connection through hole (18) through the tenth internal connection terminal (7-1 b); an eleventh internal connection terminal (7-2 a) and a twelfth internal connection terminal (7-2 b) are connected with the fourth metal induction coil (7-2), the eleventh internal connection terminal (7-2 a) and the twelfth internal connection terminal (7-2 b) form a C-shaped structure together, the fourth metal induction coil (7-2) is connected with the third connection through hole (11) through the eleventh internal connection terminal (7-2 a), and the fourth metal induction coil (7-2) is connected with the ninth connection through hole (17) through the twelfth internal connection terminal (7-2 b); the fifth metal induction coil (7-3) comprises a sixth metal induction coil (7-3-1) and a seventh metal induction coil (7-3-2), the sixth metal induction coil (7-3-1) and the seventh metal induction coil (7-3-2) are connected, a thirteenth internal connection terminal (7-3 a), a fourteenth internal connection terminal (7-3 b) and a fifteenth internal connection terminal (7-3 c) are connected with the fifth metal induction coil (7-3), the thirteenth internal connection terminal (7-3 a), the fourteenth internal connection terminal (7-3 b) and the fifteenth internal connection terminal (7-3 c) form a U-shaped structure together, the fourteenth internal connection terminal (7-3 b) and the fifteenth internal connection terminal (7-3 c) are respectively arranged at two ends of the fifth metal induction coil (7-3), the fourteenth internal connection terminal (7-3 b) is arranged at an intermediate position of the fifth metal induction coil (7-3), the thirteenth internal connection terminal (7-3) is connected with the fifth metal induction coil (7-3) through the thirteenth internal connection terminal (7-3 a), the sixth metal inductance coil (7-3-1) is connected with the seventh connection through hole (15) through a fourteenth internal connection terminal (7-3 b), and the seventh metal inductance coil (7-3-2) is connected with the eighth connection through hole (16) through a fifteenth internal connection terminal (7-3 c);
and a ninth layer, the structure of which is identical to that of the eighth layer.
2. The LTCC technology-based bandpass filter for a subminiature 5G module as set forth in claim 1, wherein: the first layer is formed by printing six mutually independent metal plane conductors on a ceramic dielectric substrate, and the six mutually independent metal plane conductors are respectively a first input/output port P1, a second input/output port P3, a first grounding electrode P2, a second grounding electrode P5, a first NC port P4 and a second NC port P6.
3. The LTCC technology-based bandpass filter for a subminiature 5G module as set forth in claim 1, wherein: the capacitor substrates in the fifth layer comprise a seventh capacitor substrate (5-1) and an eighth capacitor substrate (5-2), and the seventh capacitor substrate (5-1) and the eighth capacitor substrate (5-2) are arranged at the middle position, are mutually connected and are symmetrically arranged.
4. The LTCC technology-based bandpass filter for a subminiature 5G module as set forth in claim 1, wherein: the circuit structure layer also comprises a tenth layer, and the tenth layer is formed by printing a nonmetal pattern on the ceramic dielectric substrate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311270795.3A CN117200729A (en) | 2023-09-28 | 2023-09-28 | Ultra-small band-pass filter for 5G module based on LTCC technology |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117978116A (en) * | 2024-04-01 | 2024-05-03 | 深圳市麦捷微电子科技股份有限公司 | Equivalent circuit of 5G symmetrical LTCC (Low temperature Co-fired ceramic) multilayer band-pass filter and filter |
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2023
- 2023-09-28 CN CN202311270795.3A patent/CN117200729A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117978116A (en) * | 2024-04-01 | 2024-05-03 | 深圳市麦捷微电子科技股份有限公司 | Equivalent circuit of 5G symmetrical LTCC (Low temperature Co-fired ceramic) multilayer band-pass filter and filter |
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