CN211557238U - Multilayer ceramic dielectric sheet type duplexer - Google Patents
Multilayer ceramic dielectric sheet type duplexer Download PDFInfo
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- CN211557238U CN211557238U CN201922212351.XU CN201922212351U CN211557238U CN 211557238 U CN211557238 U CN 211557238U CN 201922212351 U CN201922212351 U CN 201922212351U CN 211557238 U CN211557238 U CN 211557238U
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Abstract
The utility model provides a multilayer ceramic dielectric piece formula duplexer, mainly is applied to mobile phone, panel computer and various communications facilities of other, the duplexer including the base member, set up at the long limit both sides welding terminal pin position of base member and set up the circuit layer in the base member is inside, the circuit layer including 8 layers of circuit structure, the beneficial effects of the utility model are that: the utility model discloses use LTCC (low temperature to burn pottery altogether) technique as the basis, adopt lumped parameter model design to realize high performance multilayer ceramic dielectric piece formula duplexer. The utility model discloses effectively realized outband height and restrained, had advantages such as low-loss, high reliability, low cost and be suitable for large-scale production, still adapted to new electronic component miniaturization development trend in addition.
Description
Technical Field
The invention discloses a high-performance multilayer ceramic dielectric sheet type duplexer which is mainly applied to mobile phones, tablet computers and other various communication equipment.
Background
With the rapid development of communication systems, more frequency bands and systems are brought from the early 2G single communication system to the current 2G, 3G, 4G, WiFi, bluetooth, NFC, FM and later popular 5G. The radio frequency front ends of mobile phones and various communication products become extremely complex, and the mobile phones and various communication products need to be integrated as much as possible in a limited design space, and simultaneously meet the requirements of miniaturization, high performance and low cost.
The Low Temperature Co-fired Ceramic (LTCC) technology has unique advantages in the fields of electronic components and packaging, and is widely applied to the fields of communication, automobiles, medical equipment and the like due to the advantages of high reliability, Low insertion loss, high inhibition, small volume, light weight, easy integration, Low cost, suitability for large-scale production and the like. The method provides possibility for the development of the multilayer radio frequency device to miniaturization, high performance and low cost. The low-temperature ceramic co-firing technology is that at a lower temperature, high-conductivity metals such as gold, silver, copper and the like can be used as conductive media, all circuits are laminated together for one-time sintering, time is saved, cost is reduced, the dielectrics are not easy to oxidize, electroplating protection is not needed, and the size of the circuits is greatly reduced.
Disclosure of Invention
The invention provides a high-performance multilayer ceramic dielectric chip duplexer, which adopts a special structure designed by lumped parameters and consists of a low-pass filter and a high-pass filter which form a complementary duplexer. The ceramic is integrated into the same element by using an LTCC forming technology and then is formed by low-temperature co-firing at 900 ℃. The technical scheme adopted by the invention for solving the technical problems is as follows: the utility model provides a high performance multilayer ceramic dielectric chip formula duplexer, includes the base member, sets up at the long limit both sides welding terminal pin position of base member and sets up the circuit layer in the base member inside, the inside circuit layer of base member be laminated structure.
The low-frequency band of the high-performance multilayer ceramic dielectric chip type duplexer provided by the invention is a low-pass filter consisting of a first inductor L1, a second inductor L2, a first capacitor C1, a second capacitor C2 and a third capacitor C3, and the isolation is improved by generating a transmission zero point at the high-frequency band through parallel resonance of the first inductor L1 and the second capacitor C2. The high-frequency band is a high-pass filter consisting of a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a third inductor L3 and a fourth inductor L4, the sixth capacitor C6 is bridged at two ends of the fourth capacitor C4 and the fifth capacitor C5, a transmission zero point is formed at a low-frequency band, and the high-end is connected with the fourth inductor L4 in series to widen the bandwidth of the high-frequency band. The high-low pass filter forms a duplexer through a common port (I), wherein the common port (I) is a low-frequency input/output port, and the common port (II) is a high-frequency input/output port.
And the second grounding port P2, the fourth grounding port P4 and the sixth grounding port P6 are grounding ports of the duplexer, the common port P5 is a common port, P1 is a high-frequency-band input/output port, P3 is a low-frequency-band input/output port, and Mark is a direction identifier.
The circuit structure of the duplexer is distributed in the ceramic substrate. The circuit structure I has eight layers, and each layer has the following structure:
the first layer is characterized in that three mutually insulated metal plane conductors are printed on the ceramic dielectric substrate and are respectively a first layer of first capacitor substrate, a first layer of second capacitor substrate and a first layer of third capacitor substrate, wherein a first internal end point and a second internal end point of the first layer of first capacitor substrate are respectively connected with a sixth grounding port and a second grounding port, a first internal end point of the first layer of second capacitor substrate is connected with a common port, and the first layer of third capacitor substrate is connected with a fourth grounding port;
the second layer is printed with three insulated metal plane conductors which are respectively a second layer of first capacitor substrate, a second layer of second capacitor substrate and a second layer of third capacitor substrate, wherein the second layer of first capacitor substrate is connected with the first point column, and the second layer of second capacitor substrate is connected with the second point column; the inner end point of the second layer of third capacitor substrate is connected with the third point column;
the ceramic dielectric substrate is printed with six metal plane conductors which are respectively a third layer of first capacitor substrate, a third layer of second capacitor substrate, a third layer of third capacitor substrate, a third layer of fourth capacitor substrate, a third layer of fifth capacitor substrate and a third layer of sixth capacitor substrate, wherein the internal endpoint of the third layer of first capacitor substrate is connected with the low-frequency band input/output port, the internal endpoint of the third layer of second capacitor substrate is connected with the third point column, the third layer of third capacitor substrate is connected with the high-frequency band input/output port, the third layer of fourth capacitor substrate is connected with the grounding port, the internal endpoint of the third layer of fifth capacitor substrate is connected with the public port, and the internal endpoint of the third layer of sixth capacitor substrate is connected with the grounding port;
a fourth layer of first capacitor substrate with an insulated metal planar conductor printed on the ceramic dielectric substrate and having its internal terminal interconnected with the ground port
A fifth layer, wherein two mutually insulated metal coils are printed on the ceramic dielectric substrate and are respectively a fifth layer first inductance coil and a fifth layer second inductance coil, a first internal endpoint and a second internal endpoint of the fifth layer first inductance coil are respectively connected with the second point column and the fourth point column, and a first internal endpoint and a second internal endpoint of the fifth layer second inductance coil are respectively connected with the first point column and the fifth point column;
a sixth layer, wherein two mutually insulated metal coils are printed on the ceramic dielectric substrate and respectively comprise a sixth layer of first inductance coil and a sixth layer of second inductance coil, a first internal endpoint and a second internal endpoint of the sixth layer of first inductance coil are respectively connected with the low-frequency-band input/output port and the fifth point column, and a first internal endpoint and a second internal endpoint of the sixth layer of second inductance coil are respectively connected with the high-frequency-band input/output port and the fourth point column;
a seventh layer, wherein two mutually insulated metal coils are printed on the ceramic dielectric substrate, namely a seventh layer first inductance coil and a seventh layer second inductance coil, a first internal endpoint and a second internal endpoint of the seventh layer first inductance coil are respectively connected with the first point column and the sixth point column, and a first internal endpoint and a second internal endpoint of the seventh layer second inductance coil are respectively connected with the seventh point column and the third point column;
and in the eighth layer, two mutually insulated metal coils, namely an eighth layer first inductance coil and an eighth layer second inductance coil, are printed on the ceramic dielectric substrate, a first internal endpoint and a second internal endpoint of the eighth layer first inductance coil are respectively connected with the public port and the sixth point column, and a first internal endpoint and a second internal endpoint of the eighth layer second inductance coil are respectively connected with the grounding port and the seventh point column.
The invention has the beneficial effects that: the invention is based on LTCC (low temperature co-fired ceramic) technology, and adopts lumped parameter model design to realize high-performance multilayer ceramic dielectric sheet type duplexer. The invention effectively realizes out-of-band high suppression, has the advantages of low loss, high reliability, low cost, suitability for large-scale production and the like, and is suitable for the miniaturization development trend of new electronic elements.
Drawings
FIG. 1 is a schematic diagram of an equivalent circuit of a high-performance multilayer ceramic dielectric sheet type duplexer of the present invention;
FIG. 2 is a three-dimensional representation of the appearance structure of the high-performance multilayer ceramic dielectric sheet type duplexer
An intent;
FIG. 3 is a schematic diagram of the internal structure of the high-performance multilayer ceramic dielectric sheet type duplexer of the present invention;
FIG. 4 is a schematic plan view of a first circuit layer according to the present invention;
FIG. 5 is a schematic diagram of a second layer circuit structure according to the present invention;
FIG. 6 is a schematic view of a point-pillar connection plane between the second layer and the third layer according to the present invention;
FIG. 7 is a schematic diagram of a third layer circuit plan structure according to the present invention;
FIG. 8 is a schematic diagram of a fourth layer circuit plan structure according to the present invention;
FIG. 9 is a schematic circuit plan view of a fifth layer according to the present invention;
FIG. 10 is a schematic view of a point-to-column connection plane between the fifth layer and the sixth layer according to the present invention;
FIG. 11 is a schematic diagram of a sixth layer circuit plan structure according to the present invention;
FIG. 12 is a schematic diagram of a seventh layer circuit layout according to the present invention;
FIG. 13 is a schematic view of a point-column connection plane between the seventh layer and the eighth layer according to the present invention;
FIG. 14 is a schematic diagram of a circuit plan structure of an eighth layer according to the present invention;
Detailed Description
The invention will be further described with reference to the accompanying drawings and specific embodiments.
Fig. 1 is a high-performance multilayer ceramic dielectric sheet type duplexer. The low-frequency band is a low-pass filter consisting of two inductors L1 and L2 and three capacitors C1, C2 and C3, and the isolation is improved by generating a transmission zero point at the high-frequency band through parallel resonance of the inductor L1 and the capacitor C2. The high-frequency band is a high-pass filter consisting of three capacitors C4, C5 and C6 and two inductors L3 and L4, and is bridged at two ends of C4 and C5 through C6, a transmission zero point is formed at the low-frequency band, and the high-end series inductor L4 widens the bandwidth of the high-frequency band. The high-low pass filter forms a duplexer through a common port (I), wherein the common port (I) is a low-frequency input/output port, and the common port (II) is a high-frequency input/output port.
Fig. 2 is an appearance structure of a high-performance multilayer ceramic dielectric sheet type duplexer, wherein P2, P4 and P6 are duplexer ground ports, P5 is a common port, P1 is a high-band input/output port, and P3 is a low-band input/output port. Mark is a direction Mark.
The internal structure of the high-performance multilayer ceramic dielectric chip duplexer is shown in fig. 3, and the circuit structure is distributed in the ceramic substrate.
The circuit structure I has eight layers, and the structure of each layer is as follows:
a first layer, as shown in fig. 4, three mutually insulated metal plane conductors are printed on the ceramic dielectric substrate to form a first layer first capacitor substrate (1), a first layer second capacitor substrate (2) and a first layer third capacitor substrate (3), wherein a first inner end (1a) and a second inner end (1b) of the first layer first capacitor substrate (1) are respectively connected with a sixth ground port (P6) and a second ground port P2, a first inner end (2a) of the first layer second capacitor substrate (2) is connected with a common port P5, and the first layer third capacitor substrate (3) is connected with a fourth ground port P4;
a second layer, as shown in fig. 5, three insulated metal planar conductors are printed on the ceramic dielectric substrate, namely a second layer of a first capacitor substrate (4), a second layer of a second capacitor substrate (5) and a second layer of a third capacitor substrate (6), wherein the second layer of the first capacitor substrate (4) is connected with the first point post (15), and the second layer of the second capacitor substrate (5) is connected with the second point post (13); the inner terminal (6a) of the second layer of the third capacitor substrate (6) is connected with the third point column (14);
FIG. 6 is a schematic view of a point-post connection between the second and third layers;
a third layer, as shown in fig. 7, six metal plane conductors are printed on the ceramic dielectric substrate, which are a third layer of a first capacitor substrate (7), a third layer of a second capacitor substrate (8), a third layer of a third capacitor substrate (9), a third layer of a fourth capacitor substrate (10), a third layer of a fifth capacitor substrate (11) and a third layer of a sixth capacitor substrate (12), wherein an internal endpoint (7a) of the third layer of the first capacitor substrate (7) is connected with the low-frequency input/output port P3, an internal endpoint 8a of the third layer of the second capacitor substrate (8) is connected with the third point post (14), the third layer of the third capacitor substrate (9) is connected with the high-frequency input/output port P1, the third layer of the fourth capacitor substrate (10) is connected with the ground port P4, an internal endpoint (11a) of the third layer of the fifth capacitor substrate (11) is connected with the common port P5, the inner terminal (12a) of the third layer sixth capacitive substrate (12) is connected to the ground port P6;
a fourth layer, as shown in fig. 8, an insulated metal plane conductor is printed on the ceramic dielectric substrate, which is a fourth layer of the first capacitor substrate (16), and the inner end (16a) of the fourth layer of the first capacitor substrate (16) is connected with the grounding port P2;
a fifth layer, as shown in fig. 9, two mutually insulated metal coils, namely a fifth layer first inductance coil (17) and a fifth layer second inductance coil (18), are printed on the ceramic dielectric substrate, a first internal end point (17a) and a second internal end point (17b) of the fifth layer first inductance coil are respectively connected with the second point column (13) and the fourth point column (20), and a first internal end point (18a) and a second internal end point (18b) of the fifth layer second inductance coil (18) are respectively connected with the first point column (15) and the fifth point column (19);
fig. 10 is a schematic view of the connection of the dot columns between the fifth layer and the sixth layer.
A sixth layer, as shown in fig. 11, two mutually insulated metal coils are printed on the ceramic dielectric substrate, which are a sixth layer of a first inductor coil (21) and a sixth layer of a second inductor coil (22), respectively, a first internal end point (21a) and a second internal end point (21b) of the sixth layer of the first inductor coil (21) are connected to the low-frequency-band input/output port P3 and the fifth point column (19), respectively, and a first internal end point (22a) and a second internal end point (22b) of the sixth layer of the second inductor coil (22) are connected to the high-frequency-band input/output port P1 and the fourth point column (20), respectively;
a seventh layer, as shown in fig. 12, two mutually insulated metal coils are printed on the ceramic dielectric substrate, which are a seventh layer first inductance coil (23) and a seventh layer second inductance coil (24), respectively, a first internal end point 23a and a second internal end point (23b) of the seventh layer first inductance coil (23) are connected with the first point column (15) and the sixth point column (25), respectively, and a first internal end point (24a) and a second internal end point (24b) of the seventh layer second inductance coil (24) are connected with the seventh point column (26) and the third point column (14), respectively;
fig. 13 is a schematic view of a point-column connection plane structure between the seventh layer and the eighth layer.
As shown in fig. 14, the eighth layer is formed by printing two mutually insulated metal coils on the ceramic dielectric substrate, namely, an eighth layer first inductor coil (27) and an eighth layer second inductor coil (28), wherein a first inner end point (27a) and a second inner end point (27b) of the eighth layer first inductor coil (27) are respectively connected with the common port P5 and the sixth point post (25), and a first inner end point (28a) and a second inner end point (28b) of the eighth layer second inductor coil (28) are respectively connected with the ground port P2 and the seventh point post (26).
Claims (2)
1. The utility model provides a multilayer ceramic dielectric piece formula duplexer, a serial communication port, the duplexer is including the base member, set up at the long limit both sides welding terminal pin position of base member and set up the circuit layer in the base member is inside, the circuit layer including 8 layers of circuit structure, wherein:
the first layer is formed by printing three mutually insulated metal plane conductors on a ceramic dielectric substrate, namely a first layer first capacitor substrate (1), a first layer second capacitor substrate (2) and a first layer third capacitor substrate (3), wherein a first inner end point (1a) and a second inner end point (1b) of the first layer first capacitor substrate (1) are respectively connected with a sixth grounding port (P6) and a second grounding port (P2), a first inner end point (2a) of the first layer second capacitor substrate is connected with a common port (P5), and the first layer third capacitor substrate (3) is connected with a fourth grounding port (P4);
the second layer is printed with three insulated metal plane conductors which are respectively a second layer of first capacitor substrate (4), a second layer of second capacitor substrate (5) and a second layer of third capacitor substrate (6), wherein the second layer of first capacitor substrate (4) is connected with the first point post (15), and the second layer of second capacitor substrate (5) is connected with the second point post (13); the inner terminal (6a) of the second layer of the third capacitor substrate (6) is connected with the third point column (14);
a third layer, six metal plane conductors are printed on the ceramic dielectric substrate and respectively comprise a third layer first capacitor substrate (7), a third layer second capacitor substrate (8), a third layer third capacitor substrate (9), a third layer fourth capacitor substrate (10), a third layer fifth capacitor substrate (11) and a third layer sixth capacitor substrate (12), an internal endpoint (7a) of the third layer first capacitor substrate (7) is connected with the low-frequency input/output port (P3), an internal endpoint (8 a) of the third layer second capacitor substrate is connected with a third endpoint column (14), the third layer third capacitor substrate (9) is connected with the high-frequency input/output port (P1), the third layer fourth capacitor substrate (10) is connected with the grounding port (P4), an internal endpoint (11a) of the third layer fifth capacitor substrate (11) is connected with the common port (P5), the inner terminal (12a) of the third layer sixth capacitive substrate (12) is connected to the ground port (P6);
a fourth layer, wherein an insulated metal plane conductor is printed on the ceramic dielectric substrate and is a fourth layer of first capacitor substrate (16), and an internal end point (16a) of the fourth layer of first capacitor substrate (16) is mutually connected with a grounding port (P2);
a fifth layer, wherein two mutually insulated metal coils are printed on the ceramic dielectric substrate, namely a fifth layer first inductance coil (17) and a fifth layer second inductance coil (18), a first inner end point (17a) and a second inner end point (17b) of the fifth layer first inductance coil are respectively connected with the second point column (13) and the fourth point column (20), and a first inner end point (18a) and a second inner end point (18b) of the fifth layer second inductance coil (18) are respectively connected with the first point column (15) and the fifth point column (19);
a sixth layer, wherein two mutually insulated metal coils are printed on the ceramic dielectric substrate, the sixth layer is a first inductance coil (21) and the sixth layer is a second inductance coil (22), a first internal endpoint (21a) and a second internal endpoint (21b) of the sixth layer of the first inductance coil (21) are respectively connected with the low-frequency input/output port (P3) and the fifth point column (19), and a first internal endpoint (22a) and a second internal endpoint (22b) of the sixth layer of the second inductance coil (22) are respectively connected with the high-frequency input/output port (P1) and the fourth point column (20);
a seventh layer, wherein two mutually insulated metal coils are printed on the ceramic dielectric substrate, namely a seventh layer of first inductance coil (23) and a seventh layer of second inductance coil (24), a first internal endpoint (23 a) and a second internal endpoint (23b) of the seventh layer of first inductance coil (23) are respectively connected with the first point column (15) and the sixth point column (25), and a first internal endpoint (24a) and a second internal endpoint (24b) of the seventh layer of second inductance coil (24) are respectively connected with the seventh point column (26) and the third point column (14);
and the eighth layer is formed by printing two mutually insulated metal coils on the ceramic dielectric substrate, wherein the first inductor coil (27) and the second inductor coil (28) are respectively arranged on the eighth layer, a first inner end point (27a) and a second inner end point (27b) of the first inductor coil (27) on the eighth layer are respectively connected with the common port (P5) and the sixth point column (25), and a first inner end point (28a) and a second inner end point (28b) of the second inductor coil (28) on the eighth layer are respectively connected with the grounding port (P2) and the seventh point column (26).
2. The multilayer ceramic dielectric chip duplexer of claim 1, wherein the duplexers are integrated into a same component by LTCC molding technology and then co-fired at 900 ℃.
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| CN201922212351.XU CN211557238U (en) | 2019-12-11 | 2019-12-11 | Multilayer ceramic dielectric sheet type duplexer |
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| CN201922212351.XU CN211557238U (en) | 2019-12-11 | 2019-12-11 | Multilayer ceramic dielectric sheet type duplexer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110768640A (en) * | 2019-12-11 | 2020-02-07 | 深圳市麦捷微电子科技股份有限公司 | Multilayer ceramic dielectric sheet type duplexer |
| CN112821876A (en) * | 2021-01-11 | 2021-05-18 | 深圳市麦捷微电子科技股份有限公司 | Laminated sheet type low-pass filter |
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2019
- 2019-12-11 CN CN201922212351.XU patent/CN211557238U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110768640A (en) * | 2019-12-11 | 2020-02-07 | 深圳市麦捷微电子科技股份有限公司 | Multilayer ceramic dielectric sheet type duplexer |
| CN112821876A (en) * | 2021-01-11 | 2021-05-18 | 深圳市麦捷微电子科技股份有限公司 | Laminated sheet type low-pass filter |
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