CN219833835U - Dual-power low-loss circuit - Google Patents
Dual-power low-loss circuit Download PDFInfo
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- CN219833835U CN219833835U CN202320988629.6U CN202320988629U CN219833835U CN 219833835 U CN219833835 U CN 219833835U CN 202320988629 U CN202320988629 U CN 202320988629U CN 219833835 U CN219833835 U CN 219833835U
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- resistor
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- power supply
- triode
- mos tube
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- 239000003990 capacitor Substances 0.000 claims abstract description 11
- 230000009977 dual effect Effects 0.000 claims description 8
- 230000005669 field effect Effects 0.000 claims description 3
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Abstract
The utility model discloses a dual-power low-loss circuit, which comprises: resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, capacitor C1, MOS transistor Q2, transistor Q3, transistor Q4, and transistor Q5. In the circuit provided by the utility model, the MOS tube is used for realizing the on and off period on the channel between the external power supply and the electric equipment, and when the MOS tube is completely conducted, the voltage drop on the MOS tube is far smaller than that of the diode, so that the power consumption can be effectively reduced. The components outside the MOS tube can ensure that the MOS tube in the circuit can be completely conducted or completely closed under all power supply scenes, so that the automatic seamless switching of power supply is realized, and the loss is avoided.
Description
Technical Field
The utility model relates to the technical field of power supply circuits of electronic products, in particular to a dual-power supply low-loss circuit.
Background
Electronic devices with solar charging function basically need a dual-power supply circuit, solar energy is used as one power supply, and a USB or other charging adapter interface is used as a second power supply provided outside. The dual-power supply needs to realize automatic seamless switching, and when one power supply is disconnected, the other power supply can be connected in a seamless manner, so that the equipment is ensured not to be powered down. Meanwhile, with the increasing importance of energy conservation and emission reduction, the reduction of power consumption loss on a power supply circuit becomes a significant technical improvement.
Currently, the mainstream automatic switchable dual power circuits are shown in fig. 1 and 2, which all use diode devices, and the inherent voltage drop on the diode causes obvious power consumption loss. Another conventional circuit shown in fig. 3 uses a MOS tube instead of a diode, so as to avoid voltage drop of the diode, but the circuit has a problem that the MOS tube is not completely turned on, so that the voltage of the external power supply cannot be completely supplied to the electric equipment, and therefore, power consumption loss is also generated.
Accordingly, the prior art has drawbacks and needs improvement.
Disclosure of Invention
The utility model aims to overcome the defects of the prior art, provides a dual-power low-loss circuit, realizes automatic seamless switching of two paths of external power supplies, avoids the problems of diode voltage drop and incomplete conduction of an MOS (metal oxide semiconductor) tube, and greatly reduces power consumption loss by almost zero voltage drop between the external power supply and electric equipment.
The technical scheme of the utility model is as follows: provided is a dual power supply low loss circuit including: resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, capacitor C1, MOS transistor Q2, transistor Q3, transistor Q4, and transistor Q5;
the drain electrode of the MOS transistor Q1 is connected with one end of the resistor R3 in parallel to be connected with an external power supply 1, the source electrode of the MOS transistor Q1 is connected with the source electrode of the MOS transistor Q2 and one end of the resistor R2 in parallel to be connected with electric equipment, the grid electrode of the MOS transistor Q1 is connected with one end of the resistor R1, the drain electrode of the MOS transistor Q2, one end of the capacitor C1 and the emitter electrode of the triode Q4 in parallel to be connected with an external power supply 2, the other end of the resistor R3 is connected with the emitter electrode of the triode Q3, the collector electrode of the triode Q3 is connected with the base electrode of the triode Q4 and one end of the resistor R4, the collector electrode of the triode Q4 is connected with one end of the resistor R5 and one end of the resistor R6, the grid electrode of the MOS transistor Q2 is connected with the other end of the resistor R2, the emitter electrode of the triode Q5, the other end of the capacitor C1 and the other end of the resistor R5 are respectively grounded.
Further, the MOS transistor Q1 and the MOS transistor Q2 are P-type field effect transistors.
Further, the transistor Q3 and the transistor Q4 are PNP transistors.
Further, the triode Q5 is an NPN triode.
By adopting the scheme, in the circuit provided by the utility model, the MOS tube is used for realizing the on and off period on the channel between the external power supply and the electric equipment, and when the MOS tube is completely conducted, the voltage drop on the MOS tube is far smaller than that of the diode, so that the power consumption can be effectively reduced. The components outside the MOS tube can ensure that the MOS tube in the circuit can be completely conducted or completely closed under all power supply scenes, so that the automatic seamless switching of power supply is realized, and the loss is avoided.
Drawings
Fig. 1 is a prior art dual power circuit fig. 1.
Fig. 2 is a dual power circuit prior art fig. 2.
Fig. 3 is a dual power circuit prior art fig. 3.
Fig. 4 is a schematic diagram of circuit connection provided by the present utility model.
Detailed Description
The utility model will be described in detail below with reference to the drawings and the specific embodiments.
Referring to fig. 4, the present utility model provides a dual-power low-loss circuit, comprising: resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, capacitor C1, MOS transistor Q2, transistor Q3, transistor Q4, and transistor Q5.
The drain electrode of the MOS tube Q1 and one end of the resistor R3 are connected in parallel to the external power supply 1. The source electrode of the MOS tube Q1, the source electrode of the MOS tube Q2 and one end of the resistor R2 are connected in parallel to electric equipment. The grid electrode of the MOS tube Q1 is connected with one end of the resistor R1, the drain electrode of the MOS tube Q2, one end of the capacitor C1 and the emitter electrode of the triode Q4 in parallel to be connected with the external power supply 2. The other end of the resistor R3 is connected with the emitter of the triode Q3. The collector of the triode Q3 is connected with the base of the triode Q3, the base of the triode Q4 and one end of the resistor R4. The collector of the triode Q4 is connected with one end of a resistor R5 and one end of a resistor R6. The grid electrode of the MOS transistor Q2 is connected with the other end of the resistor R2 and the collector electrode of the triode Q5. The base electrode of the triode Q5 is connected with the other end of the resistor R6. The emitter of the triode Q5, the other end of the capacitor C1, the other end of the resistor R4 and the other end of the resistor R5 are respectively grounded.
The MOS tube Q1 and the MOS tube Q2 are P-type field effect tubes.
The triode Q3 and the triode Q4 are PNP type triodes.
The triode Q5 adopts an NPN triode.
When the external power supply 1 has power input and the external power supply 2 has no input power, the MOS tube Q1 is turned on, the MOS tube Q2 is turned off, the external power supply 1 supplies power to the equipment, and meanwhile, the current of the external power supply 1 cannot flow backward to the external power supply 2. When the external power supply 2 has power input and the external power supply 1 has no input power, the MOS tube Q1 is turned off, the MOS tube Q2 is turned on, the external power supply 2 supplies power to the equipment, and meanwhile, the current of the external power supply 2 cannot flow backward to the external current 1. When the external power supply 1 and the external power supply 2 have power supply inputs, the external power supply 2 supplies power to the device.
The capacitor C1 has the function of avoiding the MOS transistor Q1 from entering an incomplete conduction state when the external power supply 1 has an initial stage of power input.
The circuit that triode Q3, triode Q4, resistance R3, resistance R4, resistance R5 constitute is in solving: when the external power supply 1 and the external power supply 2 have power input at the same time, but after one power supply is disconnected, the MOS tube Q1 or the MOS tube Q2 is prevented from entering an incomplete conduction state.
In summary, in the circuit provided by the utility model, the MOS tube is used for realizing the on-off period on the channel between the external power supply and the electric equipment, and when the MOS tube is completely conducted, the voltage drop on the MOS tube is far smaller than that of the diode, so that the power consumption can be effectively reduced. The components outside the MOS tube can ensure that the MOS tube in the circuit can be completely conducted or completely closed under all power supply scenes, so that the automatic seamless switching of power supply is realized, and the loss is avoided.
The foregoing description of the preferred embodiment of the utility model is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the utility model.
Claims (4)
1. A dual supply low loss circuit comprising: resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, capacitor C1, MOS transistor Q2, transistor Q3, transistor Q4, and transistor Q5;
the drain electrode of the MOS transistor Q1 is connected with one end of the resistor R3 in parallel to be connected with an external power supply 1, the source electrode of the MOS transistor Q1 is connected with the source electrode of the MOS transistor Q2 and one end of the resistor R2 in parallel to be connected with electric equipment, the grid electrode of the MOS transistor Q1 is connected with one end of the resistor R1, the drain electrode of the MOS transistor Q2, one end of the capacitor C1 and the emitter electrode of the triode Q4 in parallel to be connected with an external power supply 2, the other end of the resistor R3 is connected with the emitter electrode of the triode Q3, the collector electrode of the triode Q3 is connected with the base electrode of the triode Q4 and one end of the resistor R4, the collector electrode of the triode Q4 is connected with one end of the resistor R5 and one end of the resistor R6, the grid electrode of the MOS transistor Q2 is connected with the other end of the resistor R2, the emitter electrode of the triode Q5, the other end of the capacitor C1 and the other end of the resistor R5 are respectively grounded.
2. The dual-power low-loss circuit according to claim 1, wherein the MOS transistor Q1 and the MOS transistor Q2 are P-type field effect transistors.
3. The dual power low loss circuit according to claim 1, wherein said transistor Q3 and transistor Q4 are PNP transistors.
4. The dual power low loss circuit according to claim 1, wherein said transistor Q5 is an NPN transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320988629.6U CN219833835U (en) | 2023-04-25 | 2023-04-25 | Dual-power low-loss circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320988629.6U CN219833835U (en) | 2023-04-25 | 2023-04-25 | Dual-power low-loss circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219833835U true CN219833835U (en) | 2023-10-13 |
Family
ID=88278392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320988629.6U Active CN219833835U (en) | 2023-04-25 | 2023-04-25 | Dual-power low-loss circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219833835U (en) |
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2023
- 2023-04-25 CN CN202320988629.6U patent/CN219833835U/en active Active
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