CN219800853U - High-frequency IGBT chip of compound MPT structure - Google Patents
High-frequency IGBT chip of compound MPT structure Download PDFInfo
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- CN219800853U CN219800853U CN202321340530.1U CN202321340530U CN219800853U CN 219800853 U CN219800853 U CN 219800853U CN 202321340530 U CN202321340530 U CN 202321340530U CN 219800853 U CN219800853 U CN 219800853U
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- 150000001875 compounds Chemical class 0.000 title description 2
- 239000002131 composite material Substances 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 37
- 229920005591 polysilicon Polymers 0.000 claims description 36
- 238000001259 photo etching Methods 0.000 description 13
- 238000005530 etching Methods 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 238000002513 implantation Methods 0.000 description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 9
- 229910052796 boron Inorganic materials 0.000 description 9
- 238000000151 deposition Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 7
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 229910001092 metal group alloy Inorganic materials 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- QQMBHAVGDGCSGY-UHFFFAOYSA-N [Ti].[Ni].[Ag] Chemical compound [Ti].[Ni].[Ag] QQMBHAVGDGCSGY-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000010992 reflux Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
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Abstract
The utility model provides a high-frequency IGBT chip with a composite MPT structure, which comprises a drift region. According to the utility model, the cell size is reduced to 2.4 mu m through the micro-groove structure, meanwhile, the emitting groove cell is introduced into the active cell, on the basis of not changing the device structure such as the channel length, the proportion of the active cell and the emitting groove cell is reasonably distributed, the Miller capacitance (Cres) of the device is reduced, the proportion of the input capacitance (Cies) and the Miller capacitance (Cres) is increased, so that the controllability of the on-off of the IGBT under high-frequency application is increased, and the high-frequency performance is improved.
Description
Technical Field
The utility model relates to a high-frequency IGBT chip with a composite MPT structure.
Background
Currently, most IGBT high-frequency application chip cells mainly adopt a trench gate design, and the cell width is usually smaller than 3 microns. The polysilicon gate and the silicon substrate in the cell are separated by an extremely thin gate oxide layer, under the structure, various parasitic capacitances exist between the gate and the substrate, the trench density is greatly improved along with the reduction of the trench size, the parasitic capacitance is increased, and particularly under the high-frequency application, the controllability of the on-off of the IGBT is greatly reduced, so that the high-frequency switching characteristic of the chip is not facilitated.
As disclosed in publication No. CN102569373B, an IGBT with low on saturation voltage drop and a method for manufacturing the same are disclosed, in which a trench cell structure is adopted in an active region, a trench grows in a drift region of a first conductivity type under a layer of a second conductivity type, an insulating gate oxide layer is grown in the trench, and conductive polysilicon is filled in the trench, so that the polysilicon gate and a silicon substrate are oxidized by an extremely thin gate, and as the size of the trench is reduced, the density of the trench is greatly increased, resulting in an increase in parasitic capacitance.
Disclosure of Invention
In order to solve the technical problems, the utility model provides a high-frequency IGBT chip with a composite MPT structure.
The utility model is realized by the following technical scheme.
The utility model provides a high-frequency IGBT chip with a composite MPT structure, which comprises a drift region; the drift region front processing has a plurality of bars oxide layer, and bars oxide layer center is the U type groove, is equipped with first polycrystalline silicon electrode in the inslot, the front of drift region still is equipped with the Pbase district, and the Pbase district wraps up the upper end part of bars oxide layer, the terminal surface of Pbase district is equipped with a plurality of P+ cell district, and P+ cell district and bars oxide layer are established in turn and are being arranged, connect through active N+ district between P+ cell district and the bars oxide layer of Pbase district edge, the front of Pbase district is equipped with the inner insulation layer, and a plurality of inner insulation layers cover respectively on bars oxide layer, and the front of Pbase district still is equipped with the projecting pole and covers the front of Pbase district completely, the back of drift region is equipped with N+ field cut-off region, P+ back current collector in proper order.
The first polysilicon electrode completely fills the center of the gate oxide layer.
The resistivity of the N+ field cut-off region is 10-14Ω cm.
The junction depth thickness of the P+ back collector region is 1-2 mu m.
The junction depth of the Pbase region is 4-5 mu m.
The manufacturing steps of the chip are that,
1. lightly doped fused monocrystalline silicon wafer is selected as 1
2. Forming a Pbase region with junction depth of 4 μm on the front surface of the drift region;
3. photoetching a groove gate on the front surface of the drift region, oxidizing to form a gate oxide layer, and then depositing polysilicon in the groove gate;
4. performing gate wiring photoetching, etching a polysilicon gate, and photoresist stripping after forming a first polysilicon electrode and a second polysilicon electrode;
5. an active N+ region with the junction depth of 0.3-0.6 mu m and a P+ cell region with the junction depth of 1-2 mu m are manufactured on a Pbase region;
6. silicon oxide and BPSG deposition are carried out at the front gate oxide layer of the drift region, then high-temperature reflow is carried out to form an inner insulating layer, and then a trench gate contact hole which is in contact with the first polysilicon electrode is processed in the inner insulating layer; a dummy trench gate contact hole and an emitter contact hole connected with the second polysilicon electrode;
7. evaporating an Al layer of 3.5-4.6 mu m on the front surface of the drift region (1), connecting with a grid electrode and an emitter electrode, separating the metal of the grid electrode and the metal of the emitter electrode through photoetching, and forming the emitter electrode and the grid electrode by metal alloy;
8. deposit thickness ofPI deposition is carried out after photoetching, PI imidization is carried out after photoetching and development;
9. thinning the back surface of the drift region to a thickness of 65-80 mu m, and releasing wafer stress;
10. performing phosphorus injection on the back of the drift region to form an N+ field stop region, and then performing boron injection to form a P+ back collector region;
11. and finally, depositing titanium nickel silver on the back surface of the drift region to form a collector electrode.
The formation process of the Pbase region comprises the following steps:
grown on the front surface of the drift region by dry-wet-dry modeThe field oxide layer is subjected to dry-wet oxidation for 30, 100 and 30 minutes in sequence at the temperature of 1000-1200 ℃;
carrying out active region photoetching to form an active region window, etching a field oxide layer and removing photoresist;
performing boron ion implantation in the window of the active region to form a Pbase region, wherein the implantation energy is 75-85 keV, the angle is 7 DEG, and the dosage is 7e 13-9 e13 cm -2 ；
Pushing junction in Pbase region at 1000-1200 deg.c for 70-80 min and junction depth of 3-8.5 microns, and introducing oxygen to grow into the junction to obtain the junctionIs used as a mask for etching the trench.
The processing process of the active N+ region and the P+ cell region is as follows:
etching an N+ active region window;
pushing junction after phosphorus injection in N+ active region window, wherein injection energy is 30keV, angle is 7 DEG, and dosage is 8e 12-8 e19 cm -2 The junction pushing temperature is 850-1000 ℃ and the junction pushing time is 20-40 min;
etching a P+ window;
performing boron ion implantation, removing photoresist after the implantation, wherein the implantation energy is 150keV, the angle is 0 DEG, and the dosage is 1e 18-2 e19 cm -2 。
The thicknesses of the silicon nitride and the BPSG in the steps are respectivelyThe high temperature reflux temperature was 950℃for 30min.
The thickness of the titanium nickel silver in the step 11 is in turn
The utility model has the beneficial effects that: through the micro-groove structure, the cell size is reduced to 2.4 mu m, meanwhile, the emitting groove cell is introduced into the active cell, on the basis of not changing the device structure such as the channel length, the proportion of the active cell and the emitting groove cell is reasonably distributed, the Miller capacitance (Cres) of the device is reduced, the proportion of the input capacitance (Cies) and the Miller capacitance (Cres) is increased, and therefore the controllability of the on-off of the IGBT under high-frequency application is increased, and the high-frequency performance is improved. The input capacitance and the transfer capacitance are allocated to allocate high frequency.
Drawings
FIG. 1 is a schematic diagram of the structure of the present utility model;
in the figure: the device comprises a 1-N-drift region, a 2-N+ field stop region, a 3-P+ back collector region, a 4-P+ cell region, a 5-Pbase region, a 6-active N+ region, a 7-gate oxide layer, an 8-first polysilicon electrode, a 9-inner insulating layer, a 10-emitter, an 11-collector and a 12-second polysilicon electrode.
Detailed Description
The technical solution of the present utility model is further described below, but the scope of the claimed utility model is not limited to the above.
As shown in fig. 1, a high-frequency IGBT chip of a composite MPT structure and a method for manufacturing the same, including a drift region 1; the front surface of the drift region 1 is provided with a plurality of gate oxide layers 7, the center of the gate oxide layer 7 is provided with a U-shaped groove, a first polysilicon electrode 8 and a second polysilicon electrode 12 are respectively arranged in the groove, in the figure, a first polysilicon electrode 8 is arranged in a first third groove gate, the first polysilicon electrode 8 is connected with a grid, a parasitic capacitance Cgc formed between the first polysilicon electrode 8 and a collector 11 forms a Miller capacitance (Cres), a second middle polysilicon electrode 12 is arranged in the second groove, and the parasitic capacitance formed by the second polysilicon electrode 12 and an emitter is called Cge and forms a device input capacitance Cies together with the Cgc; by connecting part of polysilicon with the emitter, cgc forming the Miller capacitance is converted into Cge, so that the input capacitance Cies of the device is increased, the Miller capacitance Cres of the device is reduced, the capacitance composition of the device is improved, high-frequency use conditions are met, and the number of the first polysilicon electrode 8 and the second polysilicon electrode 12 can be adjusted according to different use frequencies in the chip manufacturing process.
The first polysilicon electrode 8 and the second polysilicon electrode 12 extend outwards out of the cell region and are connected with the grid metal bus outside the cell region, so that the voltages of the cell grid and the grid bus are inhibited, and the consistency of cell switching is ensured.
Under the high-frequency circuit, when the chip is manufactured, part of polysilicon gate is connected with an emitter to form an emitting grid cell, the parasitic capacitance Cgc is converted into the parasitic capacitance Cec, the Miller capacitance is reduced, and the input capacitance is improved. In the IGBT turn-on process, the smaller Cgc reduces the charge for driving the grid electrode to reach the threshold voltage, firstly, the power consumption for driving the IGBT at high frequency can be reduced, and secondly, the turn-on time under the same grid electrode driving condition can be reduced, so that the working frequency of the input capacitor is increased; during the turn-off process of the IGBT, vce changes rapidly, so that the miller capacitance Cgc begins to discharge, forming a current Igc, which generates a voltage across the gate resistor, and if the voltage is greater than the threshold voltage, the IGBT will be in an on state, and the whole circuit will have a risk of burning. The miller capacitance Cgc is reduced, which reduces the turn-off current Igc, thereby enhancing the controllability of the device when turned off.
As shown in fig. 1, the first polysilicon electrode 8 completely fills the center of the gate oxide layer 7.
The resistivity of the N+ field stop region 2 is 10-14Ω cm.
The junction depth thickness of the P + back-collector region 3 is 1-2 μm.
The junction depth of the Pbase region 5 is 4-5 μm.
Example 1: the preparation method of the high-frequency IGBT chip with the composite MPT structure comprises the following steps of,
1. a lightly doped zone-melting monocrystalline silicon wafer is used as an N-drift region, and the doping concentration is 6e 13-8 e13.
2. Thermal growthAnd (5) pre-oxidizing the layer.
3. And (4) performing P+ ring region oxide layer photoetching, and reserving photoresist.
4. And (3) performing terminal region boron ion implantation with energy of 60keV, angle of 7 degrees and dose of 5e13, etching the pre-oxidation layer after implantation, and photoresist removing.
5. And (5) pushing the junction in the P+ ring region, and simultaneously introducing oxygen to grow a field oxide layer. Dry-wet dry growthThe field oxide layer has an oxidation time of 30+100+30 minutes, a temperature of 1100 ℃, and a junction depth of about 4 μm.
6. And (5) carrying out active region photoetching, etching the field oxide layer and photoresist removing.
7. Performing boron ion implantation in the Pbase region 5 with the implantation energy of 80keV, the angle of 7 degrees and the dosage of 7e 13-9 e13, then performing push junction in the Pbase region, introducing oxygen in the push junction process to grow an oxide layer, wherein the push junction temperature is 1100 ℃, the time is 70-80 min, the junction depth is about 3-3.5 mu m, and the thickness of the oxide layer is aboutUsed as a mask for etching trenches.
8. And (5) carrying out groove gate region photoetching, etching an oxide layer and photoresist removing.
9. Etching silicon to form a groove structure, the bottom is smooth, the depth is 3.5-5 mu m,
10. thermal growth sacrificialAfter oxidizing the layer, the layer is oxidized and cleaned.
11. Thermally grown gate oxide layer 7 thickness
12. Polysilicon deposition, backfilling the trench structure 8.
13. And performing gate wiring lithography.
14. And etching the polysilicon to form a polysilicon gate, and removing photoresist.
15. And (5) carrying out photoetching on the active N+ region 6.
16. And (3) performing phosphorus injection and junction pushing on the active N+ region, wherein the injection energy is 30keV, the angle is 7 degrees, the dosage is 8e15, and the junction pushing temperature is 950 ℃ and the time is 30min after photoresist removal, and the junction depth is 0.3-0.6 mu m.
17. And (3) performing boron ion implantation in the P+ region 4, wherein the implantation energy is 150keV, the angle is 0 degree, and the dose is 2e15, and then performing photoresist stripping.
18. Performing chemical vapor deposition of silicon oxide and BPSG with thickness of respectivelyAnd->Then, high-temperature reflux is carried out for 30min (9) at 950 ℃.
19. And (3) performing metal hole photoetching, respectively processing a trench gate contact hole in contact with the first polysilicon electrode 8, a false trench gate contact hole and an emitter contact hole which are connected with the second polysilicon electrode (2) in the inner insulating layer 9, and removing photoresist.
20. And (3) shallow boron ion implantation in the P+ region is carried out, the implantation energy is 60keV, the angle is 7 degrees, the dose is 3e15, and then high-temperature activation is carried out by using a rapid annealing furnace, wherein the temperature is 900 ℃ and the time is 30-45 s.
21. Front metal Al evaporation was performed to a thickness of 4 μm.
22. An Al layer of 3.5-4.6 μm is evaporated on the front of the drift region 1 and connected with the grid and the emitter, and then the grid metal and the emitter metal are separated by photoetching.
23. And forming a front metal alloy 10, forming an emitter and a grid by using the metal alloy, wherein the temperature is 450 ℃ and the time is 30min.
24. Depositing silicon nitride to a thickness of about
25. And (5) performing silicon nitride photoetching, etching and photoresist removal.
26. PI deposition
27. Performing PI lithography and development
28. PI imidization
29. The backside thinning is performed to a thickness of about 70 μm and the wafer stress is relieved.
30. And (3) performing boron implantation in a back surface N+ field stop region (2), wherein the implantation energy is 400-550 keV, the angle is 7 degrees, and the dosage is 8e 12-1 e13.
31. And (3) performing boron implantation (3) of the back P+ collector region, wherein the implantation energy is 30keV, the angle is 7 degrees, and the doses are 5e 13-1 e14.
32. The rapid annealing furnace activates ions in the P+ collector region and the N+ field stop region, and the temperature is 950 ℃ and the time is 30s.
33. Depositing Ti-Ni-Ag on the back surface to obtain the following thicknessesAnd forming a back metal electrode.
Claims (5)
1. The high-frequency IGBT chip with the composite MPT structure comprises a drift region (1), and is characterized in that: the front surface of the drift region (1) is provided with a plurality of gate oxide layers (7), the center of the gate oxide layers (7) is a U-shaped groove, a plurality of first polysilicon electrodes (8) and a plurality of second polysilicon electrodes (12) are arranged in the groove, and the first polysilicon electrodes (8) are connected with a grid electrode to form a trench grid electrode; the second polysilicon electrode (12) is connected with the emitter to form a false trench gate; the drift region (1) is characterized in that a Pbase region (5) is further arranged on the front face of the drift region (1), the Pbase region (5) wraps the upper end portion of the gate oxide layer (7), a plurality of P+ cell regions (4) are arranged on the end face of the Pbase region (5), the P+ cell regions (4) and the gate oxide layer (7) are alternately arranged, the P+ cell regions (4) at the edge of the Pbase region (5) are connected with the gate oxide layer (7) through an active N+ region (6), an inner insulating layer (9) is arranged on the front face of the Pbase region (5), a plurality of inner insulating layers (9) are respectively covered on the gate oxide layer (7), an emitter (10) is further arranged on the front face of the Pbase region (5), and an N+ field stop region (2), a P+ back region (3) and a collector (11) are sequentially arranged on the back face of the drift region (1).
2. The high frequency IGBT chip of the composite MPT structure of claim 1, wherein: the first polysilicon electrode (8) completely fills the center of the gate oxide layer (7).
3. The high frequency IGBT chip of the composite MPT structure of claim 1, wherein: the resistivity of the N+ field stop region (2) is 10-14Ω & cm.
4. The high frequency IGBT chip of the composite MPT structure of claim 1, wherein: the junction depth thickness of the P+ back collector region (3) is 1-2 mu m.
5. The high frequency IGBT chip of the composite MPT structure of claim 1, wherein: the junction depth of the Pbase region (5) is 4-5 mu m.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202321340530.1U CN219800853U (en) | 2023-05-29 | 2023-05-29 | High-frequency IGBT chip of compound MPT structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202321340530.1U CN219800853U (en) | 2023-05-29 | 2023-05-29 | High-frequency IGBT chip of compound MPT structure |
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