CN219180510U

CN219180510U - Chip stacking and packaging structure and flash memory

Info

Publication number: CN219180510U
Application number: CN202222980515.5U
Authority: CN
Inventors: 孙成思; 刘小刚; 覃云珍; 李振华
Original assignee: Biwin Storage Technology Co Ltd
Current assignee: Biwin Storage Technology Co Ltd
Priority date: 2022-11-09
Filing date: 2022-11-09
Publication date: 2023-06-13
Anticipated expiration: 2032-11-09

Abstract

The utility model discloses a chip stacking and packaging structure and a flash memory. Meanwhile, a multi-IO parallel transmission mode is adopted on the packaging body, so that a faster interface transmission speed is realized.

Description

Chip stacking and packaging structure and flash memory

Technical Field

The present utility model relates to the field of flash memory chips, and in particular, to a chip stacking and packaging structure and a flash memory.

Background

Currently, stacking of flash memory chips mainly adopts single-row stacking, and IO interfaces mainly adopt 8 bit/1 channel or 16 bit/2 channel. The stacking mode has limited capacity due to thickness, and has limited IO number and no advantage of the read-write speed of a single chip.

Disclosure of Invention

The utility model mainly aims to provide a chip stacking and packaging structure and a flash memory, and aims to solve the problem that the capacity of the existing single-row stacked flash memory chip is highly limited.

In order to achieve the above object, the present utility model provides a chip stack package structure, which includes a substrate and unit chips disposed on the substrate, wherein the substrate includes a plurality of signal channel interfaces, each two unit chips are stacked to form a chip pair, and each chip pair is electrically connected to the substrate and is connected to one signal channel interface through a signal line;

the chip stacking and packaging structure comprises at least two chip pairs, and each chip pair is independently arranged on the substrate;

alternatively, the chip pair stack is disposed on the substrate and forms a chip set, and the chip stack package structure includes at least two chip sets.

In some embodiments, the chip stack package structure includes two chip sets disposed side by side along a length direction of the substrate, each of the chip sets includes at least two chip pairs disposed in a stacked manner, and unit chips in each of the chip sets are sequentially stacked upward from a surface of the substrate.

In some embodiments, the unit chips in the chipset are stacked in order offset from bottom to top to one side of the substrate to expose the upper surface of the other side of the unit chips; the upper surface of the other side of the unit chip in the chipset is electrically connected with the substrate through a wire.

In some embodiments, the offset directions of the two chip sets are opposite, and the signal channel interface and the power interface corresponding to each chip set on the substrate are located on the same side of the corresponding chip set.

In some embodiments, the two chipsets are offset away from each other, the power interface and the signal path interface being located in the center of the substrate.

In some embodiments, each of the chip sets includes two chip pairs, respectively, the chip pairs in the same chip set transmitting data in parallel.

In some embodiments, at least one of the chip sets further includes a cushion disposed between two chip pairs, the cushion being a fow cushion.

In some embodiments, the pad layer is offset in a direction opposite to the offset direction of the die below it.

In some embodiments, the chip stack package structure includes a plurality of columns of chip sets arranged side by side along a width direction of the substrate, each column of chip sets includes two chip sets, and offset directions of unit chips on two adjacent chip sets in the width direction of the substrate are the same.

The utility model also provides a flash memory, which comprises the chip stacking and packaging structure.

According to the utility model, the unit chips are arranged in a plurality of rows and coexist in a single package, each row is stacked in a plurality of layers to realize single chip large capacity, and meanwhile, a multi-IO parallel transmission mode is adopted on the package to realize faster interface transmission speed.

Drawings

FIG. 1 is a schematic diagram of a chip package on package structure according to an embodiment of the utility model;

FIG. 2 is a schematic diagram of another embodiment of a stacked chip package structure according to the present utility model;

FIG. 3 is a schematic diagram of another embodiment of a stacked chip package structure according to the present utility model;

FIG. 4 is a schematic diagram of another embodiment of a stacked chip package structure according to the present utility model;

fig. 5 is a side view of the stacked package structure of the embodiment of fig. 4.

The achievement of the objects, functional features and advantages of the present utility model will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

The following description of the embodiments of the present utility model will be made more clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

It should be noted that all directional indicators, such as up, down, left, right, front, and rear … …, are merely used to explain a specific posture, that is, a relative positional relationship between the components, a movement condition, and the like as shown in the drawings, and if the specific posture is changed, the directional indicator is changed accordingly.

It will also be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present utility model.

The utility model also proposes a chip stack package structure, referring to fig. 1 to 5, which includes a substrate 10 and at least two chip sets disposed on the substrate 10; the substrate 10 includes a plurality of signal channel interfaces, and the chipset includes at least one chip pair, which is formed by stacking two unit chips 20; each of the chip pairs is electrically connected to the substrate 10, and is connected to one of the signal channel interfaces through a signal line, respectively.

In this embodiment, the stacked package structure of the chip includes two ways, one of which is to set a plurality of separate chip pairs on the substrate 10, one unit chip 20 of each chip pair is attached to the substrate 10, and each chip set is electrically connected to the signal channel interface through a signal line, so as to realize parallel signal transmission of the plurality of chip pairs. The unit chips 20 of each chip pair are electrically connected to the power supply interface on the substrate 10 by wire bonding. The packaging structure is suitable for chip specifications with thinner thickness and larger size. The chip pairs are typically provided in an even number, and an array of chip pairs may be provided on the substrate 10.

In another package structure, a plurality of chip pairs are stacked in one chip set, a plurality of chip sets are disposed on the substrate 10, the unit chip 20 at the bottommost layer of each chip set is attached to the substrate 10, and data are transmitted in parallel between the chip pairs. In order to control the thickness of the chip, the packaging mode is provided with a plurality of chip sets in the horizontal direction, so that the flash memory has larger data capacity.

The present utility model realizes a single chip large capacity by arranging and coexisting the unit chips 20 in a single package, each row being stacked in multiple layers. Meanwhile, a multi-IO parallel transmission mode is adopted on the packaging body, so that a faster interface transmission speed is realized.

In some embodiments, referring to fig. 1 and 2, the chip stack package structure includes two chip sets disposed side by side along a length direction of the substrate 10, each of the chip sets includes at least two chip pairs disposed in a stacked manner, and unit chips 20 in each of the chip sets are disposed in a stacked manner upward in order from a surface of the substrate 10.

In some embodiments, referring to fig. 1 and 2, the unit chips 20 in the chipset are stacked in order offset from bottom to top toward one side of the substrate 10 to expose the upper surface of the other side of the unit chips 20; the upper surface of the other side of the unit chip 20 in the chipset is electrically connected to the substrate 10 through a wire.

In this embodiment, the chip stacking package structure includes two chip sets disposed side by side, the two chip sets are a first chip set and a second chip set, and unit chips 20 in the chip sets are sequentially stacked upward from the surface of the substrate 10. The unit chips 20 in the first chipset are stacked in a shifting manner from bottom to top to one side in order to form a first shifting side; an end of the unit chip 20 in the first chipset remote from the first offset side is electrically connected to the substrate 10 through the wire; the unit chips 20 in the second chip set are stacked in a shifting manner from bottom to top to one side in order to form a second shifting side; the end of the unit chip 20 of the second chip set remote from the second offset side is electrically connected to the substrate 10 through the wire.

In some embodiments, referring to fig. 1 and 2, the offset directions of the two chip sets are opposite, and the signal channel interface corresponding to each chip set on the substrate 10 is located on the same side of the corresponding chip set as the power interface. In this embodiment, the first chipset and the second chipset are arranged side by side, the first chipset is located at the left side of the second chipset, the first chipset is offset to the right, and the second chipset is offset to the left. The signal channel interface and the power interface corresponding to the first chip set on the substrate 10 are positioned on the left side of the first chip set; correspondingly, the signal channel interface and the power interface corresponding to the second chipset on the substrate 10 are located on the right side of the second chipset, and the chipset is connected with the signal channel interface and the power interface through wires.

In some embodiments, referring to fig. 1 and 2, two of the chip sets are offset away from each other, the power interface and the signal path interface being provided in the center of the substrate 10. In the present embodiment, 8 unit chips 20, i.e., die1-die8, may be provided. Wherein die1-die4 forms one chipset and die5-die8 forms another chipset, the two chipsets are arranged side by side, and die1-die4 is positioned on the left side of die5-die 8. The die 20 in die1-die4 are offset from bottom to top to left; the die 20 in die5-die8 are offset from bottom to top to right; whereby the signal path interface and the power interface are located between the two chipsets and in the center of the substrate 10.

In some embodiments, referring to fig. 1-2, each of the chip sets includes two chip pairs, the chip pairs in the same chip set transmitting data in parallel. Wherein die1 and die2 are electrically connected with the signal channel interface, die1 and die2 are used as the connection chips of the first channel, die3 and die4 are also electrically connected with the signal channel interface, and die3 and die4 are used as the connection chips of the third channel. Die1/2 and Die3/4 may transmit data in parallel. Wherein die5 and die6 connect the second channel and die7 and die8 connect the fourth channel.

In this embodiment, there are 8 data lines on a Die, and the 8 data lines form a signal channel connected to the data lines; if there are now two channels, but 4 Die, then one channel uses two Die, which are connected by data lines. The data transmission device comprises 8 data lines and signal lines, wherein the 8 data lines and the signal lines form a channel, the other 8 data lines and the signal lines form a channel, and the two channels are not mutually interfered and can transmit data together.

In some embodiments, referring to fig. 3, at least one of the chip sets further includes a cushion layer disposed between two chip pairs, the cushion layer being a fow cushion layer. The first chip set further comprises a first cushion layer arranged between the two chip pairs, the second chip set further comprises a second cushion layer arranged between the two chip pairs, and the first cushion layer and the second cushion layer are fow cushion layers. The offset direction of the first cushion layer is opposite to the first offset direction, and the offset direction of the second cushion layer is opposite to the second offset direction. For example, the first pad layer is aligned with the unit chip 20 above, i.e., the first pad layer and the unit chip 20 above may not be offset with respect to the first pad layer.

In this embodiment, the FOW (film on wire) process refers to the fact that the wire can be buried. In contrast to the left-hand stacking of fig. 2, the third layer Die may not be stacked in a back step, but the lines of the second layer may be buried with the FOW, and the third layer may be attached to the FOW, whereby the fourth layer of the third layer may not cause the package size to become large.

In some embodiments, the chip stacking package structure includes a plurality of columns of chip sets disposed side by side along the width direction of the substrate 10, each column of chip sets includes two chip sets, and the offset directions of the unit chips 20 on two adjacent chip sets in the width direction of the substrate 10 are the same.

In this embodiment, referring to fig. 4 and 5, the chip stack package structure includes four chip pairs, and each of the chip pairs is disposed in an array on the substrate 10. The four chip pairs are arranged in two rows and two columns, die1 and die2 are connected with the first channel, die3 and die4 are connected with the third channel, and die5 and die6 are connected with the second channel; die7 and die8 connect to the fourth channel. There may be more columns, not limited to 4, with 2 chip pairs arranged in each column, with the offset of the cells in the two chip pairs being identical in the lateral direction and opposite in the longitudinal direction.

The utility model also provides a flash memory, which comprises the chip stacking and packaging structure. The present utility model realizes a single chip large capacity by arranging and coexisting the unit chips 20 in a single package, each row being stacked in multiple layers. Meanwhile, a multi-IO parallel transmission mode is adopted on the packaging body, so that a faster interface transmission speed is realized.

The above description of the preferred embodiments of the present utility model should not be taken as limiting the scope of the utility model, but rather should be understood to cover all modifications, variations and adaptations of the present utility model using its general principles and the following detailed description and the accompanying drawings, or the direct/indirect application of the present utility model to other relevant arts and technologies.

Claims

1. The chip stacking and packaging structure is characterized by comprising a substrate and at least two chip groups arranged on the substrate;

the substrate comprises a plurality of signal channel interfaces, the chip set comprises at least one chip pair, and the chip pair is formed by stacking two unit chips; the unit chips in the chip set are sequentially stacked upwards from the upper surface of the substrate;

each chip pair is electrically connected with the substrate respectively and is connected with one signal channel interface through a signal wire respectively.

2. The chip stack package structure according to claim 1, wherein the chip stack package structure includes two chip sets arranged side by side in a longitudinal direction of the substrate, each of the chip sets includes at least two chip pairs arranged in a stacked manner, and unit chips in each of the chip sets are stacked up in order from a surface of the substrate.

3. The chip stack package structure according to claim 2, wherein the unit chips in the chip set are sequentially stacked with an offset to one side of the substrate from bottom to top to expose an upper surface of the other side of the unit chips; the upper surface of the other side of the unit chip in the chipset is electrically connected with the substrate through a wire.

4. The chip stack package structure of claim 3, wherein the offset directions of the two chip sets are opposite, and the signal channel interface and the power interface of each chip set are located on the same side of the corresponding chip set.

5. The chip stack package structure of claim 4, wherein two of the chip sets are offset away from each other, the power interface and the signal path interface being disposed in a center of the substrate.

6. The chip stack package structure according to claim 2, wherein each of the chip pairs includes two chip pairs, and the chip pairs in the same chip group transmit data in parallel.

7. The chip stack package structure of claim 3, wherein at least one of the chip sets further comprises a cushion layer disposed between two chip pairs, the cushion layer being a fow cushion layer.

8. The chip stack package structure according to claim 7, wherein the pad layer is offset in a direction opposite to an offset direction of the unit chip thereunder.

9. The chip stack package structure according to claim 3, wherein the chip stack package structure includes a plurality of columns of chip sets arranged side by side in a width direction of the substrate, each column of chip sets including two of the chip sets, offset directions of unit chips on two adjacent chip sets in the width direction of the substrate are the same.

10. A flash memory comprising the chip stack package structure of any one of claims 1-9.