CN219180509U - Chip packaging structure and memory - Google Patents

Abstract

The utility model discloses a chip packaging structure and a memory, wherein the chip packaging structure comprises: a substrate; at least two chip groups, adjacent to each other, are arranged on the substrate, and the chips in each chip group are stacked in sequence in a step shape; and the heightening layer is arranged in at least one chip group so that part or all chips between at least two chip groups form high-low dislocation. The chip packaging structure comprises a substrate, at least two chip sets and a pad layer, wherein chips in each chip set are stacked in sequence in a step shape in the vertical direction of the substrate, the pad layer is arranged in at least one chip set, so that part or all of the chips between the at least two chip sets form high-low dislocation, a wire bonding space is provided by using the dislocation height difference, wire bonding can be performed between each chip set in the wire bonding space without mutual influence, and therefore, the adjacent chip sets do not need to be arranged at a larger interval, the design size of the substrate can be correspondingly reduced, and the packaging size is reduced.

Description

Chip packaging structure and memory

Technical Field

The present utility model relates to the field of chip packaging, and in particular, to a chip packaging structure and a memory.

Background

Multi-chip stacking is a basic technology of three-dimensional packaging, and particularly for storage products, the multi-layer stacking technology determines the degree to which the product size can be reduced, and the integration level of the three-dimensional packaging module.

Chips with different specifications, types and sizes are stacked, a certain space needs to be reserved for preventing mutual contact interference between the wires and the chips during wire bonding, but the current trend of the package size is more miniaturization, and how to package more chips in smaller size is a current technical difficulty.

In the existing chip packaging technology, chips are obliquely mounted on a substrate, and adjacent chip groups are required to be arranged at larger intervals to wire with reserved space, so that the space of the required occupied substrate is increased, and the packaging size of a product is large.

Disclosure of Invention

The utility model mainly aims to provide a chip packaging structure, which aims to solve the problem of large packaging size of the existing chip structure.

In order to achieve the above object, the present utility model provides a chip package structure, comprising:

a substrate;

at least two chip sets are adjacently arranged on the substrate, and chips in each chip set are stacked in sequence in a step shape;

and the heightening layer is arranged in at least one of the chip sets, so that part or all of chips between at least two chip sets form high-low dislocation.

In some embodiments, a spacer is provided on the substrate, the spacer forming the elevated layer to support a plurality of the chips in the chipset.

In some embodiments, adjacent ones of the at least two chipsets are tilted in the same direction.

In some embodiments, the chip set includes at least two chip groups sequentially disposed from bottom to top, each of the chip groups including two adjacent chips.

In some embodiments, the elevated layer is a Fow layer and is disposed between two adjacent groups of chips.

In some embodiments, the elevated layer is a Dummy layer and is disposed between two adjacent groups of chips.

In some embodiments, adjacent ones of the at least two chipsets are relatively tilted.

In some embodiments, the chips below each of the chip groups are connected to the chip above the chip groups and the substrate by bonding wires, respectively.

In some embodiments, adjacent chips between adjacent ones of the chip groupings are connected by bond wires.

The utility model further provides a memory, which comprises a main board and the chip packaging structure, wherein the chip packaging structure is arranged on the main board.

The chip packaging structure comprises a substrate, at least two chip sets and a pad layer, wherein chips in each chip set are stacked in sequence in a step shape in the vertical direction of the substrate, the pad layer is arranged in at least one chip set, so that part or all of the chips between the at least two chip sets form high-low dislocation, a wire bonding space is provided by using the dislocation height difference, wire bonding can be performed between each chip set in the wire bonding space without mutual influence, and therefore, the adjacent chip sets do not need to be arranged at a larger interval, the design size of the substrate can be correspondingly reduced, and the packaging size is reduced.

Drawings

FIG. 1 is a schematic diagram of a chip package structure according to an embodiment of the utility model;

FIG. 2 is a schematic diagram of a chip package structure according to another embodiment of the present utility model;

fig. 3 is a schematic structural diagram of a chip package structure according to another embodiment of the utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made more clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present utility model are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.

It will also be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present utility model.

The inventor researches and discovers that in the prior dislocation lamination packaging technology, chips are obliquely attached to a substrate, adjacent chip groups are required to be arranged at larger intervals to wire with reserved space, and when the chips are stacked higher, the space of the substrate is required to be occupied to be larger, so that the packaging size of the product is larger.

The present utility model provides a chip package structure, as shown in fig. 1 to 3, which includes:

a substrate 100;

at least two chip sets 200 disposed adjacently on the substrate 100, wherein the chips 210 in each chip set 200 are stacked in a step-like manner;

the spacer layer 300 is disposed in at least one of the chip sets 200, so that part or all of the chips 210 between at least two of the chip sets 200 are staggered.

In this embodiment, the chip package structure is a three-dimensional package of a memory chip, and specifically, the three-dimensional package mainly comprises a substrate 100, at least two chip sets 200 and a raised layer 300, wherein the upper surface of the substrate 100 is divided into mounting positions for mounting the at least two chip sets 200, and in addition, other mounting positions may be further divided on the substrate 100 for mounting other elements, which is not explicitly described herein. When packaging is performed, the substrate 100 is further provided with a packaging layer, and the packaging layer is attached to the substrate 100 to realize packaging of each element, such as at least two chip sets 200 and a pad layer 300, on the substrate 100. Wherein, the packaging layer is preferably made of epoxy resin material.

Each of the chip sets 200 includes a plurality of chips 210, and the number of chips 210 of the chip sets 200 may be the same or different, which is not limited. In the chip set 200, the chips 210 are stacked in a stepwise manner in order to form a misalignment between the chips 210 for connection routing between the chips 210, and finally the routing is connected to the substrate 100. Also, the stepped stacking of chips 210 in the chip set 200 makes the chip set 200 tilt toward a certain direction (e.g., left or right direction). The inclination directions of the chip sets 200 in the at least two chip sets 200 may be the same or different. The bump height layer 300 is located in at least one chipset 200 so that part or all of the chips 210 between at least two chipsets 200 are staggered in height, and the routing space is provided without increasing the size of the substrate 100, thereby increasing the packaging capability of the uniform size substrate 100. The pad layer 300 may be located at the bottom of the chipset 200, or may be located between the chipsets 200, according to the specific situation.

The chip packaging structure of the utility model is composed of a substrate 100, at least two chip sets 200 and a raised layer 300, wherein chips 210 in each chip set 200 are stacked in a ladder-shaped manner in the vertical direction of the substrate 100, the raised layer 300 is arranged in at least one chip set 200, so that part or all of the chips 210 between the at least two chip sets 200 form height dislocation, a wire bonding space is provided by using the dislocation height difference, and wire bonding can be performed in the wire bonding space between each chip set 200 without mutual influence, thereby ensuring that the adjacent chip sets 200 do not need to be arranged at a larger interval, and correspondingly reducing the design size of the substrate 100, thereby reducing the packaging size.

In some embodiments, as shown in fig. 1, a spacer 310 is provided on the substrate 100, the spacer 310 forming a raised layer 300 to support a plurality of chips 210 in the chipset 200. In this embodiment, the exemplary chipset 200 is two, each chipset 200 includes 4 chips, one chipset 200 having chips 210-1 through 210-4, and the other chipset 200 having chips 210-5 through 210-8, respectively. A spacer 310 is provided on the substrate 100, and the spacer 310 forms a spacer layer 300 for supporting a plurality of chips 210 in the chipset 200. For example, as shown in FIG. 1, pad 310 supports a chipset 200 comprised of chips 210-5 through 210-8. The spacer 310 is disposed between one of the chip sets 200 and the substrate 100, and forms a height dislocation between all the chips 210 of the two chip sets 200, and a wire bonding space is provided by using the dislocation height difference, so that the two chip sets 200 can be wire bonded without mutual influence, and the package size is reduced. Preferably, the spacer 310 is a silicon wafer or an aluminum sheet.

In some embodiments, adjacent ones 200 of the at least two chipsets 200 are tilted in the same direction. In this embodiment, as shown in fig. 1, the number of the chip sets 200 is two, and the step structures formed by the chips 210 in the two chip sets 200 are all inclined to the left.

The left and right sides in this embodiment refer to the left and right sides in the drawing, and indicate one relative direction, and do not indicate the absolute direction.

In some embodiments, as shown in fig. 1-3, the chipset 200 includes at least two chip groupings disposed in sequence from bottom to top, each chip grouping including two adjacent chips. In this embodiment, the exemplary grouping of chips in each chipset 200 is two, wherein in one chipset 200, chip 210-1 and chip 210-2 are grouped into one chip, and chip 210-3 and chip 210-4 are grouped into one chip. In another chipset 200, chip 210-5 and chip 210-6 are grouped into one chip and chip 210-7 and chip 210-8 are grouped into one chip. Each chip set 200 includes two chip groups sequentially arranged from bottom to top, each chip group includes two adjacent chips 210, and data transmission signals of the two chips 210 are connected through one channel.

In some embodiments, as shown in FIG. 2, the elevated layer 300 is a Fow layer 320 and is disposed between two adjacent chip groupings. In this embodiment, the Fow (Film on Wire) layer 320 is a novel supporting type chip adhesive, generally in the form of a film, for supporting the chip 210, and is disposed between two adjacent chip groups 210-1 to 210-2 and 210-3 to 210-4, so as to realize the spacing between the chip groups 210-1 to 210-2 and 210-3 to 210-4, and avoid the short circuit caused by the contact between the gold wire of the lower chip 210-2 and the upper chip 210-3. The Fow layer 320 is disposed between two adjacent chip groupings 210-1 to 210-2 and 210-3 to 210-4 of one of the chip sets 200, and forms a high-low offset for a portion of the chips 210 between the two chip sets 200, increasing the packaging capability of the uniform size substrate 100. Preferably, the Fow layer 320 is made of an epoxy material, wherein, as an advantage, the area of the Fow layer 320 is consistent with the size of the chip 210, and is stacked and arranged in superposition with the chip 210-2 below.

In some embodiments, as shown in FIG. 3, the elevated layer 300 is a Dummy layer 330 and is disposed between two adjacent chip groupings. In this embodiment, the Dummy layer 330 is used to support the chips 210 and is disposed between two adjacent chip groups 210-1 to 210-2 and 210-3 to 210-4. The Dummy layer 330 is disposed between two adjacent chip groups 210-1 to 210-2 and 210-3 to 210-4 of one of the chip sets 200, and forms a high-low dislocation of a portion of the chips 210 between the two chip sets 200, thereby increasing the packaging capability of the unified size substrate 100. Preferably, the Dummy layer 330 is a silicon wafer or an aluminum sheet, wherein the Dummy layer 330 is stacked with the lower chip 210-2 in a staggered manner, so that the bonding position of the lower chip 210-2 is exposed, and bonding is facilitated.

In some embodiments, adjacent ones 200 of the at least two chipsets 200 are relatively tilted. In this embodiment, as shown in fig. 2 and 3, the number of the exemplary chip sets 200 is two, wherein the stepped structures formed by the plurality of chips 210 in one chip set 200 are inclined to the left, the stepped structures formed by the plurality of chips 210 in the other chip set 200 are inclined to the right, and the stepped structures formed by the two chip sets 200 are inclined to each other.

In some embodiments, as shown in FIGS. 1-3, chips 210-1, 210-3, 210-5, and 210-7 below each chip group are connected to the chip and substrate 100 above it, respectively, by bond wires. In this embodiment, to meet the faster read/write speed while stacking multiple chips, the input/output ports of the chip 210 may be in a multi-port parallel manner, the chips 210-1, 210-3, 210-5 and 210-7 below each chip group are connected to the chip above and the substrate 100 through bonding wires, respectively, signals are simultaneously transmitted from the substrate 100 to the chips 210-1, 210-3, 210-5 and 210-7 below each chip group, and then transmitted from the chips 210-1, 210-3, 210-5 and 210-7 below the chip group to the chip above, so that the signal delay between the chips 210 in the chip group 200 is reduced, and the exemplary two chip groups 200 have a total of four channels, each channel is connected to the two chips 210, and the data between the channels is transmitted from the lowermost chips 210-1 and 210-5 to the uppermost chips 210-4 and 210-8 in sequence by the substrate 100, thereby achieving the faster parallel speed.

In some embodiments, as shown in FIGS. 1-3, adjacent chips 210-2 and 210-3 and 210-6 and 210-7 between adjacent chip groups are connected by bond wires. In this embodiment, adjacent chips 210-2 and 210-3 and 210-6 and 210-7 between adjacent chip groups are connected by bonding wires, and the power and ground ports in each chip group 200 are connected to each other by wire bonding in the chip 210 and finally connected to the substrate 100, so that the wire bonding cost is reduced compared with the case where the power and ground ports are directly connected to the substrate 100.

The utility model also provides a memory, which comprises a main board and a chip packaging structure, wherein the chip packaging structure is arranged on the main board, and the specific structure of the chip packaging structure refers to the embodiment.

The above description of the preferred embodiments of the present utility model should not be taken as limiting the scope of the utility model, but rather should be understood to cover all modifications, variations and adaptations of the present utility model using its general principles and the following detailed description and the accompanying drawings, or the direct/indirect application of the present utility model to other relevant arts and technologies.

Claims (10)

1. A chip package structure, comprising:

a substrate;

at least two chip sets are adjacently arranged on the substrate, and chips in each chip set are stacked in sequence in a step shape;

and the heightening layer is arranged in at least one of the chip sets, so that part or all of chips between at least two chip sets form high-low dislocation.

2. The chip package structure of claim 1, wherein the semiconductor package structure comprises a plurality of semiconductor chips,

and a gasket is arranged on the substrate, and the gasket forms the heightening layer to support a plurality of chips in the chip set.

3. The chip package structure of claim 2, wherein adjacent ones of the at least two chip sets are tilted in the same direction.

4. The chip package structure according to claim 1, wherein the chip set includes at least two chip groups disposed in order from bottom to top, each of the chip groups including two adjacent chips.

5. The chip package structure of claim 4, wherein the elevated layer is a Fow layer and is disposed between two adjacent chip groupings.

6. The chip package structure of claim 4, wherein the elevated layer is a Dummy layer and is disposed between two adjacent chip groups.

7. The chip package structure according to claim 5 or 6, wherein adjacent ones of the at least two chip sets are inclined with respect to each other.

8. The chip package structure according to claim 4, wherein the chips below each of the chip groups are connected to the chips above the chip groups and the substrate by bonding wires, respectively.

9. The chip package structure of claim 8, wherein adjacent chips between adjacent ones of the chip groupings are connected by bond wires.

10. A memory comprising a motherboard and the chip package structure of any one of claims 1-9, the chip package structure being disposed on the motherboard.

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