CN115692385A

CN115692385A - Chip packaging structure and memory

Info

Publication number: CN115692385A
Application number: CN202211372592.0A
Authority: CN
Inventors: 孙成思; 覃云珍; 李振华
Original assignee: Biwin Storage Technology Co Ltd
Current assignee: Biwin Storage Technology Co Ltd
Priority date: 2022-11-03
Filing date: 2022-11-03
Publication date: 2023-02-03

Abstract

The invention discloses a chip packaging structure and a memory, wherein the chip packaging structure comprises: a substrate; at least two chip groups which are adjacently arranged on the substrate, wherein the chips in each chip group are sequentially stacked in a ladder shape; and the cushion layer is arranged in at least one of the chip groups, so that part or all of the chips between at least two chip groups form high-low dislocation. The chip packaging structure comprises a substrate, at least two chip groups and a pad high layer, wherein chips in each chip group are sequentially stacked in a step shape in the vertical direction of the substrate, the pad high layer is arranged in at least one chip group, so that part or all chips between the at least two chip groups are staggered in height, a routing space is provided by utilizing the staggered height difference, routing can be carried out in the routing space between the chip groups without mutual influence, and therefore the adjacent chip groups do not need to be arranged at a larger interval, the design size of the substrate can be correspondingly reduced, and the packaging size is reduced.

Description

Chip packaging structure and memory

Technical Field

The invention relates to the field of chip packaging, in particular to a chip packaging structure and a memory.

Background

The multi-chip stacking is a basic technology of three-dimensional packaging, and particularly for storage products, the multi-layer stacking technology determines the degree of product size reduction and the integration level of a three-dimensional packaging module.

Chips with different specifications, types and sizes are stacked, a certain space needs to be reserved during wire bonding to prevent mutual contact and interference between wires and the chips, but the current trend of packaging size is more miniaturized, and how to package more chips in smaller size is a current technical difficulty.

According to the existing chip packaging technology, chips are obliquely mounted on a substrate, and adjacent chip groups need to be separated by a large distance to perform routing in a reserved space, so that the occupied space of the substrate is increased, and the packaging size of a product is large.

Disclosure of Invention

The invention mainly aims to provide a chip packaging structure, and aims to solve the problem that the packaging size of the existing chip structure is large.

In order to achieve the above object, the present invention provides a chip package structure, including:

a substrate;

at least two chip groups which are adjacently arranged on the substrate, wherein chips in each chip group are sequentially stacked in a ladder shape;

and the cushion layer is arranged in at least one of the chip groups, so that part or all of the chips between at least two of the chip groups form high-low dislocation.

In some embodiments, a pad is disposed on the substrate, the pad forming the pad layer to support the plurality of chips in the chipset.

In some embodiments, adjacent ones of at least two of the chipsets are co-inclined.

In some embodiments, the chipset includes at least two chip groups arranged in sequence from bottom to top, and each chip group includes two adjacent chips.

In some embodiments, the higher-pad layer is a Fow layer and is disposed between two adjacent chip groups.

In some embodiments, the pad layer is a Dummy layer and is disposed between two adjacent chip groups.

In some embodiments, adjacent ones of at least two of the chipsets are relatively tilted.

In some embodiments, the chips below each of the chip groups are respectively connected with the chips above the chip groups and the substrate through bonding wires.

In some embodiments, adjacent chips between adjacent said chip groupings are connected by bond wires.

The invention further provides a memory, which comprises a mainboard and the chip packaging structure, wherein the chip packaging structure is arranged on the mainboard.

The chip packaging structure comprises a substrate, at least two chip groups and a pad high layer, wherein chips in each chip group are sequentially stacked in a step shape in the vertical direction of the substrate, the pad high layer is arranged in at least one chip group, so that part or all chips between the at least two chip groups are staggered in height, a routing space is provided by utilizing the staggered height difference, routing can be carried out in the routing space between the chip groups without mutual influence, and therefore the adjacent chip groups do not need to be arranged at a larger interval, the design size of the substrate can be correspondingly reduced, and the packaging size is reduced.

Drawings

Fig. 1 is a schematic structural diagram of a chip package structure according to an embodiment of the invention;

FIG. 2 is a schematic structural diagram of a chip package structure according to another embodiment of the present invention;

fig. 3 is a schematic structural diagram of a chip package structure according to another embodiment of the invention.

Detailed Description

In the following, the embodiments of the present invention will be described in detail with reference to the drawings in the following, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.

It should be noted that all the directional indicators (such as upper, lower, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the motion situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.

It will also be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.

The inventor researches and discovers that in the existing staggered lamination packaging technology, chips are obliquely mounted on a substrate, adjacent chip groups need to be separated by a larger distance to perform routing in a reserved space, and when the chips are stacked more and more, the occupied space of the substrate is larger, so that the packaging size of the product is larger.

The invention provides a chip packaging structure, as shown in fig. 1 to 3, the chip packaging structure includes:

a substrate 100;

at least two chip groups 200 adjacently arranged on the substrate 100, wherein the chips 210 in each chip group 200 are sequentially stacked in a step shape;

and the cushion layer 300 is arranged in at least one of the chip groups 200, so that part or all of the chips 210 between at least two chip groups 200 form high-low dislocation.

In this embodiment, the chip package structure is a three-dimensional package of a memory chip, and specifically, the chip package structure mainly includes a substrate 100, at least two chip sets 200, and a pad layer 300, where a mounting position is defined on an upper surface of the substrate 100 to mount the at least two chip sets 200, and other mounting positions may be defined on the substrate 100 to mount other components, which are not listed herein. When packaging is performed, a packaging layer is further disposed on the substrate 100, and the packaging layer is attached to the substrate 100 to realize packaging of each element including at least two chip sets 200, a pad layer 300, and the like on the substrate 100. Wherein, the packaging layer is preferably made of epoxy resin material.

Each chipset 200 includes a plurality of chips 210, and the number of chips 210 of the chipset 200 may be the same or different, which is not limited. In the chipset 200, the chips 210 are stacked in a step-like manner, so that the chips 210 are staggered for connecting wires among the chips 210, and finally the wires are connected to the substrate 100. Also, the stepped stacking of the chips 210 in the chip set 200 causes the chip set 200 to be inclined toward a certain direction (e.g., a left direction or a right direction). The inclination directions of the chip sets 200 in at least two chip sets 200 may be the same or different. The padding layer 300 is positioned in at least one chip set 200, so that part or all of the chips 210 between at least two chip sets 200 form height dislocation, and a routing space is provided while the size of the substrate 100 is not increased, thereby increasing the packaging capacity of the substrate 100 with uniform size. The padding layer 300 may be located at the bottom of the chipset 200, or between the chipsets 200, and is set according to specific situations.

The chip packaging structure comprises a substrate 100, at least two chip groups 200 and a padding layer 300, wherein the chips 210 in each chip group 200 are sequentially stacked in a step shape in the vertical direction of the substrate 100, the padding layer 300 is arranged in at least one chip group 200, so that part or all of the chips 210 between at least two chip groups 200 form high-low dislocation, a routing space is provided by utilizing the dislocation height difference, routing can be carried out in the routing space between each chip group 200 without mutual influence, and therefore, the adjacent chip groups 200 do not need to be arranged at a larger interval, the design size of the substrate 100 can be correspondingly reduced, and the packaging size is reduced.

In some embodiments, as shown in fig. 1, a pad 310 is disposed on the substrate 100, and the pad 310 forms a pad layer 300 to support the plurality of chips 210 in the chip set 200. In this embodiment, there are two exemplary chipsets 200, each chipset 200 includes 4 chips, one chipset 200 has chips 210-1 to 210-4, and the other chipset 200 has chips 210-5 to 210-8. The substrate 100 is provided with a pad 310, and the pad 310 forms a pad layer 300 for supporting a plurality of chips 210 in the chipset 200. For example, as shown in FIG. 1, the gasket 310 supports the chip set 200 made up of chips 210-5 through 210-8. The gasket 310 is disposed between one of the chip sets 200 and the substrate 100, and the height difference between all the chips 210 of the two chip sets 200 is utilized to provide a wire bonding space, so that wire bonding can be performed between the two chip sets 200 without mutual influence, thereby reducing the package size. Preferably, the gasket 310 is made of a silicon wafer or an aluminum sheet.

In some embodiments, adjacent chipsets 200 of the at least two chipsets 200 are co-inclined. In the present embodiment, as shown in fig. 1, the exemplary chip sets 200 are two, and the stepped structures formed by the plurality of chips 210 in the two chip sets 200 are all disposed obliquely to the left side.

In the present embodiment, the left and right sides are both the left and right sides in the drawings, and they represent one relative direction and do not represent an absolute direction.

In some embodiments, as shown in fig. 1 to 3, the chipset 200 includes at least two chip groups arranged in sequence from bottom to top, each chip group including two adjacent chips. In the present embodiment, the chips in each chipset 200 are exemplarily grouped into two groups, wherein in one chipset 200, the chip 210-1 and the chip 210-2 are grouped into one chip, and the chip 210-3 and the chip 210-4 are grouped into one chip. In another chipset 200, chips 210-5 and 210-6 are grouped together, and chips 210-7 and 210-8 are grouped together. Each chipset 200 includes two chip groups sequentially arranged from bottom to top, each chip group includes two adjacent chips 210, and the data transmission signals of the two chips 210 are connected through one channel.

In some embodiments, as shown in fig. 2, the elevated layer 300 is a Fow layer 320 and is disposed between two adjacent chip groups. In this embodiment, the Film on Wire layer 320 is a new supporting type die adhesive, generally in a Film form, for supporting the die 210, and is disposed between two adjacent die groups 210-1 to 210-2 and 210-3 to 210-4, so as to realize the spacing between the die groups 210-1 to 210-2 and 210-3 to 210-4 and avoid the short circuit caused by the contact between the gold wires of the lower die 210-2 and the upper die 210-3. The Fow layer 320 is disposed between two adjacent chip groups 210-1 to 210-2 and 210-3 to 210-4 of one of the chip sets 200, and the height offset is formed between some chips 210 of the two chip sets 200, so as to increase the packaging capacity of the substrate 100 with uniform size. The Fow layer 320 is preferably made of an epoxy material, wherein the area of the Fow layer 320 is preferably the same size as the chip 210, and the Fow layer is stacked in superposition with the chip 210-2 below.

In some embodiments, as shown in fig. 3, the padding layer 300 is a Dummy layer 330 and is disposed between two adjacent chip groupings. In this embodiment, the Dummy layer 330 is used to support the chips 210 and is disposed between two adjacent chip groups 210-1 to 210-2 and 210-3 to 210-4. The Dummy layer 330 is disposed between two adjacent chip groups 210-1 to 210-2 and 210-3 to 210-4 of one of the chip sets 200, and the height offset is formed between some chips 210 of the two chip sets 200, so as to increase the packaging capacity of the substrate 100 with uniform size. Preferably, the Dummy layer 330 is a silicon wafer or an aluminum sheet, wherein the Dummy layer 330 and the lower chip 210-2 are stacked in a staggered manner, so that the bonding position of the lower chip 210-2 is exposed, thereby facilitating the bonding.

In some embodiments, adjacent chipsets 200 of the at least two chipsets 200 are relatively tilted. In this embodiment, as shown in fig. 2 and fig. 3, the number of the exemplary chip sets 200 is two, wherein the stepped structure formed by the plurality of chips 210 in one chip set 200 is inclined to the left, the stepped structure formed by the plurality of chips 210 in the other chip set 200 is inclined to the right, and the stepped structures formed by the two chip sets 200 are inclined to each other.

In some embodiments, as shown in fig. 1-3, chips 210-1, 210-3, 210-5, and 210-7 under each chip group are connected with chips above it and substrate 100, respectively, by bond wires. In this embodiment, to satisfy faster read/write speed while stacking multiple chips, the input/output ports of the chips 210 may be connected in a multi-port parallel manner, the chips 210-1, 210-3, 210-5, and 210-7 under each chip group are respectively connected to the chip above the chip and the substrate 100 through bonding wires, signals are simultaneously transmitted from the substrate 100 to the chips 210-1, 210-3, 210-5, and 210-7 under each chip group, and then transmitted from the chips 210-1, 210-3, 210-5, and 210-7 under the chip group to the chips above the chip, so that signal delay between the chips 210 in the chip group 200 is reduced, compared to sequentially transmitting signals from the substrate 100 to the lowermost chips 210-1 and 210-5 to the uppermost chips 210-4 and 210-8, the exemplary two chip groups 200 form four channels in total, each channel has a group of data transmission, each channel connects two chips 210, and data between the channels are transmitted in parallel, so as to achieve faster transmission speed.

In some embodiments, as shown in fig. 1-3, adjacent chips 210-2 and 210-3 and 210-6 and 210-7 between adjacent chip groupings are connected by bond wires. In this embodiment, the adjacent chips 210-2 and 210-3 and 210-6 and 210-7 in the adjacent chip groups are connected by bonding wires, and the power and ground ports in each chipset 200 are wire-bonded to each other in the chip 210 and finally connected to the substrate 100, so that the wire-bonding cost is reduced compared with the case where the power and ground ports are directly connected to the substrate 100.

The present invention further provides a memory, where the memory includes a motherboard and a chip package structure, the chip package structure is disposed on the motherboard, and the specific structure of the chip package structure refers to the foregoing embodiments.

The above description is only a part of or preferred embodiments of the present invention, and neither the text nor the drawings should be construed as limiting the scope of the present invention, and all equivalent structural changes, which are made by using the contents of the present specification and the drawings, or any other related technical fields, are included in the scope of the present invention.

Claims

1. A chip package structure, comprising:

a substrate;

2. The chip package structure of claim 1,

the substrate is provided with a gasket, and the gasket forms the gasket layer to support the chips in the chip group.

3. The chip package structure according to claim 2, wherein adjacent ones of at least two of the chipsets are tilted in the same direction.

4. The chip package structure according to claim 1, wherein the chip set comprises at least two chip groups arranged in sequence from bottom to top, each of the chip groups comprising two adjacent chips.

5. The chip package structure according to claim 4, wherein the padding layer is a Fow layer and is disposed between two adjacent chip groups.

6. The chip package structure according to claim 4, wherein the pad up layer is a Dummy layer and is disposed between two adjacent chip groups.

7. The chip package structure according to claim 5 or 6, wherein adjacent ones of at least two of the chipsets are inclined with respect to each other.

8. The chip packaging structure according to claim 4, wherein the chip under each of the chip groups is connected to the chip over the chip group and the substrate through bonding wires.

9. The chip package structure according to claim 8, wherein adjacent chips between adjacent chip groups are connected by bonding wires.

10. A memory, comprising a motherboard and the chip package structure of any one of claims 1 to 9, wherein the chip package structure is disposed on the motherboard.