CN100411170C - Stack architecture of multiple chips - Google Patents
Stack architecture of multiple chips Download PDFInfo
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- CN100411170C CN100411170C CNB2005100734788A CN200510073478A CN100411170C CN 100411170 C CN100411170 C CN 100411170C CN B2005100734788 A CNB2005100734788 A CN B2005100734788A CN 200510073478 A CN200510073478 A CN 200510073478A CN 100411170 C CN100411170 C CN 100411170C
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- weld pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The present invention relates to a stack structure of multiple chips, which comprises a chip carrier, a first chipset, a cushion piece and a second chipset, wherein the first chipset is provided with a plurality of chips, the chips which are provided with unilateral weld pads are stacked on the chip carrier in the shape of a step; the cushion piece is connected to the first chipset; the second chipset is provided with a plurality of chips which are provided with unilateral weld pads; bottommost chips of the second chipset are connected to the cushion piece in a deflection way along the direction of the weld pads of the first chipset; then, the chips are stacked in the shape of the step, the weld pads are exposed, and the present invention avoids that when the chips are stacked, the chips are beyond the packaging range. Multiple layers of the chips can be packed in a packaging piece under the principle that the area of the packaging piece is not increased, the chips which are provided with the unilateral weld pads can be effectively stacked in a semiconductor packaging piece, the chips can not be stacked in the deflection way and in a single direction, and the convenience for throwing of the welding part of the chips is strengthened.
Description
Technical field
The invention relates to a kind of multi-chip stack structure, particularly about a kind of stack architecture with a plurality of chips of monolateral weld pad.
Background technology
Because the microminiaturization of electronic product and the increase of high-speed cruising demand, for the performance that improves single semiconductor package and capacity to meet the demand of miniaturization of electronic products, the multi-chip moduleization of semiconductor package part structure (Multi chip Module) has become a kind of trend, whereby two or more semiconductor chips are combined in the single encapsulating structure, reduction integrated circuit volume improves electrical functionality.Just multichip packaging structure can pass through two or more chip portfolios in single encapsulating structure the restriction of system running speed to be minimized.In addition, multichip packaging structure can reduce the length of chip chamber connection line, thereby reduces signal delay and access time.
Common multichip packaging structure is to adopt side-by-side (side-by-side) multichip packaging structure, and it is the main installed surface that plural chip is installed in each other abreast a substrate.Being connected between the conducting wire generally is to realize by line weldering method (wire bonding) on chip and this substrate.But, owing to the area of this substrate can increase along with the increase of core number, so make the packaging cost of this side-by-side multichip package structure increase.
For addressing the above problem, often use the chip that stacking method is installed to be increased in recent years, the mode of its storehouse is had nothing in common with each other according to design, the routing processing procedure of its chip, but if this chip is designed to weld pad when concentrating on one side, flash chip (flash memory chip) etc. for example, its storehouse mode certainly will adopt stair-stepping form for the facility of routing.United States Patent (USP) the 6th shown in Figure 1A, 621, the multi-chip stack structure that discloses for No. 155, it be on chip carrier 10 storehouse a plurality of chips, first chip 11 is installed on the chip carrier 10, and second chip 12 is offset suitable distance under the principle that does not hinder the 11 weld pad routing operations of first chip, and storehouse is on this first chip 11, the 3rd chip 13 under the principle that does not hinder the 12 weld pad routing operations of second chip, be offset suitable apart from storehouse on this second chip 12.
The windrow chip stack carries out the routing operation again, but its disadvantage is, storehouse is during than the chip of multilayer, the storehouse mode makes it constantly banking, the projected area of entire chip storehouse certainly will be continued to increase, shown in Figure 1B, the side edge length of supposing semiconductor chip is S, whenever setting up semiconductor chip of storehouse all must be away from the distance of the pad zone L of lower floor's semiconductor chip, be beneficial to the carrying out of routing operation, so when storehouse behind the n layer chip, the storehouse projected length of this semiconductor chip will be S+ (n-1) L; Hence one can see that when constantly to single direction during with the step-wise manner stack chip, when storehouse arrives certain number of plies, chip will exceed the scope that can encapsulate, must increase the chip carrier area of packaging part to finish this stack chip this moment, but the area that increases packaging part also has influence on the area of whole electronic product, has run counter to electronic product small size and multi-functional characteristic demand.
Therefore, the structure how a plurality of chips of a kind of storehouse to be provided does not need again in the packaging part so increases the packaging part area to realize that a plurality of chips can be encapsulated in, and being needs the problem that solves at present.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of multi-chip stack structure, not increasing under the packaging part area principle, multilayer chiop can be encapsulated in the packaging part.
A further object of the present invention is to provide a kind of multi-chip stack structure, make a plurality of chips with monolateral weld pad effectively storehouse in semiconductor package part.
Another purpose of the present invention is to provide a kind of multi-chip stack structure, make a plurality of chips can folk prescription to the skew storehouse.
Another object of the present invention is to provide a kind of multi-chip stack structure, promote the convenience of chip weldering knot portion routing.
For reaching above-mentioned and other purpose, a kind of multi-chip stack structure of the present invention comprises: chip carrier; First chipset has a plurality of chips, and these chips have monolateral weld pad and stepped storehouse on this chip carrier, and manifest this weld pad; Bolster connects and puts on this first chipset; And second chipset, have a plurality of chips, these chips have monolateral weld pad, and the bottom chip of this second chipset is to connect with the weld pad direction skew to this first chipset to put on this bolster, again with stepped storehouse remaining chip, and manifest this weld pad.Wherein, this first chipset comprises lower floor's chip and upper strata chip, in this stack architecture, the weld pad of this upper and lower layer chip is positioned at the same side, and the predetermined distance of this relative lower floor of upper strata chip chip offset is electrically connected to this chip carrier for this lower floor's chip and upper strata chip by bonding wire with the area just above of the weld pad of avoiding covering lower floor's chip.Preferably the projected area of this second chipset does not surpass the projected area of this first chipset.
The corresponding lateral deviation that it has weld pad of a plurality of chips in this first chipset and second chipset is from following square chip one predefined distance, make to go up square chip can not keep off the below chip pad directly over the zone, can not hinder the routing processing procedure, be electrically connected at chip carrier via many bonding wires for these chip pad; This bolster, anchor on the chip of this first chipset the top and the area just above that can not keep off the weld pad of this top chip, and the square chip that descends most of this second chipset can begin upwards storehouse by being provided with to this first chipset routing direction of this bolster, can not make all chips in this first chipset and second chipset only carry out storehouse and cause taking too large tracts of land of chip carrier, may cause problems such as exceeding the packaging part scope when avoiding chip stack to single direction.
Therefore, multi-chip stack structure of the present invention is after the storehouse number layer has the chip of monolateral weld pad, under the principle of not blocking the superiors' chip pad bolster is being covered on the superiors' chip earlier, and then cover later chip, this chip that covers on the bolster does not just need to avoid the bonding wire end of lower floor's chip, can be according to the principle storehouse of chip stack layer minimum projection area, when soon exceeding the packaging part scope, stack layer can regulate its stack space in the mode of bolster separation chip again, can not make whole chips only to the single direction skew, can increase the chip stack number whereby.
In sum, multi-chip stack structure of the present invention can not increase under the packaging part area principle, multilayer chiop can be encapsulated in the packaging part, make a plurality of chips with monolateral weld pad effectively storehouse in semiconductor package part, a plurality of chips can folk prescription to the skew storehouse, promote the convenience of chip weldering knot portion routing.
Description of drawings
Figure 1A is the generalized section of existing multi-chip stack structure;
Figure 1B is the shortcoming schematic diagram of existing multi-chip stack structure; And
Fig. 2 is the generalized section of multi-chip stack structure of the present invention.
Embodiment
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention.Only show the assembly relevant in the following drawings, and be not that component count, shape and size when implementing according to reality drawn that kenel, quantity and the ratio of each assembly can arbitrarily change during reality enforcement, and its assembly layout form may be more complicated with the present invention.
Fig. 2 is the generalized section of multi-chip stack structure of the present invention.
This multi-chip stack structure comprises: chip carrier 20, first chipset 21, bolster 23 and second chipset 22.Wherein, this first chipset 21 has a plurality of chips, and these chips have monolateral weld pad and stepped storehouse on this chip carrier 20, and manifest this weld pad; This bolster 23 connects to be put on this first chipset 21; This second chipset 22 has a plurality of chips, these chips have monolateral weld pad and stepped storehouse on this bolster 23, and the bottom chip of this second chipset 22 is to put on this bolster 23 to connect to the skew of the direction of these first chipset, 21 weld pads, again with stepped storehouse remaining chip, and manifest this weld pad.
Preferably the projected area of this second chipset 22 does not surpass the projected area of this first chipset 21.This chip carrier 20 can be ball grid array type substrate or conducting wire frame structure.
As shown in the figure, this first chipset 21 comprises first chip 211 and second chip 212 (but non-exceed with layers of chips), the size of this first chip 211 and second chip 212 is roughly the same, and have a plurality of weld pad 211a monolateral, 212a, this second chip 212 is to have the side of weld pad 212a and depart from first chip, 211 1 predefined distances with it, make this second chip 212 can not keep off the zone directly over first chip, the 211 weld pad 211a, be electrically connected to this chip carrier 20 for this first chip 211 and second chip 212 by many bonding wires 241, can not hinder the routing processing procedure.
The material of this bolster 23 is waste chips, metal gasket or insulating resin pad etc., puts on second chip 212 of these first chipset, 21 the tops for connecing, and the weld pad 212a that can not keep off this second chip 212 directly goes up regional.
As shown in the figure, this second chipset 22 includes the 3rd chip 223 and four-core sheet 224 (but non-exceed with layers of chips), the 3rd chip 223, the size of four-core sheet 224 and first chip 211, second chip 212 is roughly the same, and have a plurality of weld pad 223a monolateral, 224a, this four-core sheet 224 is to have the side of weld pad 224a and depart from the 3rd chip 223 1 predefined distances with it, make this four-core sheet 224 can not keep off the zone directly over the weld pad 223a of the 3rd chip 223, confession the 3rd and four-core sheet 223,224 are electrically connected to this chip carrier 20 by many bonding wires 242, can not hinder the routing processing procedure.It should be noted, the 3rd chip 223 of this second chipset 22 can be by the setting of this bolster 23, connect to these first chipset, 21 routing directions and to put on this bolster 23, restart again with stepped upwards storehouse, can not make first chip 211, second chip 212, the 3rd chip 223 and four-core sheet 224 in this first chipset 21 and second chipset 22 only carry out storehouse to single direction, cause taking the too big area of chip carrier 20, and then may cause problems such as exceeding the packaging part scope when having avoided chip stack.
Semiconductor chip weld pad in the multi-chip stack structure just of the present invention all be positioned at one-sided and these die size roughly the same, having a side edge length is S, for in first chipset 21 with isometric second chip 212 of these first chip, 211 length under the pad zone principle that exposes outside first chip 211, to the pad zone of first chip 211 away from a L apart from storehouse on this first chip 211, when carrying out the routing operation, make this first chip 211 and second chip 212 be electrically connected to chip carrier 20 by this bonding wire 241.
Make this bolster 23 connect under the pad zone principle of not covering second chip 212 on second chip 212 that places this first chipset 21 again, and the 3rd chip 223 that makes second chipset 22 is covered on this bolster 23, and the 3rd chip 223 to connect the position that places this bolster 23 be corresponding to this first chip 211, the routing direction skew of second chip 212, and its downward projected position corresponds to this first chip 211, again four-core sheet 224 is being stacked on the 3rd chip 223 to the pad zone of the 3rd chip 223 distance away from a L under the pad zone principle that exposes outside the 3rd chip 223, is carrying out the routing operation and make the 3rd chip 223 for follow-up, four-core sheet 224 is electrically connected to this chip carrier 20 by bonding wire 242.
Therefore, after the present invention at first includes first chipset 21 of a plurality of semiconductor chips with stepped storehouse, carry out the routing operation first time, on this first chipset 21, connect successively then and put the bolster 23 and second chipset 22, isolate first chipset and second chipset 21 by this bolster 23,22, second chipset 22 is not contacted and first chipset 21 has all been finished the routing operation with first chipset 21, therefore need not worry and to hinder its routing or hide its pad zone, and the optimum position of the 3rd chip 223 of this second chipset 22 then corresponds to first chip, 211 positions of first chipset 21 for its view field, similarly, 224 of four-core sheets with its view field corresponding to the mode storehouse of this second chip 212 on the 3rd chip 223, no matter what of the whole projected length storehouse number of plies behind these chip stacks will remain (S+L) always for, compare to the projected length that method is caused of stepped skew storehouse with folk prescription with prior art, the present invention can save the projected length of 2L.
Certainly this first chipset, second chipset are not only to exceed with two chips, but if relatively altogether during storehouse n chip, the total projection length of this n chip will be maintained (S+L), so the total projection length that a plurality of chips only continue to cause when single direction is offset in the prior art is S+ (n-1) L relatively, the comparable prior art of the chip total projection length in the multi-chip stack structure of the present invention shortens (S+ (n-1) L)-(S+L)=(n-2) distance of L.
In addition, equally also can on this second chipset, continue to be provided with bolster, and on this bolster the stack chip group, by the setting of this bolster, the projected length of these chipsets is maintained in the certain distance.
Therefore, multi-chip stack structure of the present invention is after the storehouse number layer has the chip of monolateral weld pad, under the principle of not blocking the superiors' chip pad bolster is being covered on the superiors' chip earlier, and then cover later chip, this chip that covers on the bolster does not just need to avoid the bonding wire end of lower floor's chip, can be according to the principle storehouse of chip stack layer minimum projection area, when soon exceeding the packaging part scope, stack layer regulates its stack space in the mode of bolster separation chip again, can not make whole chips only to the single direction skew, can increase the chip stack number whereby.
Claims (10)
1. a multi-chip stack structure is characterized in that, this stack architecture comprises:
Chip carrier;
First chipset has a plurality of chips, and these chips have monolateral weld pad and stepped storehouse on this chip carrier, and manifest this weld pad;
Bolster connects and puts on this first chipset; And
Second chipset, have a plurality of chips, these chips have monolateral weld pad, and the bottom chip of this second chipset is to connect with the weld pad direction skew to this first chipset to put on this bolster, again with stepped storehouse remaining chip, and manifest this weld pad, wherein, this first chipset comprises lower floor's chip and upper strata chip, in this stack architecture, on being somebody's turn to do, the weld pad of lower floor's chip is positioned at the same side, and the predetermined distance of this relative lower floor of upper strata chip chip offset is electrically connected to this chip carrier for this lower floor's chip and upper strata chip by bonding wire with the area just above of the weld pad of avoiding covering lower floor's chip.
2. multi-chip stack structure as claimed in claim 1 is characterized in that, the projected area of this second chipset does not surpass the projected area of this first chipset.
3. multi-chip stack structure as claimed in claim 1 is characterized in that, the chip size in this first chipset and second chipset is identical.
4. multi-chip stack structure as claimed in claim 1 is characterized in that, this chip carrier is spherical grid array type substrate or conducting wire frame structure.
5. multi-chip stack structure as claimed in claim 1 is characterized in that, this bolster is waste chips, metal gasket or insulating resin pad.
6. multi-chip stack structure as claimed in claim 1 is characterized in that, this bolster connects to be put on the chip of this first chipset the top, and can not keep off the zone directly over the weld pad of this chip.
7. multi-chip stack structure as claimed in claim 1, it is characterized in that, this second chipset comprises lower floor's chip and upper strata chip, in this stack architecture, the weld pad of this upper and lower layer chip is positioned at the same side, and the predetermined distance of this relative lower floor of upper strata chip chip offset is electrically connected to this chip carrier for this lower floor's chip and upper strata chip by bonding wire with the zone directly over the weld pad of avoiding covering lower floor's chip.
8. multi-chip stack structure as claimed in claim 1, it is characterized in that, this first chipset and second chipset respectively have lower floor's chip and upper strata chip, and the downward projected position of lower floor's chip of this second chipset and upper strata chip corresponds respectively to the lower floor's chip and the upper strata chip position of this first chipset.
9. multi-chip stack structure as claimed in claim 1 is characterized in that, this multi-chip stack structure also comprises and is located at another bolster on this second chipset and connects the chipset of putting on this another bolster.
10. multi-chip stack structure as claimed in claim 1, wherein, the position of a plurality of chips of this second chipset corresponds respectively to the position of a plurality of chips of this first chipset, so that the whole projected length behind a plurality of chip stacks of this first chipset and second chipset is consistent.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100734788A CN100411170C (en) | 2005-05-30 | 2005-05-30 | Stack architecture of multiple chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100734788A CN100411170C (en) | 2005-05-30 | 2005-05-30 | Stack architecture of multiple chips |
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| Publication Number | Publication Date |
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| CN1873972A CN1873972A (en) | 2006-12-06 |
| CN100411170C true CN100411170C (en) | 2008-08-13 |
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| CNB2005100734788A Active CN100411170C (en) | 2005-05-30 | 2005-05-30 | Stack architecture of multiple chips |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101452861B (en) * | 2007-12-07 | 2011-01-26 | 矽品精密工业股份有限公司 | Multi-chip stacking structure and preparation thereof |
| US9263421B2 (en) * | 2014-02-28 | 2016-02-16 | Infineon Technologies Ag | Semiconductor device having multiple chips mounted to a carrier |
Citations (7)
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| WO2002009181A1 (en) * | 2000-07-20 | 2002-01-31 | Vertical Circuits, Inc. | Vertically integrated chip on chip circuit stack |
| US6353265B1 (en) * | 2001-02-06 | 2002-03-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| US6538331B2 (en) * | 2000-01-31 | 2003-03-25 | Hitachi, Ltd. | Semiconductor device and a method of manufacturing the same |
| US6621155B1 (en) * | 1999-12-23 | 2003-09-16 | Rambus Inc. | Integrated circuit device having stacked dies and impedance balanced transmission lines |
| US6706557B2 (en) * | 2001-09-21 | 2004-03-16 | Micron Technology, Inc. | Method of fabricating stacked die configurations utilizing redistribution bond pads |
| US6867500B2 (en) * | 2002-04-08 | 2005-03-15 | Micron Technology, Inc. | Multi-chip module and methods |
| CN1858907A (en) * | 2005-05-06 | 2006-11-08 | 冲电气工业株式会社 | Semiconductor device and fabrication method thereof |
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2005
- 2005-05-30 CN CNB2005100734788A patent/CN100411170C/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6621155B1 (en) * | 1999-12-23 | 2003-09-16 | Rambus Inc. | Integrated circuit device having stacked dies and impedance balanced transmission lines |
| US6538331B2 (en) * | 2000-01-31 | 2003-03-25 | Hitachi, Ltd. | Semiconductor device and a method of manufacturing the same |
| WO2002009181A1 (en) * | 2000-07-20 | 2002-01-31 | Vertical Circuits, Inc. | Vertically integrated chip on chip circuit stack |
| US6353265B1 (en) * | 2001-02-06 | 2002-03-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| US6706557B2 (en) * | 2001-09-21 | 2004-03-16 | Micron Technology, Inc. | Method of fabricating stacked die configurations utilizing redistribution bond pads |
| US6867500B2 (en) * | 2002-04-08 | 2005-03-15 | Micron Technology, Inc. | Multi-chip module and methods |
| CN1858907A (en) * | 2005-05-06 | 2006-11-08 | 冲电气工业株式会社 | Semiconductor device and fabrication method thereof |
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| CN1873972A (en) | 2006-12-06 |
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