CN220543352U - Chip and memory device - Google Patents
Chip and memory device Download PDFInfo
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- CN220543352U CN220543352U CN202322073294.8U CN202322073294U CN220543352U CN 220543352 U CN220543352 U CN 220543352U CN 202322073294 U CN202322073294 U CN 202322073294U CN 220543352 U CN220543352 U CN 220543352U
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- 238000012360 testing method Methods 0.000 claims abstract description 140
- 239000000758 substrate Substances 0.000 claims description 39
- 239000002184 metal Substances 0.000 claims description 28
- 238000005538 encapsulation Methods 0.000 claims description 5
- 238000004806 packaging method and process Methods 0.000 claims description 2
- 230000008054 signal transmission Effects 0.000 abstract description 11
- 238000000034 method Methods 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
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Abstract
The application belongs to the chip field, discloses a chip and storage device, the chip includes the base plate, be provided with master control, test point interface and main interface on the base plate, the main interface sets up the middle part of base plate, the test point interface sets up the edge of base plate, the master control sets up the test point interface with between the main interface, the master control respectively with the main interface with the test point is connected, the master control with the test point interface is located the same side of base plate. By the method, the wiring from the test point to the main control is shortened, and signal transmission of the chip is improved.
Description
Technical Field
The present application relates to the field of chips, and in particular, to a chip and a memory device.
Background
The EMMC product can rapidly solve the technical compatibility problem with the master controller and the flash memory, and the product can be customized in capacity, security, industrial level and the like. Has high reliability and is also an economical storage product.
In the existing EMMC products, most of the EMMC products are manufactured by using a 4-layer board process, the test points are distributed around, and the distance between the test points and the main control is too large, so that the wiring from the test points to the main control end is relatively long, so that too long stub piles are formed, the antenna effect is triggered, and the signal transmission is poor.
Therefore, how to shorten the wiring from the test point to the main control, and improve the signal transmission of the chip, becomes a problem to be solved in the field.
Disclosure of Invention
The purpose of the application is to provide a chip and a storage device, shorten the wiring from a test point to a main control, and improve the signal transmission of the chip.
The application discloses chip, the chip includes the base plate, be provided with master control, test point interface and main interface on the base plate, the main interface sets up the middle part of base plate, the test point interface sets up the edge of base plate, the master control sets up the test point interface with between the main interface, the master control respectively with the master interface with the test point is connected, the master control with the test point interface is located the same side of base plate.
Optionally, the substrate includes a first metal layer, a second metal layer, an insulating layer, and an encapsulation layer, the first metal layer being stacked over the second metal layer, the insulating layer being disposed between the first metal layer and the second metal layer; the packaging layer wraps the first metal layer, the second metal layer and the insulating layer.
Optionally, the test point interfaces are multiple, and the multiple test point interfaces are arranged at intervals and are arranged in a straight line along the edge of the substrate.
Optionally, a plurality of connection ends are arranged on one side of the main control, which is close to the test point interfaces, the connection ends are arranged in a straight line, and the test point interfaces which are arranged in a plurality of straight lines are parallel to the connection ends which are arranged in a plurality of straight lines.
Optionally, the number of test point interfaces is greater than the number of connection terminals.
Optionally, the chip further includes a wafer, and the wafer is connected with a side of the main interface away from the main control.
Optionally, the total number of test point interfaces is 24.
Optionally, the test point interfaces are arranged along a straight line and divided into a first test group, a second test group and a third test group, the first test group is close to the edge of the substrate, the second test group is close to the main control, and the third test group is arranged between the first test group and the second test group.
Optionally, the number of test point interfaces in the first test group is 16, the number of test point interfaces in the second test group is 4, and the number of test point interfaces in the third test group is 4.
The application also discloses a storage device, including the circuit board, storage device still includes foretell the chip, the chip with the circuit board is connected.
According to the test point interface and the main control device, the test point interface and the main control device are arranged on the same side of the substrate, the test point interface is arranged on the edge of the substrate, and the main control device is arranged on one side, close to the main interface, of the test point interface, so that the main control device is arranged close to the test point interface, the distance between the main control device and the test point interface is shortened, the wiring from the test point interface to the main control device can be shortened, the length of a stub is shortened, and chip signal transmission is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive faculty for a person skilled in the art. In the drawings:
FIG. 1 is a top view of a first embodiment of a chip of the present application;
FIG. 2 is a schematic view of a substrate in a second embodiment of a chip of the present application;
FIG. 3 is a schematic diagram of an embodiment of a memory device of the present application.
10, a storage device; 100. a chip; 200. a circuit board; 110. a substrate; 111. a first metal layer; 112. a second metal layer; 113. an insulating layer; 114. an encapsulation layer; 120. a master control; 121. a connection end; 130. a test point interface; 131. a first test set; 132. a second test set; 133. a third test set; 140. a main interface; 150. and (3) a wafer.
Detailed Description
It should be understood that the terminology, specific structural and functional details disclosed herein are merely representative for purposes of describing particular embodiments, but that the application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
The present application is described in detail below with reference to the attached drawings and alternative embodiments.
Fig. 1 is a top view of a first embodiment of a chip of the present application, as shown in fig. 1, the present application discloses a chip 100, the chip 100 includes a substrate 110, a main control 120, a test point interface 130 and a main interface 140 are disposed on the substrate 110, the main interface 140 is disposed in the middle of the substrate 110, the test point interface 130 is disposed at an edge of the substrate 110, the main control 120 is disposed between the test point interface 130 and the main interface 140, the main control 120 is connected with the main interface 140 and the test point respectively, and the main control 120 and the test point interface 130 are located on the same side of the substrate 110.
According to the test point interface 130 and the main control 120 are arranged on the same side of the substrate 110, the test point interface 130 is arranged at the edge of the substrate 110, and the main control 120 is arranged on one side of the test point interface 130 close to the main interface 140, so that the main control 120 is close to the test point interface 130, the distance between the main control 120 and the test point interface 130 is shortened, wiring from the test point interface 130 to the main control 120 is shortened, the length of stub is shortened, and signal transmission of the chip 100 is improved.
The test point interfaces 130 are plural, and the plural test point interfaces 130 are arranged at intervals and are arranged in a straight line along the edge of the substrate 110. By arranging the plurality of test point interfaces 130 in a straight line, the distance between each test point interface 130 and the main control 120 can be shortened as much as possible in the process of connecting the plurality of test point interfaces 130 with the main control 120, the wiring from the test point interface 130 to the main control 120 is shortened, the length of a stub is shortened, and the signal transmission of the chip 100 is improved; and overlapping connection can not appear, the condition that causes signal interference or short circuit takes place to avoid.
Further, as shown in fig. 1, a plurality of connection terminals 121 are disposed on a side of the main control 120 near the test point interfaces 130, the plurality of connection terminals 121 are arranged in a straight line, and the plurality of test point interfaces 130 arranged in a straight line are parallel to the plurality of connection terminals 121 arranged in a straight line. The design makes the distance between the plurality of test point interfaces 130 and the main control 120 closer, further shortens the distance between the main control 120 and the test point interfaces 130, and thus, the wiring from the test point interfaces 130 to the main control 120 can be shortened, the length of stub is shortened, and the signal transmission of the chip 100 is improved.
Further, the number of test point interfaces 130 is greater than the number of connection terminals 121. Therefore, part of test point interfaces 130 can be reserved and designed, and when the subsequent products have bad problems, the reserved and designed test point interfaces 130 are utilized to be changed into other products, so that the utilization rate and the practical rate of the products are improved.
The chip 100 further includes a wafer 150, and the wafer 150 is connected to a side of the main interface 140 away from the main controller 120. In this way, the wafer 150, the main control 120 and the test point interface 130 are integrated on the substrate 110 at the same time in the limited space of the substrate 110, and the signal connection between the main control 120 and the wafer 150 can be shortened, so that the signal transmission is more stable, and the signal loss is reduced.
As shown in fig. 1, the total number of test point interfaces 130 is 24. This design facilitates placement of test point interfaces 130 within the limited space of substrate 110 and provides for efficient testing performance.
The test point interfaces 130 are arranged along a straight line and divided into a first test group 131, a second test group 132 and a third test group 133, wherein the first test group 131 is arranged near the edge of the substrate 110, the second test group 132 is arranged near the main control 120, and the third test group 133 is arranged between the first test group 131 and the second test group 132. Through the design of the three groups of test point interfaces 130, the test device can be more conveniently connected with the test point interfaces 130, and the stability and the reliability of the test of the chip 100 can be improved.
Specifically, the number of test point interfaces 130 in the first test group 131 is 16, the number of test point interfaces 130 in the second test group 132 is 4, and the number of test point interfaces 130 in the third test group 133 is 4. By limiting the number of the test point interfaces 130 in each group, the test point interfaces 130 can be laid out in a limited space of the substrate 110, which is beneficial to connecting the test point interfaces 130 through a test device and improving the reliability of the test.
It should be noted that, the chip 100 in the present application is mainly an EMMC chip 100, where the EMMC chip 100 has a small volume and a fast transmission speed, and the NAND test point interface 130 may be used to make a U disc with a smaller volume than a conventional U disc, and make a solid state hard disc with a smaller volume than a conventional solid state hard disc.
Fig. 2 is a schematic view of a substrate in a second embodiment of a chip of the present application, as shown in fig. 2, a substrate 110 includes a first metal layer 111, a second metal layer 112, an insulating layer 113, and an encapsulation layer 114, where the first metal layer 111 is stacked over the second metal layer 112, and the insulating layer 113 is disposed between the first metal layer 111 and the second metal layer 112; the encapsulation layer 114 encapsulates the first metal layer 111, the second metal layer 112, and the insulating layer 113.
In this embodiment, a two-layer board design is adopted, that is, only two metal layers are adopted to manufacture the substrate 110, compared with the substrate 110 manufactured by four metal layers, the cost for manufacturing the chip 100 is effectively saved, and the wiring space of the substrate 110 is saved by the design of the substrate 110 with two layers, so that the size of the substrate 110 is further reduced, the manufacture of the small-sized storage device 10 is more facilitated, meanwhile, the layout of the test point interfaces 130 can be rearranged, and the test point interfaces 130 and the main control 120 are arranged on the same side of the substrate 110, so that the manufacturing process can be effectively simplified, and the difficulty for manufacturing the chip 100 is reduced; in addition, the test point interface 130 is arranged at the edge of the substrate 110, and the main control 120 is arranged at one side of the test point interface 130 close to the main interface 140, so that the main control 120 is arranged close to the test point interface 130, the distance between the main control 120 and the test point interface 130 is shortened, the wiring from the test point interface 130 to the main control 120 is shortened, the length of stub is shortened, and the signal transmission of the chip 100 is improved.
Fig. 3 is a schematic diagram of an embodiment of a memory device according to the present application, and as shown in fig. 3, the present application further discloses a memory device 10, including a circuit board 200, where the memory device 10 further includes the above-mentioned chip 100, and the chip 100 is connected to the circuit board 200.
By connecting the chip 100 with the circuit board 200 and generally requiring a housing to wrap, the chip 100 and the circuit board 200 are protected by the housing, so that the chip 100 and the circuit board 200 are prevented from being damaged, and the service lives of the chip 100 and the circuit board 200 are prolonged; the chip 100 transmits signals through the circuit board 200, so that data can be stored or erased, and normal use of the memory device 10 is ensured.
According to the test point interface 130 and the main control 120 are arranged on the same side of the substrate 110, the test point interface 130 is arranged at the edge of the substrate 110, the main control 120 is arranged on one side of the test point interface 130 close to the main interface 140, so that the main control 120 is close to the test point interface 130, the distance between the main control 120 and the test point interface 130 is shortened, wiring from the test point interface 130 to the main control 120 is shortened, the length of a stub is shortened, signal transmission of the chip 100 is improved, and the quality of the storage device 10 is further improved.
The storage device 10 in the present application may be, but is not limited to, a flash disk, a hard disk, or the like, which may be used to store information.
It should be noted that, the inventive concept of the present application may form a very large number of embodiments, but the application documents have limited space and cannot be listed one by one, so that on the premise of no conflict, the above-described embodiments or technical features may be arbitrarily combined to form new embodiments, and after the embodiments or technical features are combined, the original technical effects will be enhanced.
The foregoing is a further detailed description of the present application in connection with specific alternative embodiments, and it is not intended that the practice of the present application be limited to such descriptions. It should be understood that those skilled in the art to which the present application pertains may make several simple deductions or substitutions without departing from the spirit of the present application, and all such deductions or substitutions should be considered to be within the scope of the present application.
Claims (10)
1. The chip is characterized by comprising a substrate, wherein a main control, a test point interface and a main interface are arranged on the substrate, the main interface is arranged in the middle of the substrate, the test point interface is arranged at the edge of the substrate, the main control is arranged between the test point interface and the main interface, the main control is respectively connected with the main interface and the test point interface, and the main control and the test point interface are positioned on the same side of the substrate.
2. The chip of claim 1, wherein the substrate comprises a first metal layer, a second metal layer, an insulating layer, and an encapsulation layer, the first metal layer stack disposed over the second metal layer, the insulating layer disposed between the first metal layer and the second metal layer; the packaging layer wraps the first metal layer, the second metal layer and the insulating layer.
3. The chip of claim 1, wherein a plurality of said test point interfaces are spaced apart and arranged in a straight line along an edge of said substrate.
4. The chip of claim 3, wherein a plurality of connection terminals are arranged on one side of the main control close to the test point interfaces, the plurality of connection terminals are arranged in a straight line, and the test point interfaces arranged in a plurality of straight lines are parallel to the plurality of connection terminals arranged in a straight line.
5. The chip of claim 4, wherein the number of test point interfaces is greater than the number of connection terminals.
6. The chip of claim 1, further comprising a wafer connected to a side of the primary interface remote from the primary control.
7. The chip of claim 1, wherein the total number of test point interfaces is 24.
8. The chip of claim 7, wherein the plurality of test point interfaces are arranged in a straight line and divided into a first test group, a second test group and a third test group, the first test group being disposed proximate to an edge of the substrate, the second test group being disposed proximate to the master control, the third test group being disposed between the first test group and the second test group.
9. The chip of claim 8, wherein the number of test point interfaces in the first test group is 16, the number of test point interfaces in the second test group is 4, and the number of test point interfaces in the third test group is 4.
10. A memory device comprising a circuit board, characterized in that the memory device further comprises a chip as claimed in any one of claims 1 to 9, said chip being connected to the circuit board.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321016492 | 2023-04-27 | ||
| CN2023210164924 | 2023-04-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220543352U true CN220543352U (en) | 2024-02-27 |
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ID=89965652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322073294.8U Active CN220543352U (en) | 2023-04-27 | 2023-08-03 | Chip and memory device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220543352U (en) |
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2023
- 2023-08-03 CN CN202322073294.8U patent/CN220543352U/en active Active
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Address after: 518000 floor 1, floor 2 and floor 3, No. 7, Xinfa East Road, Xiangshan community, Xinqiao street, Bao'an District, Shenzhen, Guangdong Province; No.5 1st, 2nd and 3rd floors Patentee after: Shenzhen Shi Creative Electronics Co.,Ltd. Country or region after: China Address before: Shenzhen Shishi Creative Electronics Co., Ltd., No. 5, Xinfa East Road, Xinqiao Street, Bao'an District, Shenzhen City, Guangdong Province, 518000 Patentee before: SHENZHEN SHICHUANGYI ELECTRONIC CO.,LTD. Country or region before: China |