CN218997914U - Optimized structure of copper-clad ceramic substrate in power semiconductor module - Google Patents

Abstract

The utility model discloses an optimized structure of a copper-clad ceramic substrate in a power semiconductor module, which is characterized in that an upper bridge copper-clad pattern, a lower bridge copper-clad pattern, a negative electrode copper-clad pattern, three-phase copper-clad patterns, an upper bridge Kelvin source electrode signal pattern, an upper bridge gate electrode signal pattern, a lower bridge gate electrode signal pattern, a plurality of upper bridge power semiconductor chips and lower bridge power semiconductor chips are arranged on the upper bridge copper-clad pattern and the lower bridge copper-clad pattern, the Kelvin source electrode and the gate electrode are connected with the corresponding signal patterns, a positive electrode busbar is connected with the upper bridge copper-clad patterns on two sides of the copper-clad ceramic substrate, a negative electrode busbar is connected with the negative electrode copper-clad pattern, the three-phase busbar is connected with the three-phase copper-clad pattern, and the lower bridge copper-clad pattern and the three-phase copper-clad pattern are connected through binding wires. The structure is connected with the bonding wire through the chip arrangement mode of the copper-clad ceramic substrate, the current grain design, and the length of the gate electrode and the Kelvin source electrode loop signal wire is adjusted, so that the current sharing characteristic and the low inductance characteristic of the power semiconductor module are realized, and the open tube reliability is ensured.

Description

Optimized structure of copper-clad ceramic substrate in power semiconductor module

Technical Field

The utility model relates to the technical field of power semiconductors, in particular to an optimized structure of a copper-clad ceramic substrate in a power semiconductor module.

Background

The power semiconductor module is formed by packaging the power semiconductor chips into a whole according to certain functional combination, has the advantages of small size, high power density and the like, and therefore, has wide application in the field of new energy automobiles. With the development of high power and long endurance of new energy automobiles, the application environment of the power semiconductor module is increasingly severe, and the current sharing characteristic and the voltage withstanding capability of the power semiconductor module are widely focused.

With the rapid development of new energy automobiles, si-based and SiC-based power semiconductor modules are continuously developed. In these high-power applications, higher and higher requirements are placed on the switching frequency of the power semiconductor modules. In order to obtain higher rated current and lower manufacturing cost, these power semiconductor modules generally employ a multi-chip parallel package structure. However, due to the fact that the current loop of the copper-clad ceramic substrate is asymmetric and dynamic and static parameters of the power chips are inconsistent, larger transient unbalanced current and stray inductance can occur among the parallel chips, and small challenges are brought to safety and stability of the power semiconductor module.

In the three-phase ac motor control system, a circuit diagram of the power semiconductor module is shown in fig. 1, in which a plurality of upper bridge power semiconductor chips a1 to a5 and lower bridge power semiconductor chips b1 to b5 are connected in parallel in each phase circuit, and a circuit diagram of the U-phase circuit diagram is shown in fig. 2 and 3, in which when the upper bridge power semiconductor chips are turned on and the lower bridge power semiconductor chips are turned off, current Ia flows from the positive electrode busbar to the three-phase busbar. The resistance value of the source and gate driving loop signals of each power semiconductor chip, the inductance generated by the length, the resistance between the power semiconductor chips, the inductance and the like determine the on-time of each power semiconductor. If the switching time of the power semiconductor chip a1 is earlier than that of the other power semiconductor chips a2 to a5, a large current intensively flows through the power semiconductor chip a1, and in an extreme case, damage to the power semiconductor chip a1 is caused; at this time, if the stray inductance of the upper bridge current loop is too large, the power semiconductor chips a1 to a5 are all at risk of voltage overcharge, so that the risk of damage of the power semiconductor chip a1 is further increased. Similarly, as shown in fig. 3, when the lower bridge power semiconductor chip is turned on and the upper bridge power semiconductor chip is turned off, the current Ib flows from the three-phase busbar to the negative electrode busbar. In this case, as described above, when the switching time of the power semiconductor chip b5 closest to the three-phase busbar is earlier than that of the other power semiconductor chips b1 to b4, current intensively flows through the power semiconductor chip b5, and in an extreme case, damage is caused to the power semiconductor chip b5; at this time, if the stray inductance of the lower bridge current loop is too large, the power semiconductor chips b1 to b5 are all at risk of voltage overcharge, so that the risk of damage of the power semiconductor chip b5 is further increased.

Among SiC power semiconductor modules for high-speed driving, a kelvin source is designed in some power semiconductor chips. The Kelvin source connection is a source that separates the power semiconductor chip into two parts, one for the main path through which large currents flow and the other for the return path for the gate drive signals. By uniformizing the sum of the signal line lengths from the power semiconductor chip gate, the kelvin source to the gate, the kelvin source signal terminal, variations in switching times of different power semiconductor chips can be reduced. In the case of the kelvin source connection, it is preferable that the total length Ltn of the gate signal line, the kelvin source signal line, and the signal line of each power semiconductor chip is equal to each other. Ltn is defined as follows:

Ltn=Lgn+Lkn

wherein, ltn is the total length; lgn is the sum of the signal line and the signal line length from the gate electrode to the gate electrode signal terminal of the chip; lkn is the sum of the signal line and the signal line length from the Kelvin source to the Kelvin source signal terminal of the chip.

In addition, when the SiC power semiconductor module is driven at a high speed, the voltage u=ldi/dt at two ends of the power semiconductor chip, if the design of the whole current loop including the copper-clad ceramic substrate is unreasonable, the stray inductance L is too large, which can cause the whole current loop to generate larger voltage overcharge, and even break down the power semiconductor chip in severe cases. When the copper-clad ceramic substrate is designed, the stray inductance of the whole current loop can be reduced through the design structures such as chip arrangement, symmetrical current lines, simplified current lines, binding connection modes and the like.

Disclosure of Invention

The utility model aims to solve the technical problem of providing an optimized structure of a copper-clad ceramic substrate in a power semiconductor module, and the optimized structure is characterized in that the lengths of a gate electrode and a Kelvin source electrode loop signal line are adjusted through the chip arrangement mode, the current line design and the bonding line connection of the copper-clad ceramic substrate, so that the consistency of the opening time of each power semiconductor chip is ensured, the parasitic inductance of an upper bridge, a lower bridge and the whole loop is reduced, the current sharing characteristic and the low inductance characteristic are realized, and the opening reliability of the power semiconductor module is ensured.

As shown in fig. 4, the present utility model is applicable to a power semiconductor module having a positive electrode busbar P and a negative electrode busbar N on one side, a three-phase busbar U, V, W on the opposite side, and 3 to 5 power semiconductor chips connected in parallel to upper and lower arms to carry a large current.

In order to solve the technical problems, the optimized structure of the copper-clad ceramic substrate in the power semiconductor module comprises a copper-clad ceramic substrate, a positive electrode busbar, a negative electrode busbar, a three-phase busbar, a plurality of upper bridge power semiconductor chips and a plurality of lower bridge power semiconductor chips, wherein upper bridge copper-clad lines extend from the upper part to the middle part on two sides of the copper-clad ceramic substrate, the upper part of the copper-clad ceramic substrate is provided with the negative electrode copper-clad lines between the upper bridge copper-clad lines on two sides, the positive electrode busbar is respectively connected with the upper bridge copper-clad lines on two sides of the copper-clad ceramic substrate and is positioned on the upper part of the copper-clad ceramic substrate, the negative electrode busbar is connected with the negative electrode copper-clad lines and is positioned on the upper part of the copper-clad ceramic substrate, the lower part of the copper-clad ceramic substrate is provided with three-phase copper-clad lines extending from the two sides, the three-phase busbar is connected with the three-phase copper-clad lines and is positioned on the lower part of the copper-clad ceramic substrate, the negative electrode copper-clad pattern is arranged below the negative electrode copper-clad pattern and between the upper bridge copper-clad patterns on two sides of the copper-clad ceramic substrate, a lower bridge Kelvin source electrode signal pattern, a lower bridge gate electrode signal pattern and a lower bridge copper-clad pattern are sequentially arranged above the three-phase copper-clad patterns, an upper bridge Kelvin source electrode signal pattern and an upper bridge gate electrode signal pattern are sequentially arranged above the three-phase copper-clad patterns, a plurality of upper bridge power semiconductor chips are transversely arranged at intervals on the upper bridge copper-clad pattern in the middle of the copper-clad ceramic substrate, the drain electrode is connected with the upper bridge copper-clad pattern, the gate electrode is connected with the upper bridge gate electrode signal pattern through the gate electrode signal wire, the Kelvin source electrode is connected with the upper bridge Kelvin source electrode signal pattern through the Kelvin source electrode signal wire, the source electrode is respectively connected with the three-phase copper-clad pattern through a second binding wire and connected with the lower bridge copper-clad pattern through a first binding wire, and the plurality of lower bridge power semiconductor chips are transversely arranged at intervals on the lower bridge copper-clad pattern, and the drain electrode is connected with the lower bridge copper-clad pattern, the gate is connected with the lower bridge gate signal line through the gate signal line, the Kelvin source is connected with the lower bridge Kelvin source signal line through the Kelvin source signal line, the source is connected with the negative electrode copper-clad line through the third binding line, and the lower bridge copper-clad line and the three-phase copper-clad line are connected through the first binding line, the upper bridge power semiconductor chip source and the second binding line or through the fourth binding line.

Further, the upper bridge Kelvin source electrode signal lines, the upper bridge gate electrode signal lines, the lower bridge Kelvin source electrode signal lines and the lower bridge gate electrode signal lines are arranged in parallel.

Further, the upper bridge gate electrode signal lines and the lower bridge gate electrode signal lines are bent to 180 degrees within the through length range, and the gates of the upper bridge power semiconductor chips and the gates of the lower bridge power semiconductor chips are respectively connected with the bent sections of the upper bridge gate electrode signal lines and the lower bridge gate electrode signal lines through the gate electrode signal lines.

Further, the upper bridge power semiconductor chips and the lower bridge power semiconductor chips are equidistantly arranged on the upper bridge copper-clad lines and the lower bridge copper-clad lines.

Further, the upper bridge power semiconductor chips and the lower bridge power semiconductor chips are arranged in the upper bridge copper-clad lines and the lower bridge copper-clad lines in a staggered manner.

Further, the upper bridge Kelvin source electrode signal line and the upper bridge gate electrode signal line are provided with an upper bridge Kelvin source electrode signal terminal and an upper bridge gate electrode signal terminal on the same side, and the lower bridge Kelvin source electrode signal line and the lower bridge gate electrode signal line are provided with a lower bridge Kelvin source electrode signal terminal and a lower bridge gate electrode signal terminal on the same side.

Further, the upper bridge copper-clad lines and the lower bridge copper-clad lines are respectively provided with an upper bridge drain electrode signal terminal and a lower bridge drain electrode signal terminal.

Further, the lengths from the gate pass gate signal line and the upper bridge gate signal line to the upper bridge gate signal terminal of each upper bridge power semiconductor chip are added to the sum of the lengths from the upper bridge source pass Kelvin source signal line and the upper bridge Kelvin source signal line to the upper bridge Kelvin source signal terminal of the upper bridge power semiconductor chip to be similar or equal; the length from the gate electrode through the gate electrode signal line and the lower bridge gate electrode signal line to the lower bridge gate electrode signal terminal of each lower bridge power semiconductor chip is increased by the sum of the lengths from the Kelvin source electrode through the Kelvin source electrode signal line and the lower bridge Kelvin source electrode signal line to the lower bridge Kelvin source electrode signal terminal of the lower bridge power semiconductor chip.

Further, the upper bridge kelvin source electrode signal line and the upper bridge gate electrode signal line are interchangeable, i.e. the upper bridge kelvin source electrode signal line is used as an upper bridge gate electrode signal line, and the upper bridge gate electrode signal line is used as an upper bridge kelvin source electrode signal line; the lower bridge Kelvin source electrode signal lines and the lower bridge gate electrode signal lines are interchangeable, namely the lower bridge Kelvin source electrode signal lines are used as lower bridge gate electrode signal lines, and the lower bridge gate electrode signal lines are used as lower bridge Kelvin source electrode signal lines.

Further, a fourth binding line between the lower bridge copper-clad lines and the three-phase copper-clad lines is positioned on the left side, the right side or the two sides of the extension parts of the three-phase copper-clad lines to the two sides of the copper-clad ceramic substrate.

Because the optimized structure of the copper-clad ceramic substrate in the power semiconductor module adopts the technical scheme, the structure is characterized in that an upper bridge copper-clad pattern, a lower bridge copper-clad pattern, a negative electrode copper-clad pattern, a three-phase copper-clad pattern, an upper bridge Kelvin source electrode signal pattern, an upper bridge gate electrode signal pattern, a lower bridge Kelvin source electrode signal pattern and a lower bridge gate electrode signal pattern are respectively arranged on the copper-clad ceramic substrate, a plurality of upper bridge power semiconductor chips and a plurality of lower bridge power semiconductor chips are respectively arranged on the upper bridge copper-clad pattern and the lower bridge copper-clad pattern, the Kelvin source electrode and the gate electrode are connected with the corresponding signal patterns, the positive electrode busbar is connected with the upper bridge copper-clad pattern on two sides of the copper-clad ceramic substrate, the negative electrode busbar is connected with the negative electrode copper-clad pattern, the three-phase busbar is connected with the three-phase copper-clad pattern, and the lower bridge copper-clad pattern and the three-phase copper-clad pattern are connected through binding wires. The structure is connected with the bonding wire through the chip arrangement mode of the copper-clad ceramic substrate, the current grain design, and the bonding wire, the length of the gate electrode and the length of the Kelvin source electrode loop signal wire are adjusted, the consistency of the opening time of each power semiconductor chip is ensured, the parasitic inductance of an upper bridge, a lower bridge and the whole loop is reduced, the current sharing characteristic and the low inductance characteristic are realized, and the opening reliability of the power semiconductor module is ensured.

Drawings

The utility model is described in further detail below with reference to the attached drawings and embodiments:

FIG. 1 is a schematic diagram of a power semiconductor module circuit logic;

FIG. 2 is a schematic diagram of the flow direction of a single-phase upper bridge current in a power semiconductor module;

FIG. 3 is a schematic diagram of the flow direction of a single-phase down-bridge current in a power semiconductor module;

fig. 4 is an overall block diagram of a power semiconductor module;

FIG. 5 is a schematic view of an optimized structure of a copper-clad ceramic substrate in a power semiconductor module according to the present utility model;

FIG. 6 is a partial view of the upper bridge of FIG. 5;

FIG. 7 is a partial view of the lower bridge of FIG. 5;

FIG. 8 is a schematic diagram of non-equidistant placement of the power semiconductor chips of FIG. 5;

fig. 9 is a schematic diagram of the power semiconductor chips in fig. 5 arranged in a staggered manner;

FIG. 10 is a schematic diagram of the arrangement of the opposite sides of the gate signal terminal and the Kelvin source signal terminal of FIG. 5;

FIG. 11 is a diagram showing the gate signal lines and Kelvin source signal lines of FIG. 5;

fig. 12 is a schematic diagram of four structures of the upper and lower bridge power semiconductor chips in fig. 5, respectively;

fig. 13 is a schematic diagram showing three structures of the upper and lower bridge power semiconductor chips in fig. 5, respectively;

fig. 14 and 15 are schematic diagrams of connection between the lower bridge copper-clad pattern and the three-phase copper-clad pattern in the present structure.

Detailed Description

An embodiment of the optimized structure of the copper-clad ceramic substrate in the power semiconductor module of the utility model is shown in fig. 5, which comprises a copper-clad ceramic substrate 1, a positive electrode busbar 2, a negative electrode busbar 3, a three-phase busbar 4, a plurality of upper bridge power semiconductor chips 5 and a plurality of lower bridge power semiconductor chips 6, wherein upper bridge copper-clad lines 11 extend from the upper part to the middle part at two sides of the copper-clad ceramic substrate 1, a negative electrode copper-clad line 12 is arranged between the upper bridge copper-clad lines 11 at two sides of the copper-clad ceramic substrate 1 at the upper part of the copper-clad ceramic substrate 1, the positive electrode busbar 2 is respectively connected with the upper bridge copper-clad lines 11 at two sides of the copper-clad ceramic substrate 1 and is positioned at the upper part of the copper-clad ceramic substrate 1, the negative electrode busbar 3 is connected with the negative electrode copper-clad line 12 and is positioned at the upper part of the copper-clad ceramic substrate 1, three-phase copper-clad lines 13 extend from the lower part to two sides of the copper-clad ceramic substrate 1, the three-phase busbar 4 is connected with the three-phase copper-clad lines 13 and is positioned at the lower part of the copper-clad ceramic substrate 1, a lower bridge Kelvin source electrode signal line 14, a lower bridge gate electrode signal line 15 and a lower bridge copper-clad line 16 are sequentially arranged below the negative electrode copper-clad line 12 and between the upper bridge copper-clad lines 11 on two sides of the copper-clad ceramic substrate 1, an upper bridge Kelvin source electrode signal line 17 and an upper bridge gate electrode signal line 18 are sequentially arranged above the three-phase copper-clad line 13, a plurality of upper bridge power semiconductor chips 5 are transversely arranged at intervals on the upper bridge copper-clad line 11 in the middle of the copper-clad ceramic substrate 1, the drain electrode is connected with the upper bridge copper-clad line 11, the gate electrode is connected with the upper bridge gate electrode signal line 18 through a gate electrode signal line 52, the Kelvin source electrode is connected with the upper bridge Kelvin source electrode signal line 17 through a Kelvin source electrode signal line 53, the source electrode is connected with the three-phase copper-clad line 13 through a second binding line 54, the source electrode is connected with the lower bridge copper-clad line 16 through a first binding line 51, the lower bridge power semiconductor chips 6 are transversely arranged at intervals on the lower bridge copper-clad lines, the drain electrode is connected with the lower bridge copper-clad lines 16, the gate electrode is connected with the lower bridge gate electrode signal lines 15 through the gate electrode signal lines, the Kelvin source electrode is connected with the lower bridge Kelvin source electrode signal lines 14 through the Kelvin source electrode signal lines, the source electrode is connected with the cathode copper-clad lines 12 through the third binding lines 56, and the lower bridge copper-clad lines 16 and the three-phase copper-clad lines 13 are connected through the first binding lines 51, the upper bridge power semiconductor chip 5 source electrode and the second binding lines 54 or through the fourth binding lines 55.

Preferably, the upper bridge kelvin source electrode signal line 17, the upper bridge gate electrode signal line 18, the lower bridge kelvin source electrode signal line 14 and the lower bridge gate electrode signal line 15 are arranged in parallel.

Preferably, the upper bridge gate signal lines 18 and the lower bridge gate signal lines 15 are bent into 180 degrees within the range of the pass length, and the gates of the upper bridge power semiconductor chips 5 and the gates of the lower bridge power semiconductor chips 6 are respectively connected with the bent sections of the upper bridge gate signal lines 18 and the lower bridge gate signal lines 15 through gate signal lines.

Preferably, the upper bridge power semiconductor chips 5 and the lower bridge power semiconductor chips 6 are equidistantly arranged on the upper bridge copper-clad pattern 11 and the lower bridge copper-clad pattern 16.

Preferably, the upper bridge power semiconductor chips 5 and the lower bridge power semiconductor chips 6 are arranged in the upper bridge copper-clad pattern 11 and the lower bridge copper-clad pattern 16 in a vertically staggered manner.

Preferably, the upper bridge kelvin source signal trace 17 and the upper bridge gate signal trace 18 are provided with an upper bridge kelvin source signal terminal 71 and an upper bridge gate signal terminal 72 on the same side, and the lower bridge kelvin source signal trace 14 and the lower bridge gate signal trace 15 are provided with a lower bridge kelvin source signal terminal 81 and a lower bridge gate signal terminal 82 on the same side.

Preferably, the upper bridge copper clad laminate 11 and the lower bridge copper clad laminate 16 are respectively provided with an upper bridge drain signal terminal 91 and a lower bridge drain signal terminal 92.

Preferably, the sum of the lengths of the gate pass gate signal line, the upper bridge gate signal line 18 and the upper bridge gate signal terminal 72 of each upper bridge power semiconductor chip 5 and the lengths of the kelvin source pass kelvin source signal line, the upper bridge kelvin source signal line 17 and the upper bridge kelvin source signal terminal 71 of the upper bridge power semiconductor chip is similar or equal; the sum of the lengths of the gate pass gate signal line, the lower bridge gate signal line 15 and the lower bridge gate signal terminal 82 of each lower bridge power semiconductor chip 6 and the lengths of the Kelvin source pass Kelvin source signal line, the lower bridge Kelvin source signal line 14 and the lower bridge Kelvin source signal terminal 81 of the lower bridge power semiconductor chip is similar or equal.

Preferably, the upper bridge kelvin source electrode signal line 17 and the upper bridge gate electrode signal line 18 are interchangeable, i.e. the upper bridge kelvin source electrode signal line 17 is used as the upper bridge gate electrode signal line 18, and the upper bridge gate electrode signal line 18 is used as the upper bridge kelvin source electrode signal line 17; the lower bridge kelvin source electrode signal line 14 and the lower bridge gate electrode signal line 15 are interchangeable, that is, the lower bridge kelvin source electrode signal line 14 is used as the lower bridge gate electrode signal line 15, and the lower bridge gate electrode signal line 15 is used as the lower bridge kelvin source electrode signal line 14.

Preferably, the fourth bonding wire 55 between the lower bridge copper-clad pattern 16 and the three-phase copper-clad pattern 13 is located at the left side, the right side or both sides of the extension portion of the three-phase copper-clad pattern 13 towards the two sides of the copper-clad ceramic substrate 1.

As shown in fig. 5, in the present optimized structure, voltage is applied to the positive and negative bus bars, the current flowing from the positive bus bar 2 on the left and right sides of the upper portion of the copper-clad ceramic substrate 1 is divided into two paths, which flow into the upper bridge copper-clad lines 11, the power semiconductor chips 5 (a 1 to a 5) of the upper bridge are laterally arranged on the upper bridge copper-clad lines 11, the current flows into the power semiconductor chips 5 of the upper bridge through the upper bridge copper-clad lines 11, and the current flows into the three-phase copper-clad lines 13 through the second bonding wires 54, and finally flows into the three-phase bus bars 4; the current flowing from the three-phase busbar 4 flows into the lower bridge copper-clad pattern 16 through the three-phase copper-clad pattern 13, the second bonding wire 54, the source electrode of the upper bridge power semiconductor chip 5, the first bonding wire 51 and the fourth bonding wire 55, the power semiconductor chips 6 (b 1-b 5) of the lower bridge are transversely arranged on the lower bridge copper-clad pattern 16, the current flows into the lower bridge power semiconductor chip 6 through the lower bridge copper-clad pattern 16, and the current flows into the negative electrode copper-clad pattern 12 through the bonding wire 56 and finally flows into the negative electrode busbar 3. The gate electrode of the upper bridge power semiconductor chip 5 is connected to the upper bridge gate electrode signal line 18 through a gate electrode signal line 52, and the Kelvin source electrode of the upper bridge power semiconductor chip is connected to the upper bridge Kelvin source electrode signal line 17 through a Kelvin source electrode signal line 53; the gate electrode of the power semiconductor chip of the lower bridge is connected to the lower bridge gate electrode signal line 15 through a gate electrode signal line, and the Kelvin source electrode of the power semiconductor chip of the lower bridge is connected to the lower bridge Kelvin source electrode signal line 14 through a Kelvin source electrode signal line. The gate signal lines 18 and 15 of the upper bridge and the lower bridge are respectively arranged in parallel with the Kelvin source signal lines 17 and 14 of the upper bridge and the lower bridge, the gate signal lines 18 and 15 of the upper bridge and the lower bridge are bent for 180 degrees in the through length range, and the gate signals of the power semiconductor chips of the upper bridge and the lower bridge are connected on the bent segment lines, so that the sum of the distances from the gate signal line, the gate signal line and the Kelvin source signal line of the power semiconductor chips of the same bridge arm to the gate signal terminal and the Kelvin source signal terminal is equal to or close to the sum of the distances from the Kelvin source signal line and the Kelvin source signal terminal.

Since the gate signal lines of all power semiconductor chips of the same bridge arm have the same length and the Kelvin source signal lines have the same length, the gate signal lines of the power semiconductor chips can be uniformly given by Lg and the Kelvin source signal lines can be uniformly given by Lk

As shown in fig. 6, the sum of the distances from the gate electrode, the kelvin source electrode through the gate electrode signal line, the gate electrode signal line and the kelvin source electrode signal line, the kelvin source electrode signal line to the gate electrode signal terminal, and the kelvin source electrode signal terminal of the power semiconductor chip of the upper bridge is calculated as follows:

ltn1= Lgn1+lkn1 of the power semiconductor chip a1

Wherein, ltn1 is the total length of the gate signal line, the kelvin source signal line and the signal line, lgn is the sum of the signal line and the signal line length from the gate to the gate signal terminal, lkn1 is the sum of the signal line and the signal line length from the kelvin source to the kelvin source signal terminal (the following is the same);

Lgn1= Ga+Ga_0+Ga_1+Lg，Lkn1=Ka_1+Lk，

so ltn1= Lgn1 +lkn1= (ga+ga_0) + (ga_1+ka_1) + (lg+lk)

Ltn2= Lgn2+lkn2 of the power semiconductor chip a2

Lgn2= Ga+Ga_0+Ga_2+Lg，Lkn2=Ka_2+Lk，

So ltn2= Lgn2 +lkn2= (ga+ga_0) + (ga_2+ka_2) + (lg+lk)

Ltn3= Lgn3+lkn3 of the power semiconductor chip a3

Lgn3= Ga+Ga_0+Ga_3+Lg，Lkn3=Ka_3+Lk，

So ltn3= Lgn3 +lkn3= (ga+ga_0) + (ga_3+ka_3) + (lg+lk)

Ltn4= Lgn4+lkn4 of the power semiconductor chip a4

Lgn4= Ga+Ga_0+Ga_4+Lg，Lkn4=Ka_4+Lk，

So ltn4= Lgn4 +lkn4= (ga+ga_0) + (ga_4+ka_4) + (lg+lk)

Ltn5= Lgn5+lkn5 of the power semiconductor chip a5

Lgn5= Ga+Ga_0+Ga_5+Lg，Lkn5=Ka_5+Lk，

So ltn5= Lgn5 +lkn5= (ga+ga_0) + (ga_5+ka_5) + (lg+lk)

Wherein Ga is the length from the head end to the bending end of the gate signal line, ga_0 is the bending length of the gate signal line, ga_1, ga_2, ga_3, ga_4 and Ga_5 are the lengths from the gate signal line connecting point of each power semiconductor chip gate electrode and gate signal line to the bending end of the gate signal line, ka_1, ka_2, ka_3, ka_4 and Ka_5 are the lengths from the head end of the Kelvin source signal line to the Kelvin source and Kelvin source signal line connecting point of each power semiconductor chip respectively.

As shown in fig. 6, ga_1+ka_1=ga_2+ka_2=ga_3+ka_3=ga_4+ka_4=ga_5+ka_5, and thus ltn1=ltn2=ltn3=ltn4=ltn5. Through the measures, the Ltn of the power semiconductor chips of the upper bridge is guaranteed to be equal, so that the opening time of each power semiconductor chip of the upper bridge is controlled to be equal, the current sharing characteristic is realized, and finally the opening reliability of the upper bridge of the power semiconductor module is guaranteed.

As shown in fig. 7, the sum of the distances from the gate electrode, the kelvin source electrode through the gate electrode signal line, the gate electrode signal line and the kelvin source electrode signal line, the kelvin source electrode signal line to the gate electrode signal terminal, the kelvin source electrode signal terminal of the power semiconductor chip of the lower bridge is calculated as follows:

ltn1= Lgn1+lkn1 of the power semiconductor chip b1

Lgn1= Gb+Gb_0+Gb_1+Lg，Lkn1=Kb_1+Lk

So ltn1= Lgn1 +lkn1= (gb+gb_0) + (gb_1+kb_1) + (lg+lk)

Ltn2= Lgn2+lkn2 of the power semiconductor chip b2

Lgn2= Gb+Gb_0+Gb_2+Lg，Lkn2=Kb_2+Lk，

So ltn2= Lgn2 +lkn2= (gb+gb_0) + (gb_2+kb_2) + (lg+lk)

Ltn3= Lgn3+lkn3 of the power semiconductor chip b3

Lgn3= Gb+Gb_0+Gb_3+Lg，Lkn3=Kb_3+Lk，

So ltn3= Lgn3 +lkn3= (gb+gb_0) + (gb_3+kb_3) + (lg+lk)

Ltn4= Lgn4+lkn4 of the power semiconductor chip b4

Lgn4= Gb+Gb_0+Gb_4+Lg，Lkn4=Kb_4+Lk，

So ltn4= Lgn4 +lkn4= (gb+gb_0) + (gb_4+kb_4) + (lg+lk)

Ltn5= Lgn5+lkn5 of the power semiconductor chip b5

Lgn5= Gb+Gb_0+Gb_5+Lg，Lkn5=Kb_5+Lk，

So ltn5= Lgn5 +lkn5= (gb+gb_0) + (gb_5+kb_5) + (lg+lk)

The meanings of Gb, gb_0, gb_1, gb_2, gb_3, gb_4, gb_5, and kb_1, kb_2, ba_3, kb_4, and kb_5 are the same as those of the calculation of the upper bridge, respectively.

As shown in fig. 7, gb_1+kb_1=gb_2+kb_2=gb_3+kb_3=gb_4+kb_4=gb_5+kb_5, so that ltn1=ltn2=ltn3=ltn4=ltn5. Through the measures, the Ltn of the power semiconductor chips of the lower bridge is guaranteed to be equal, so that the opening time of each power semiconductor chip of the lower bridge is controlled to be equal, the current sharing characteristic is realized, and finally the opening reliability of the lower bridge of the power semiconductor module is guaranteed.

The power semiconductor chips 5 and 6 of the upper bridge and the lower bridge are respectively transversely arranged on the upper bridge copper-clad lines 11 and the lower bridge copper-clad lines 16, and the power semiconductor chips 5 and 6 of the single bridge arm are transversely arranged at equal intervals. As a modification of this structure, as shown in fig. 8, several power semiconductor chips 5, 6 of a single bridge arm may be arranged at unequal intervals in the lateral direction.

As shown in fig. 9, as a modification of the present structure, the upper and lower power semiconductor chips 5, 6 of the single bridge arm are arranged in a staggered manner up and down in the lateral direction on the upper bridge copper clad laminate 11 and the lower bridge copper clad laminate 16, respectively.

As shown in fig. 10, as a modification of the present structure, the upper bridge gate signal terminal 72 is arranged on the opposite side from the kelvin source signal terminal 71, and the lower bridge gate signal terminal 82 is arranged on the opposite side from the kelvin source signal terminal 81, so that the sum of the distances from the gate signal line, the kelvin source line and the kelvin source signal line, the kelvin source signal line to the gate signal terminal, the kelvin source signal terminal is equal or close to the gate, the kelvin source of several power semiconductor chips of the same bridge arm.

As shown in fig. 11, as a modification of the present structure, the definition of the gate signal traces 18, 15 of the upper and lower bridges and the definition of the kelvin signal traces 17, 14 may be interchanged, that is, the gate signal trace 18 of the upper bridge becomes the kelvin source signal trace, the kelvin source signal trace 17 becomes the gate signal trace, and likewise, the gate signal trace 15 of the lower bridge becomes the kelvin source signal trace, and the kelvin source signal trace 14 becomes the gate signal trace.

As shown in fig. 12 and 13, each bridge arm in the structure is formed by connecting three or four power semiconductor chips in parallel, three or four power semiconductor chips 5 of an upper bridge are transversely arranged on the upper bridge copper-clad pattern 11, and three or four power semiconductor chips 6 of a lower bridge are transversely arranged on the lower bridge copper-clad pattern 16.

As shown in fig. 14 and 15, as a modification of the present structure, the lower bridge copper clad laminate 16 and the three-phase copper clad laminate 13 are connected by a first bonding wire 51, a source electrode of the upper bridge power semiconductor chip 5, a second bonding wire 54, or a fourth bonding wire 55.

The structure aims at the problems of uneven parallel current and larger stray inductance of the power semiconductor modules connected in parallel by multiple chips, and provides an optimized structure for the copper-clad ceramic substrate.

Claims (10)

1. The utility model provides an optimized structure of covering copper ceramic substrate in power semiconductor module, includes covering copper ceramic substrate, anodal busbar, negative pole busbar, three-phase busbar, a plurality of bridge power semiconductor chips and a plurality of bridge power semiconductor chips down, its characterized in that: the copper-clad ceramic substrate is provided with upper bridge copper-clad lines extending from the upper part to the middle part, the upper part of the copper-clad ceramic substrate is provided with negative electrode copper-clad lines between the upper bridge copper-clad lines on the two sides, the positive electrode busbar is respectively connected with the upper bridge copper-clad lines on the two sides of the copper-clad ceramic substrate and is positioned on the upper part of the copper-clad ceramic substrate, the negative electrode busbar is connected with the negative electrode copper-clad lines and is positioned on the upper part of the copper-clad ceramic substrate, the lower part of the copper-clad ceramic substrate is provided with three-phase copper-clad lines extending to the two sides, the three-phase busbar is connected with three-phase copper-clad lines and is positioned on the lower part of the copper-clad ceramic substrate, the lower bridge Kelvin source electrode signal lines, lower bridge gate electrode signal lines and lower bridge copper-clad lines are sequentially arranged between the upper bridge copper-clad lines on the two sides of the copper-clad ceramic substrate, the upper bridge Kelvin source electrode signal lines and the upper bridge gate electrode signal lines are sequentially arranged above the three-phase copper-clad lines, the upper bridge power semiconductor chips are transversely and alternately arranged on upper bridge copper-clad lines in the middle of the copper-clad ceramic substrate, the drain electrode is connected with the upper bridge copper-clad lines, the gate electrode is connected with the upper bridge gate electrode signal lines through the gate electrode signal lines, the Kelvin source electrode is connected with the upper bridge Kelvin source electrode signal lines through the Kelvin source electrode signal lines, the source electrode is respectively connected with three-phase copper-clad lines through second binding lines and with lower bridge copper-clad lines through first binding lines, the lower bridge power semiconductor chips are transversely and alternately arranged on the lower bridge copper-clad lines, the drain electrode is connected with the lower bridge copper-clad lines, the gate electrode is connected with the lower bridge gate electrode signal lines through the gate electrode signal lines, the Kelvin source electrode is connected with the lower bridge Kelvin source electrode signal lines through the Kelvin source electrode signal lines, the source electrode is connected with the negative bridge copper-clad lines through third binding lines, the lower bridge copper-clad lines and the three-phase copper-clad lines are connected through a first bonding wire, an upper bridge power semiconductor chip source electrode and a second bonding wire or through a fourth bonding wire.

2. The optimized structure of copper-clad ceramic substrates in a power semiconductor module according to claim 1, characterized in that: the upper bridge Kelvin source electrode signal lines, the upper bridge gate electrode signal lines, the lower bridge Kelvin source electrode signal lines and the lower bridge gate electrode signal lines are arranged in parallel.

3. The optimized structure of copper-clad ceramic substrates in a power semiconductor module according to claim 1, characterized in that: the upper bridge gate electrode signal lines and the lower bridge gate electrode signal lines are bent to 180 degrees within the range of the pass length, and the gates of the upper bridge power semiconductor chips and the gates of the lower bridge power semiconductor chips are respectively connected with the bending sections of the upper bridge gate electrode signal lines and the lower bridge gate electrode signal lines through the gate electrode signal lines.

4. The optimized structure of copper-clad ceramic substrates in a power semiconductor module according to claim 1, characterized in that: the upper bridge power semiconductor chips and the lower bridge power semiconductor chips are equidistantly arranged on the upper bridge copper-clad lines and the lower bridge copper-clad lines.

5. The optimized structure of copper-clad ceramic substrates in a power semiconductor module according to claim 1, characterized in that: the upper bridge power semiconductor chips and the lower bridge power semiconductor chips are arranged in the upper bridge copper-clad lines and the lower bridge copper-clad lines in a staggered mode.

6. The optimized structure of copper-clad ceramic substrates in a power semiconductor module according to claim 1, characterized in that: the upper bridge Kelvin source electrode signal lines and the upper bridge gate electrode signal lines are provided with upper bridge Kelvin source electrode signal terminals and upper bridge gate electrode signal terminals on the same side, and the lower bridge Kelvin source electrode signal lines and lower bridge gate electrode signal lines are provided with lower bridge Kelvin source electrode signal terminals and lower bridge gate electrode signal terminals on the same side.

7. The optimized structure of copper-clad ceramic substrates in a power semiconductor module according to claim 1, characterized in that: the upper bridge copper-clad lines and the lower bridge copper-clad lines are respectively provided with an upper bridge drain electrode signal terminal and a lower bridge drain electrode signal terminal.

8. The optimized structure of copper-clad ceramic substrates in a power semiconductor module according to claim 6, characterized in that: the lengths from the gate pass gate signal line and the upper bridge gate signal line to the upper bridge gate signal terminal of each upper bridge power semiconductor chip are added with the sum of the lengths from the upper bridge Kelvin source pass Kelvin source signal line and the upper bridge Kelvin source signal line to the upper bridge Kelvin source signal terminal of the upper bridge power semiconductor chip to be similar or equal; the length from the gate electrode through the gate electrode signal line and the lower bridge gate electrode signal line to the lower bridge gate electrode signal terminal of each lower bridge power semiconductor chip is increased by the sum of the lengths from the Kelvin source electrode through the Kelvin source electrode signal line and the lower bridge Kelvin source electrode signal line to the lower bridge Kelvin source electrode signal terminal of the lower bridge power semiconductor chip.

9. The optimized structure of copper-clad ceramic substrates in a power semiconductor module according to claim 1, characterized in that: the upper bridge Kelvin source electrode signal lines and the upper bridge gate electrode signal lines are interchangeable, namely the upper bridge Kelvin source electrode signal lines are used as upper bridge gate electrode signal lines, and the upper bridge gate electrode signal lines are used as upper bridge Kelvin source electrode signal lines; the lower bridge Kelvin source electrode signal lines and the lower bridge gate electrode signal lines are interchangeable, namely the lower bridge Kelvin source electrode signal lines are used as lower bridge gate electrode signal lines, and the lower bridge gate electrode signal lines are used as lower bridge Kelvin source electrode signal lines.

10. The optimized structure of copper-clad ceramic substrates in a power semiconductor module according to claim 1, characterized in that: and a fourth binding line between the lower bridge copper-clad lines and the three-phase copper-clad lines is positioned at the left side, the right side or the two sides of the extension parts of the three-phase copper-clad lines to the two sides of the copper-clad ceramic substrate.

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