WO2021130290A1

WO2021130290A1 - Power module with improved electrical characteristics

Info

Publication number: WO2021130290A1
Application number: PCT/EP2020/087734
Authority: WO
Inventors: Henning STRÖBEL-MAIER; Jörg BERGMANN
Original assignee: Danfoss Silicon Power Gmbh
Priority date: 2019-12-28
Filing date: 2020-12-23
Publication date: 2021-07-01

Abstract

A power semiconductor module (1) comprising; two or more semiconductor switching components (11-14, 64-70, 74-77, 501-504) which are electrically connected in parallel, wherein the first power contacts of each switching component (11-14, 64-70, 74-77, 501-504) are electrically connected to a first track (41, 61, 71), wherein the second power contacts of each switching component (11-14, 64-70, 74- 77, 501-504) are electrically connected to a second track (42, 62, 72) by a connecting means (37, 43, 48, 49, 63), and wherein the ratio R of the maximum linear extent (LI) of the landing area (45) of the connecting means (37, 43, 48, 49, 63) on the second track (42, 62, 72) to the length (L2) of the shortest distance connecting all of the geometric centres of the second power contacts is less and or equal to 70%.

Description

Power module with improved electrical characteristics Semiconductor power modules are widely used in industry. For example, such a power module may be used for the controlled switching of high currents and can be used in power converters (such as inverters) to convert DC to AC or vice versa, or for converting between different voltages or frequencies of AC. Such inverters are used in motor controllers or interfaces between power generation or storage, or a power distribution grid. In addition, power modules are being increasingly utilised in vehicles, in particular electrical or hybrid vehicles, where the conversion or control of electrical power is important. In such an application, there are very great constraints on size, weight and efficiency.

A semiconductor power module is designed to fulfil two major characteristics: High power conversion efficiency and high power density. Factors such as lifetime, cost and quality are also taken into account. In order to achieve a high power density, high performance wide-bandgap semiconductors, such as Silicon Carbide (SiC) semiconductor switches may be used, since they generally outperform standard silicon-based semiconductor switches, e.g. Insulated Gate Bipolar Transistors (IGBT). SiC devices put high demands on the design of the power module from thermal and electrical standpoint. The wide- bandgap semiconductors (e.g., SiC semiconductor switches) have the characteristic that they can switch very quickly, meaning that the transition from conduction to blocking mode takes only a few nanoseconds.

SiC MOSFETs are used as the semiconductor switches in applications where highest efficiency in a small volume is required by the application. SiC MOSFETs show fast switching speeds and low on-state resistance at the same time. Since SiC wafers are expensive to manufacture, and with current manufacturing processes it is hard to fabricate components with an acceptably low crystal failure amount, the die are typically very small (for example, 5-25mm²). This keeps yield losses low, but restricts the total current that a SiC semiconductor switches can pass. In order to achieve high output powers, several of these small semiconductor switches (for example MOSFETs) need to be operated in parallel. In applications such as automotive power conversion, the use of multiple semiconductor switches in parallel takes up space within the semiconductor power module, yielding potentially larger modules. However, space is at a premium within a vehicle, and increasing the size of modules is not generally an option. It is therefore a great advantage if innovative design of layouts can both accommodate multiple semiconductor switches in parallel, a balanced (symmetric) operation, low stray inductance and small overall layout size.

It is known that when a power module contains more than one switch which is connected in parallel, it is often difficult to ensure that the switches switch simultaneously and/or pass equal currents during the switching cycle. This is because the different commutation loops and gate emitter couplings found in real-world layouts often disturb the switching behaviour. It is important to find a way to switch all parallel semiconductors at the same time with the same switching behaviour.

A standard module often has the disadvantage that the dies of the different switching function are placed in a row. That makes it difficult to create equal commutation loops. This is illustrated in Fig. 1A and Fig. IB in which is shown a prior art layout wherein a set of semiconductor switches 401-404, are mounted on a positive load track 41 and are electrically connected to a negative load track 42 via a set of wire bonds An example of such an embodiment of might be a set of SiC MOSFETs 401-404 mounted on the DC positive track 41 via their drain contacts and with the source and gate contacts facing away from the DC positive track 41. The source contacts are connected via wire bonds 43 to the DC negative track 42.

In Fig. IB, arrows denote the paths of currents in the commutation loops of the semiconductor switches 401, 404 placed at the ends of the row of semiconductor switches. It can be clearly seen that the lengths of these arrows, and thus the areas of the final commutation loops, are significantly different for this particular layout.

An additional consideration is the effect of inductance on the switching behaviour. This is particularly influenced by stray induced voltage since on the source side since the gate action is dominated by the gate- source voltage.

Induced voltages on the source side can markedly delay the turn-on or turn-off time of the semiconductor switch. These induced voltages are dependent upon the induction inherent in the layout of the circuit connected to the source. Specifically, differing circuit routing lengths from a common voltage point to the individual source connections of each paralleled semiconductor switch will change the time of switching of individual switches and must therefore be taken into consideration when driving the module. In prior art layouts such as that seen in Fig. 1A and Fig. IB, we can see that there are significantly different circuit routing lengths (asymmetries) between the common voltage point, here the negative supply pad marked and the source connection of each of the semiconductors 401-404.

Such asymmetries mean that a safety margin/derating must be applied to every power module with parallel switches. The safety margin/derating which must be applied strongly depends on the asymmetry of the switching, and leads to a power module being used far below its theoretical current switching capabilities, and thus at a reduced efficiency.

The current invention significantly decreases the path length differences, and thus improves the performance of the power module which utilises the invention. Summary of the invention

The current invention leads to a power module layout which improves the equality of commutation loops between paralleled semiconductor switches in comparison with prior art power modules.

Additionally, the inventive layout effectively accelerates the switching of semiconductor switches with longer commutation loops, and slows down those with shorter commutation loops. This enables an even more symmetric switching behaviour.

It is, thus, an object of the present invention to provide a power module where minimum safety margin/derating is required allowing a much more effective and efficient use.

It is a further object of the present invention to provide a semiconductor power module with an improved symmetry of switching behaviour. Such symmetric behaviour allows the current capability of the semiconductor switches to be fully utilised, leading to much more cost-effective applications.

According to a first aspect of the present invention the above and other objects are fulfilled by providing a power semiconductor module comprising; two or more semiconductor switching components which are electrically connected in parallel, wherein the first power contacts of each switching component are electrically connected to a first track, wherein the second power contacts of each switching component are electrically connected to a second track by a connecting means, and wherein the ratio R of the maximum linear extent of the landing area of the connecting means on the second track to the length of the shortest distance connecting all of the geometric centres of the second power contacts is less and or equal to 70%.

The term "semiconductor switching components" is here used to include any of a number of known semiconductor switching devices. Examples of such devices are Thyristors, JFETs, IGBTs and MOSFETs, and they may be based on traditional silicon technology or wide-bandgap technologies such as silicon carbide (SiC). Gallium nitride (GaN) devices may also suitable.

The terms "the first power contacts" and "the second power contacts" refer to the areas on the semiconductor switching components by which the switched currents enter or leave the semiconductor switching components. In a typical IGBT, for example, the first power contact may be the collector contact on the base of the IGBT die, and the second power contact may be the emitter contact found on the upper surface of the die.

The term "track" is here used to specify a circuit track formed from a metal layer forming part of a substrate and insulated from other tracks by a gap. Some tracks may be suitable for carrying a large current, such as that supplying the electrical load for which the power module is supplying power. Suitability for large currents may be a combination of the width of the track and thickness of the track, forming a large cross- sectional area and thus allowing the passage of large currents without undue heating.

The substrate may comprise an insulating base, with conducting tracks to form the circuitry required, attached to the insulating base. A suitable substrate may be a DBC (direct bonded copper) substrate formed of two conducting copper layers either side of an insulating ceramic layer. Other suitable substrates may include DBA (direct bonded aluminium) or other substrates well known in the field.

By "landing area" is meant a theoretical line which encloses all of the ends of the connecting means where they are attached to the second track, and by "linear extent" is meant the distance in the plane of the landing area between entry and exit points of any line which intersects the landing area. The "maximum linear extent" is that linear extent of the line having the greatest linear extent. This parameter is a measure of the spatial spread of the ends of the connecting means where they are connected to the second track.

The ratio R in percent is calculated using the formula:

LI

R = — X 100%

L

Where LI is the maximum linear extent of the landing area of the connecting means on the second track and L2 is the length of the shortest distance connecting all of the geometric centres of the second power contacts.

The connecting means may comprise a wire bond, electrically conducting tape, such as a ribbon bond, or an electrically conducting braid such as a woven or knitted braid with multiple strands.

In another preferred embodiment of the invention, the ratio R is less than or equal to 60%.

In an even more preferred embodiment of the invention, the ratio R is between 10% and 60%.

In another embodiment of the invention, the first power contacts of each switching component are electrically connected to the first track by being mounted on the first track.

The term "mounted" is here used to mean the permanent connection of a device to a track, and may include an electrically conducting connection. Means of such connections include soldering, brazing and sintering.

In alternative embodiment of the invention, the first power contacts of each switching component are connected to the first track by being electrically connected by wire bonds. Description of the Drawings

The invention will become more fully understood from the detailed description given herein below. The accompanying drawings are given by way of illustration only, and thus, they are not limitative of the present invention. In the accompanying drawings:

Fig. 1 shows a prior art layout of a semiconductor power module; Fig. 2 shows a first embodiment of the inventive power module; Fig. 3 shows a representation of a second embodiment of the inventive power module; Fig. 4 shows a representation of a third embodiment of the inventive power module;

Fig. 5 shows a fourth embodiment of the inventive power module; Fig. 6 shows a representation of a fifth embodiment of the inventive power module; Fig. 7 shows a plot of modelled current in four of the semiconductor switches of the fifth embodiment;

Fig. 8 shows a prior art layout; Fig. 9 shows a plot of the modelled current in four of the semiconductor switches of the prior art layout shown in Fig.

8;

Fig. 10 shows a perspective view of the fifth embodiment of the inventive power module;

Fig. 11 shows a sixth embodiment of the inventive power module;

Fig. 12 shows a seventh embodiment of the inventive power module which utilises lateral semiconductor devices, and

Fig. 13 shows a cross section through an embodiment a power module including features of the current invention. Detailed description of the invention

Referring now in detail to the drawings for the purpose of illustrating preferred embodiments of the present invention, a first embodiment of the inventive power module 1 is shown in Fig. 2A. A set of semiconductor switches 501-504 are mounted on a positive load track 41 and are electrically connected to a negative load track 42 via a set of wirebonds 43. The landing area 45 of the wirebonds 43 are substantially smaller than the extent of the semiconductor switches 501-504 themselves. The ratio of the maximum linear extent LI of the landing area 45 of the wirebonds 43 to the length L2 of the shortest distance connecting all of the geometric centres of the second power contacts is 50%. The distribution of the wirebonds in this way improves performance, since the difference between the length of the commutation loops through the semiconductor switches in the extreme positions is greatly reduced. This can be seen by the arrows describing the shortest 46 and longest 47 commutation loops shown in Fig. 2B. Comparison with the prior art layout shown in Fig. IB illustrates how the difference between the shortest and longest commutation loops is greatly reduced in this first embodiment of the invention, compared with the prior art.

An additional consideration is the effect of inductance on the switching behaviour. This is particularly influenced by stray induced voltages.

This can be clearly illustrated in the embodiment shown in Fig. 2A and Fig 2B where the semiconductor switches 501-504 are a set of SiC MOSFETs mounted on the DC positive track 41 via their drain contacts and with their source and gate contacts facing away from the DC positive track 41. The source contacts are connected, via wire bonds 43, to the DC negative track 42. In this case, the gate action is dominated by the gate-source voltage and any induced voltages on the source side can markedly delay the turn-on or turn-off time of the semiconductor switches. These induced voltages are dependent upon the induction inherent in the layout of the circuit connected to the source. Specifically, differing circuit routing lengths from a common voltage point to the individual source connections of each paralleled semiconductor switch will change the time of switching of individual switches, and must therefore be taken into consideration when driving the module. In prior art layouts (such as that seen in Fig. 1A and Fig. IB), there may be significantly different circuit routing lengths (asymmetries) between a common voltage point and the source connection of each of the semiconductors. Such asymmetries are greatly reduced in the layout shown in Fig. 2A and Fig. 2B, where the circuit routing lengths between the common voltage point, here the negative supply pad 520, and the source connection of each of the semiconductors 501-504 do not show such great differences as are shown in the equivalent prior art layout shown in Fig. 1A and Fig. IB.

This reduction in asymmetries means that the safety margin/derating which needs to be applied is, in turn, reduced, allowing the power module to be used much closer to its theoretical current switching capabilities and so the efficiency of the module in service is significantly increased in comparison with prior art power modules.

Fig. 3 shows a representation of a second embodiment of the invention in which the connecting means are formed from electrically conducting tape or ribbon 48.

Fig. 4 shows a representation of a third embodiment of the invention, in which the connecting means of formed from an electrically conducting braid 49. Here, instead of a ribbon in the form of a metal strip, the connection is established very advantageously by means of a multiple- stranded wire or braid. The connection of the multiple- stranded wire to the contact points is possible can be made by means of ultrasound- assisted methods. However, the connection of the multiple-stranded wire by soldering or by silver sintering is also possible. Compared with the solid-material structure of a ribbon, the woven structure of the multiple- stranded wire affords the advantage of elasticity under thermomechanical loads. The multiple-stranded wire can deform in the plane, whereas a ribbon can obtain the elasticity only in certain directions as a result of the loop routing.

A fourth embodiment of the inventive module comprises the substrate, layout of tracks and distribution of semiconductors shown in Fig. 5.

Here, the substrate 2 comprises an inner load track 4, two intermediate load tracks 5, 6 and two outer load tracks 7, 8, each of which load tracks is elongated and extends substantially across the substrate 2 in a first direction 9. The two intermediate load tracks 5, 6 are arranged adjacent to the inner load track 4, and each outer load track 7, 8 is arranged on the opposite side of one of the two intermediate load tracks 5, 6 to that of the inner load track 4 with respect to a second direction 10, which is substantially orthogonal to the first direction 9. Also shown are two first sets of semiconductor switches 15-18, 19-22, each first set of semiconductor switches being mounted on the inner load track 4 and electrically connected to an intermediate load track 5,

6, such that the first sets of semiconductor switches form a first arm of the half bridge. The module also comprises two second sets of semiconductor switches 11-14, 23-26, each second set of semiconductor switches being mounted on an intermediate load track 5, 6 and electrically connected to an outer load track 7, 8, such that the second sets of semiconductor switches form a second arm of the half bridge. Landing pads for connection of external terminals are also shown here. That for the positive terminal 52 is placed on the inner load track 4, and those landing pads for the positive terminals 53 are placed on the track connecting the two outer load tracks 7, 8. A landing pad for the AC terminal is shown on the track connecting the two intermediate load tracks 5,6. Also illustrated in Fig. 5 are the placement of gate tracks 50 and sense tracks 51. The ratio R of the maximum linear extent LI of the landing area of the wirebonds to the length L2 of the shortest distance connecting all of the geometric centres of the second power contacts of 11-14 is 69%.

Fig. 6 is a representation of a fifth embodiment, based on that shown in Fig. 5, here showing the DC 56, 57 and AC terminal 55, together with control terminals 58. Fig. 7 is a plot of modelled current in four of the semiconductor switches 11-14 of the fifth embodiment shown in Fig. 6, during a switching event. The currents through each of the semiconductor switches 11-14 against time are shown by the plotted curves 211-214 respectively. As can be seen from the plot, the maximum spread of currents DI1 is around 31 A.

It is interesting to compare this with a prior art layout such as that shown in Fig. 8. This prior art layout is very similar to that shown in Fig. 6, the fifth embodiment of the current invention, but the distribution of landing points of the wirebonds from the semiconductor switches 1 Il 114 are significantly different to the fifth embodiment, since the ratio R of the maximum linear extent LI of the landing area of the wirebonds to the length L2 of the shortest distance connecting all of the geometric centres of the second power contacts of 111-114 is 100%.

Fig. 9 is a plot of the modelled current in four of the semiconductor switches 111-114 of the prior art layout shown in Fig. 8 during a switching event. The modelled currents are shown by the plotted curves 311-314 respectively. Here, under identical modelling conditions to those used for the data in Fig. 7, the maximum spread of currents DI2 is around 160 A. The two plots in Fig. 7 and Fig. 9 shows a significant improvement in the symmetry of current in a plurality of semiconductor switches during a switching event.

By exploring various other modelling scenarios, the applicants have found that reducing the ratio R of the maximum linear extent LI of the landing area of the wirebonds to the length L2 of the shortest distance connecting all of the geometric centres of the second power contacts still further, for example so that it was 20% or less, did not, in fact, yield significant gains in the symmetry of currents through different semiconductor switches. Thus, it would appear that an optimum ratio R is around 50-70%.

Fig. 10 shows a perspective view of the fifth embodiment with the substrate 2, semiconductor switches 11-14, load terminals 56, 57, 55 and control terminals 58 attached.

Fig. 11 shows a sixth embodiment of the invention. Here, the substrate 2 comprises two tracks the positive 61 and the negative track 62. Load terminals 146, 147 for external connections are also shown. Seven semiconductor switches 64-70 are shown distributed in a semicircle with inwardly pointing wire bond connections 63. In this layout, the ratio R of the maximum linear extent LI of the landing area of the wirebonds to the length L2 of the shortest distance connecting all of the geometric centres of the second power contacts of 64-70 is 25%.

Fig. 12 shows a seventh embodiment of the invention which utilises lateral semiconductor devices such as GaN semiconductors. Here 72 indicates a track of a first polarity and 71 that of the other polarity. The semiconductor switches 74-77 and distributed with their wirebonds angled inwards towards the track of first polarity 72. In this embodiment, the ratio of the maximum linear extent LI of the landing area of the wirebonds to the length L2 of the shortest distance connecting all of the geometric centres of the second power contacts of 64-70 is 70%. The load terminals 540 and 530 are connected to the track of first polarity 72 and the track of the other polarity 71 respectively.

Fig. 13 shows a cross section through an embodiment of a power module 1 including features of the current invention and showing in more detail the structure of the substrate 2. Here, the substrate 2 is a direct bonded copper (DBC) substrate comprising a lower copper layer 34, a ceramic core 35 and an upper copper layer 33. The upper copper layer 33 has been formed as individual conducting tracks which form the circuitry connecting components which form the electronics of the semiconductor power module. Connections between a semiconductor switch 36 and an adjacent track are made here by a wirebond 37. Also shown is a lead frame 39 which connects one of the tracks to the outside of the module. Such a lead frame connection may be used for power and/or control connections in and out of the power module. In this embodiment the power module is encased in a mould compound 38 which protects the circuitry and components within the module from humidity, dust or physical damage.

Claims

1. A power semiconductor module (1) comprising two or more semiconductor switching components (11-14, 64-70, 74- 77, 501-504) which are electrically connected in parallel, wherein the first power contacts of each switching component (11-14, 64-70, 74-77, 501-504) are electrically connected to a first track (41, 61, 71), wherein the second power contacts of each switching component (11- 14, 64-70, 74-77, 501-504) are electrically connected to a second track (42, 62, 72) by a connecting means (37, 43, 48, 49, 63), and wherein the ratio R of the maximum linear extent (LI) of the landing area (45) of the connecting means (37, 43, 48, 49, 63) on the second track (42, 62, 72) to the length (L2) of the shortest distance connecting all of the geometric centres of the second power contacts is less and or equal to 70%.

2. A power semiconductor module (1) according to claim 1, wherein the connecting means (43, 63) comprises a wire bond.

3. A power semiconductor module (1) according to any of the preceding claims, wherein the connecting means (48) comprises an electrically conducting tape.

4. A semiconductor power module (1) according to any of the preceding claims, wherein the connecting means (49) comprises an electrically conducting braid.

5. A semiconductor power module (1) according to any of the preceding claims, wherein the ratio R is less than or equal to 60%.

6. A semiconductor power module (1) according to any of the preceding claims, wherein the ratio R is between 10% and 60%.

7. A semiconductor power module (1) according to any of the preceding claims, wherein the two or more of the semiconductor switching components (11-14, 64-70, 74-77, 501-504) are based on wide- bandgap technologies.

8. A semiconductor power module (1) according to any of the preceding claims, wherein the two or more of the semiconductor switching components (11-14, 64-70, 74-77, 501-504) are based on silicon carbide (SiC) technologies.

9. A semiconductor power module (1) according to any of the preceding claims, wherein the two or more of the semiconductor switching components (11-14, 64-70, 74-77, 501-504) are based on Gallium nitride (GaN) technologies.

10. A semiconductor power module (1) according to any of the preceding claims, wherein the first power contacts of each switching component (11-14, 64-70, 501-504) are electrically connected to the first track (41, 61) by being mounted on the first track.

11. A semiconductor power module (1) according any of claims 1-9, wherein the first power contacts of each switching component (74-77) are electrically connected to the first track (71) by wire bonds (43).