JP7208966B2 - semiconductor equipment - Google Patents

Description

The present invention relates to semiconductor devices.

Patent Document 1 discloses a semiconductor device including a trench gate type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). This semiconductor device includes a semiconductor substrate in which a plurality of trenches are formed, gate electrodes embedded in the trenches with a gate insulating film interposed therebetween, and sequentially formed on the sides of the trenches in the depth direction from the surface side of the substrate. an n-type source region, a p-type body region and an n-type drift region.

JP 2010-267677 A JP 2015-149402 A

In the semiconductor device of Patent Document 1, a channel formation region serving as a current path is provided on both side surfaces of each trench, and heat is generated on both side surfaces of the trench as the channel formation region is energized. It is configured to In the case of such a configuration, the heat generated on both side surfaces of the trench may interact with each other over the entire area of both side surfaces of the trench. There is

By the way, the semiconductor device as disclosed in Patent Document 1 is sometimes required to have a function of absorbing energy emitted from the inductive load when it is turned off. If the energy given to the semiconductor device from the inductive load exceeds a predetermined value, the semiconductor device may fail due to temperature rise. The amount of energy stored in an inductive load that can be absorbed is represented by the dynamic clamping capability. The higher the value of the dynamic clamping capability, the more energy stored in the inductive load can be absorbed.

In a semiconductor device such as that disclosed in Patent Document 1, when the energy of an inductive load is received, a portion of the substrate becomes transiently and locally heated to a high temperature. There is a risk that it will not be possible to absorb the energy that has been applied. Then, it becomes difficult to achieve a good dynamic clamp tolerance.
The inventors of the present application have found that a semiconductor device with a smaller temperature rise exhibits a relatively higher numerical value with respect to the dynamic clamp tolerance. Therefore, it is considered that the dynamic clamp tolerance can be improved by reducing the ratio of the area of the channel forming region per unit area to suppress the heat generation. However, in this case, since the area of the channel forming region is reduced, there is a trade-off problem in that the on-resistance is increased.

Therefore, the present disclosure provides a semiconductor device capable of suppressing temperature rise by devising the layout of the channel formation region.
In addition, the present disclosure provides a semiconductor device capable of increasing dynamic clamping resistance while suppressing an increase in on-resistance.

A semiconductor device according to the present disclosure includes a substrate, a plurality of trenches formed in the substrate, and a plurality of functional element formation regions including channel formation regions arranged along each of the trenches and serving as current paths. The plurality of functional element forming regions include a first functional element forming region in which the channel forming region occupies a relatively small area per unit area, and a first functional element forming region in which the channel forming region occupies a relatively large area per unit area. and a two-function element formation region. In this configuration, the first functional element formation region is provided in a region where heat generation should be suppressed.

In the semiconductor device of the present disclosure, the area of the channel forming region per unit area of the first functional element forming region is relatively smaller than that of the second functional element forming region. In other words, the first functional element formation region is configured to have a relatively small amount of heat generation and a relatively high dynamic clamp tolerance. Therefore, by providing the first functional element forming region in a region where heat generation should be suppressed, it is possible to satisfactorily suppress the temperature rise and increase the dynamic clamp resistance.

On the other hand, in the second functional element forming region, the area of the channel forming region per unit area is relatively larger than that of the first functional element forming region. Therefore, in the second functional element formation region, a relatively large area of the channel formation region can ensure a relatively large area current path. can be suppressed. This can suppress an increase in on-resistance.

As described above, according to the semiconductor device of the present disclosure, temperature rise can be suppressed by devising the layout of the channel formation region. Further, according to the semiconductor device of the present disclosure, it is possible to increase the dynamic clamp resistance while suppressing an increase in on-resistance.

1 is a perspective view of a semiconductor package according to a first embodiment of the present disclosure; FIG. 2 is a plan view (a sealing resin is omitted) of the semiconductor package shown in FIG. 1. FIG. 3 is a bottom view of the semiconductor package shown in FIG. 1. FIG. FIG. 4 is a cross-sectional view taken along line IV--IV in FIG. FIG. 5 is a cross-sectional view (the sealing resin is omitted) taken along line VV in FIG. 6 is a fragmentary plan view of the semiconductor device in the semiconductor package shown in FIG. 1. FIG. FIG. 7 is a partial cross-sectional view along line VII-VII of FIG. 8 is a front view of a radiator of the semiconductor package shown in FIG. 1. FIG. FIG. 9 is a perspective view of a semiconductor package according to a second embodiment of the present disclosure; FIG. 10 is a plan view of the semiconductor package shown in FIG. 9 (the sealing resin is omitted). 11 is a bottom view of the semiconductor package shown in FIG. 9. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 9. FIG. FIG. 13 is a cross-sectional view taken along line XIII--XIII in FIG. 14 is a fragmentary plan view of the semiconductor device in the semiconductor package shown in FIG. 9. FIG. FIG. 15A is a schematic configuration diagram showing a semiconductor device according to an embodiment of the present disclosure, and FIG. 15B is an enlarged plan view showing active regions. FIG. 16 is an electrical circuit diagram showing an example of the internal electrical structure of the semiconductor device. FIG. 17 is an enlarged plan view showing the active area, with structures on the substrate removed. 18A is an enlarged plan view showing the first functional element formation region shown in FIG. 17. FIG. 18B is an enlarged plan view showing the second functional element formation region shown in FIG. 17. FIG. 18C is an enlarged plan view showing the third functional element forming region shown in FIG. 17. FIG. FIG. 19A is a longitudinal sectional view along line XIXA--XIXA shown in FIG. 18A. FIG. 19B is a vertical cross-sectional view along line XIXB-XIXB shown in FIG. 18A. FIG. 20 is a graph showing on-resistance-dynamic clamping capability characteristics. FIG. 21 is a plan view for explaining the arrangement relationship between bonding wires and functional element forming regions. FIG. 22 is a plan view for explaining another arrangement relationship between bonding wires and functional element forming regions. FIG. 23A is a vertical cross-sectional view showing one step of a method of manufacturing a power MISFET formed in the active region. FIG. 23B is a longitudinal sectional view showing the next step of FIG. 23A. FIG. 23C is a longitudinal sectional view showing the next step of FIG. 23B. FIG. 23D is a longitudinal sectional view showing the next step of FIG. 23C. FIG. 23E is a longitudinal sectional view showing the next step of FIG. 23D. FIG. 23F is a longitudinal sectional view showing the next step of FIG. 23E. FIG. 23G is a longitudinal sectional view showing the next step of FIG. 23F. FIG. 24 is a plan view showing a semiconductor package in which the semiconductor device is incorporated, a part of which is cut away.

Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
<First embodiment>
A semiconductor package A10 according to the first embodiment of the present disclosure will be described based on FIGS. 1 to 8. FIG. The semiconductor package A10 includes a semiconductor device 11, a bonding layer 12, a first lead 21, a second lead 22, a third lead 23, a first bonding wire 31, a second bonding wire 32, a plurality of radiators 4, and an exterior plating layer 51. , an interior plating layer 52 and a sealing resin 6 . In the following description, the semiconductor package A10 may be referred to as the semiconductor device A10, and the semiconductor device 11 may be referred to as the semiconductor element 11.

FIG. 1 is a perspective view of the semiconductor package A10. FIG. 2 is a plan view of the semiconductor package A10. FIG. 3 is a bottom view of the semiconductor package A10. FIG. 4 is a cross-sectional view taken along line IV--IV in FIG. 5 is a cross-sectional view taken along line VV of FIG. 2. FIG. FIG. 6 is a fragmentary plan view of the semiconductor device 11 of the semiconductor package A10. FIG. 7 is a partial cross-sectional view along line VII-VII of FIG. FIG. 8 is a front view of the radiator 4 of the semiconductor package A10. 2 and 5 omit the sealing resin 6 for convenience of understanding. The sealing resin 6 omitted in FIGS. 2 and 5 is indicated by an imaginary line (chain double-dashed line).

The semiconductor package A10 shown in these figures is of a type that is surface-mounted, for example, on a circuit board of automotive electrical equipment. Here, for convenience of explanation, the downward direction in the plan view perpendicular to the thickness direction Z of the semiconductor device 11 (hereinafter simply referred to as the "thickness direction Z") is defined as the first direction X1, and the first direction X1 A second direction X2 is the upward direction in the plan view, which is the opposite direction, and a third direction Y is the left-right direction in the plan view, which is perpendicular to the thickness direction Z, the first direction X1, and the second direction X2. and defined respectively. The portion of the semiconductor package A10 according to the present embodiment covered with the sealing resin 6 has a rectangular shape in plan view (hereinafter simply referred to as “plan view”) in the thickness direction Z. As shown in FIG.

The semiconductor device 11 is an element serving as the core of the functions of the semiconductor package A10. The semiconductor device 11 according to this embodiment is a power MOSFET or IGBT. The semiconductor device 11 has an element main surface 111 and an element back surface 112 . As shown in FIGS. 4 and 5, the element main surface 111 and the element back surface 112 face opposite sides in the thickness direction Z. As shown in FIGS.
Element main surface 111 is the upper surface of semiconductor device 11 shown in FIGS. As shown in FIGS. 2 and 6, the element main surface 111 is formed with a second electrode 111a and a third electrode 111b. When the semiconductor device 11 is a power MOSFET, the second electrode 111a is a source electrode and the third electrode 111b is a gate electrode. Moreover, when the semiconductor device 11 is an IGBT, the second electrode 111a is an emitter electrode and the third electrode 111b is a gate electrode. The area of the second electrode 111a is larger than the area of the third electrode 111b. In this embodiment, both the second electrode 111a and the third electrode 111b are composed of a Cu layer and an Al layer that are laminated together. A first bonding wire 31 is connected to the second electrode 111a, and a second bonding wire 32 is connected to the third electrode 111b. Further, a plurality of radiators 4 are formed on the second electrode 111a.

As shown in FIGS. 6 and 7, a passivation film 111c having electrical insulation properties and surrounding the second electrode 111a and the third electrode 111b is formed on the main surface 111 of the element according to the present embodiment. there is The passivation film 111c is, for example, a stack of a Si ₃ N ₄ layer formed by plasma CVD and a polyimide layer formed by coating.

Element back surface 112 is the bottom surface of semiconductor device 11 shown in FIGS. A first electrode 112a is formed over the entire back surface 112 of the element. When the semiconductor device 11 is a power MOSFET, the first electrode 112a is the drain electrode. Moreover, when the semiconductor device 11 is an IGBT, the first electrode 112a is a collector electrode.
As shown in FIGS. 4 and 5, the bonding layer 12 is a member that has conductivity and is interposed between the semiconductor device 11 and a first pad portion 211 of a first lead 21, which will be described later. The bonding layer 12 allows the semiconductor device 11 to be mounted on the first pad portion 211 by die bonding, and ensures electrical connection between the first electrode 112 a and the first lead 21 . The bonding layer 12 is made of, for example, a synthetic resin (so-called Ag paste) whose main component is an epoxy resin containing Ag.

The first lead 21, the second lead 22, and the third lead 23 are members that have conductivity and form a conductive path between the semiconductor package A10 and the circuit board by being joined to the circuit board. The first lead 21, the second lead 22, and the third lead 23 are members derived from the same lead frame, and the lead frame according to the present embodiment is made of an alloy containing Cu as a main component.

First lead 21 includes first pad portion 211 , first terminal portion 212 and intermediate connecting portion 213 . The first pad portion 211 is a portion on which the semiconductor device 11 is mounted and which is electrically connected to the first electrode 112a formed on the element back surface 112, as shown in FIGS. The first pad portion 211 has a pad main surface 211a and a pad rear surface 211b. The pad main surface 211a is the top surface of the first pad portion 211 shown in FIGS. The pad main surface 211a is a surface on which the semiconductor device 11 is mounted. As shown in FIG. 2, an internal plating layer 52 having an area larger than that of the semiconductor device 11 is formed on the pad main surface 211a. Therefore, as shown in FIGS. 4 and 5, the bonding layer 12 is in contact with both the first electrode 112a and the internal plating layer 52. As shown in FIGS. Moreover, the pad back surface 211b is the lower surface of the first pad portion 211 shown in FIGS. As shown in FIG. 3, the pad back surface 211b is exposed from the sealing resin 6 over the entire surface. As shown in FIGS. 5 and 6, the pad rear surface 211b is covered with the exterior plating layer 51. As shown in FIGS. The pad main surface 211a and the pad back surface 211b face opposite sides in the thickness direction Z and are both flat. Further, as shown in FIGS. 2 to 4, in the first pad portion 211, a pad through hole 211c extending from the pad main surface 211a to the pad rear surface 211b is formed apart from the semiconductor device 11. As shown in FIGS. The pad through hole 211c has a circular shape.

The first terminal portion 212 is a portion extending along the first direction X1 and partly exposed from the sealing resin 6, as shown in FIGS. As shown in FIG. 4 , the portion of the first terminal portion 212 exposed from the sealing resin 6 is covered with the exterior plating layer 51 . The first terminal portion 212 is electrically connected to the first electrode 112 a through the intermediate connecting portion 213 , the first pad portion 211 and the bonding layer 12 . Therefore, when the semiconductor device 11 is a power MOSFET, the first terminal portion 212 is the drain terminal of the semiconductor package A10. Moreover, when the semiconductor device 11 is an IGBT, the first terminal portion 212 is a collector terminal of the semiconductor package A10.

The intermediate connecting portion 213 is a portion that connects the first pad portion 211 and the first terminal portion 212, as shown in FIGS. As shown in FIG. 4, the positions of the first pad portion 211 and the first terminal portion 212 are different in the thickness direction Z, and the first pad portion 211 is positioned below the first terminal portion 212 in FIG. ing. Therefore, intermediate connecting portion 213 is inclined with respect to first pad portion 211 and first terminal portion 212 . The intermediate connecting portion 213 is entirely covered with the sealing resin 6 .

The second lead 22 is a member electrically connected to the second electrode 111a formed on the element main surface 111 and extending along the first direction X1, as shown in FIGS. The second lead 22 is spaced apart from the first lead 21 and positioned on one side of the first terminal portion 212 in the third direction Y. As shown in FIG. The second lead 22 includes a second pad portion 221 and a second terminal portion 222 . The second pad portion 221 is longer than the second terminal portion 222 in the third direction Y and is entirely covered with the sealing resin 6, as shown in FIG. An internal plating layer 52 is formed on the upper surface of the second pad portion 221 shown in FIG. 5, and the first bonding wire 31 is connected to the portion where the internal plating layer 52 is formed.

The second terminal portion 222 is a portion extending along the first direction X1 and partly exposed from the sealing resin 6, as shown in FIGS. The second terminal portion 222 is connected to the second pad portion 221 . A portion of the second terminal portion 222 exposed from the sealing resin 6 is covered with the exterior plating layer 51 in the same manner as the first terminal portion 212 shown in FIG. The second terminal portion 222 is electrically connected to the second electrode 111 a through the second pad portion 221 and the first bonding wire 31 . Therefore, when the semiconductor device 11 is a power MOSFET, the second terminal portion 222 is the source terminal of the semiconductor package A10. Moreover, when the semiconductor device 11 is an IGBT, the second terminal portion 222 is the emitter terminal of the semiconductor package A10.

The third lead 23 is, as shown in FIGS. 1 to 3, a member electrically connected to the third electrode 111b formed on the element main surface 111 and extending along the first direction X1. The third lead 23 is spaced apart from the first lead 21 and positioned on the opposite side of the first terminal portion 212 from the second lead 22 in the third direction Y. As shown in FIG. Third lead 23 includes third pad portion 231 and third terminal portion 232 . The third pad portion 231 is longer than the third terminal portion 232 in the third direction Y as shown in FIG. 2 and is entirely covered with the sealing resin 6 . An internal plating layer 52 is formed on the upper surface of the third pad portion 231 shown in FIG. 5, and the second bonding wire 32 is connected to the portion where the internal plating layer 52 is formed.

The third terminal portion 232 is a portion extending along the first direction X1 and partly exposed from the sealing resin 6, as shown in FIGS. The third terminal portion 232 is connected to the third pad portion 231 . A portion of the third terminal portion 232 exposed from the sealing resin 6 is covered with the exterior plating layer 51 similarly to the first terminal portion 212 shown in FIG. The third terminal portion 232 is electrically connected through the third pad portion 231 and the second bonding wire 32 to the third electrode 111b. Therefore, when the semiconductor device 11 is a power MOSFET or IGBT, the third terminal portion 232 is the gate terminal of the semiconductor package A10.

As shown in FIGS. 1 to 3, the first terminal portion 212, the second lead 22 and the third lead 23 are all arranged along the third direction Y, and in the third direction Y the first terminal portion 212 is , between the second lead 22 and the third lead 23 . Moreover, as shown in FIGS. 1 and 4, the positions of the first terminal portion 212, the second lead 22 and the third lead 23 in the thickness direction Z are all the same.

The first bonding wire 31 is a member that has conductivity and connects the second electrode 111a and the second lead 22, as shown in FIGS. The first bonding wires 31 according to this embodiment are plural, and the second electrode 111 a and the second lead 22 are connected by the plural first bonding wires 31 . In the present embodiment, the number of arranged first bonding wires 31 that connect the second electrode 111a and the second lead 22 is three. is not limited to this. As shown in FIGS. 6 and 7, a bonding portion 311 having a circular planar shape is formed at the tip of the first bonding wire 31, and the bonding portion 311 is in contact with the first electrode 112a. The bonding portion 311 is a so-called ball bonding portion formed by general wire bonding. The first bonding wire 31 according to this embodiment is made of Cu and has a wire diameter of 30 to 70 μm.

The second bonding wire 32 is a member that has conductivity and connects the third electrode 111b and the third lead 23, as shown in FIGS. The shape and material of the second bonding wire 32 are not particularly limited, and may be the same as the shape and material of the first bonding wire 31, for example.
The plurality of heat radiators 4 are members formed on the second electrode 111a with a space from the bonding portion 311, as shown in FIGS. Each shape of the plurality of radiators 4 is the same as the shape of the bonding portion 311 . The radiator 4 is made of the same metal as the first bonding wire 31, and in this embodiment, the radiator 4 is made of Cu. As shown in FIG. 8, the radiator 4 according to this embodiment has a diameter d of 60 to 100 μm and a thickness t (length in the thickness direction Z) of 10 to 30 μm. In addition, in the present embodiment, the bonding portion 311 and the plurality of radiators 4 are arranged in a grid pattern in the second electrode 111 a , and the radiator 4 is arranged adjacent to the bonding portion 311 .

As shown in FIGS. 4 and 5, the exterior plating layer 51 is formed to cover the pad rear surface 211b of the first lead 21 exposed from the sealing resin 6 and the first terminal portion 212. As shown in FIG. In addition, like the first terminal portion 212 of the first lead 21 , the exterior plating layer 51 has the second terminal portion 222 of the second lead 22 and the third terminal portion 232 of the third lead 23 exposed from the sealing resin 6 . formed over the The exterior plating layer 51 according to this embodiment is made of an alloy containing Sn as a main component. Specifically, the alloy is lead-free solder such as Sn--Sb alloy or Sn--Ag alloy. The exterior plating layer 51 is formed by electrolytic plating.

The internal plating layer 52 is part of the pad main surface 211a of the first lead 21 covered with the sealing resin 6 and part of the second lead 22, as shown in FIGS. It is formed on the upper surface of the second pad portion 221 shown in FIG. 5 and the upper surface of the third pad portion 231 shown in FIG. The interior plating layer 52 according to this embodiment is made of Ag. The internal plating layer 52 is formed by electrolytic plating.

As shown in FIGS. 1 to 3, the encapsulating resin 6 is applied to parts of the first lead 21, the second lead 22 and the third lead 23, the semiconductor device 11, the first bonding wire 31 and the second bonding. It is a member that covers the wires 32 and the plurality of radiators 4 . The sealing resin 6 is made of a thermosetting synthetic resin having electrical insulation. The synthetic resin according to this embodiment is a black epoxy resin. The sealing resin 6 is formed, for example, by transfer molding using a mold. The sealing resin 6 has a resin main surface 61 , a resin back surface 62 , a pair of resin first side surfaces 631 and a pair of resin second side surfaces 632 .

The resin main surface 61 is the upper surface of the sealing resin 6 shown in FIG. The resin back surface 62 is the bottom surface of the sealing resin 6 shown in FIG. The resin main surface 61 and the resin back surface 62 face opposite sides in the thickness direction Z. As shown in FIG. As shown in FIGS. 3 to 5, in this embodiment, the pad back surface 211b, which is part of the first pad section 211, is exposed from the resin back surface 62. As shown in FIGS.
As shown in FIGS. 1 and 4, the pair of resin first side surfaces 631 are surfaces spaced apart in the first direction X1 and the second direction X2. One resin first side surface 631 faces the first direction X1, and the other resin first side surface 631 faces the second direction X2. The upper end of the resin first side surface 631 shown in FIG. 4 is connected to the resin main surface 61 , and the lower end of the resin first side surface 631 shown in FIG. 4 is connected to the resin back surface 62 . In this embodiment, a part of each of the first terminal portion 212, the second terminal portion 222, and the third terminal portion 232 is exposed from the resin first side surface 631 facing the first direction X1.

The pair of resin second side surfaces 632 are surfaces that are spaced apart in the third direction Y as shown in FIGS. 1 and 5 . The pair of resin second side surfaces 632 face opposite sides in the third direction Y. As shown in FIG. The upper end of the resin second side surface 632 shown in FIG. 5 is connected to the resin main surface 61 , and the lower end of the resin second side surface 632 shown in FIG. 5 is connected to the resin back surface 62 . In this embodiment, none of the first lead 21 , the second lead 22 and the third lead 23 are exposed from the pair of resin second side surfaces 632 .

As shown in FIGS. 1, 3 and 4, the sealing resin 6 is formed with a body insertion hole 64 extending from the resin main surface 61 to the pad rear surface 211b of the first pad portion 211 in the thickness direction Z. ing. A hole wall of the body insertion hole 64 is formed of the sealing resin 6 . As shown in FIGS. 2 and 3, in this embodiment, the center of the body insertion hole 64 is the same as the center of the pad through hole 211c. Also, the diameter of the body insertion hole 64 is smaller than the diameter of the pad through hole 211c.

Next, functions and effects of the semiconductor package A10 will be described.
The semiconductor package A10 mounts the semiconductor device 11 having the first electrode 112a formed on the element back surface 112 and the second electrode 111a formed on the element main surface 111, and the semiconductor device 11, and the first electrode 112a is electrically connected. a first lead 21 including a first pad portion 211 that connects to the second electrode 111a; a second lead 22 electrically connected to the second electrode 111a; A bonding portion 311 in contact with the second electrode 111 a is formed at the tip of the first bonding wire 31 , and a plurality of radiators 4 are formed on the second electrode 111 a apart from the bonding portion 311 . For example, when the semiconductor device 11 is a power MOSFET, the first electrode 112a is the drain electrode and the second electrode 111a is the source electrode.

In this case, when the semiconductor device 11 is switched, a reverse voltage is applied between the first electrode 112a and the second electrode 111a due to the inductance of the inductive load, and heat is generated in the second electrode 111a. At this time, the heat generated in the second electrode 111a is radiated to the sealing resin 6 covering the periphery of the semiconductor device 11 by the plurality of radiators 4, so that the temperature rise of the semiconductor device 11 is suppressed. Therefore, by forming a plurality of radiators 4, the occurrence of avalanche breakdown can be avoided without changing the specifications of the trench gate in the semiconductor device 11. As a result, the avalanche withstand capability of the semiconductor device 11 is improved. improves. Therefore, according to the semiconductor package A10, it is possible to prevent the circuit design of the semiconductor device 11 from becoming complicated, suppress an increase in the on-resistance, and improve the avalanche resistance.

The shape of the radiator 4 is the same as the shape of the bonding portion 311, and the bonding portion 311 and the radiator 4 are both made of the same metal. That is, the radiator 4 is obtained by forming only the bonding portion 311 in a general wire bonding process. Therefore, the radiator 4 can be easily formed by conventional manufacturing equipment.
In the second electrode 111a, the bonding portion 311 and the plurality of radiators 4 are arranged in a grid pattern, so that the heat generated in the second electrode 111a can be dissipated evenly and efficiently.

By providing a plurality of first bonding wires 31 connecting the second electrode 111 a and the second lead 22 , the heat generated from the second electrode 111 a is dissipated from each of the first bonding wires 31 in addition to the heat radiators 4 . heat is also radiated, and the avalanche resistance of the semiconductor device 11 can be further improved. In addition, since the resistance between the second electrode 111a and the second lead 22 is set low, an increase in the on-resistance of the semiconductor device 11 can be further suppressed.

A main body insertion hole 64 is formed from the resin main surface 61 to the first pad portion 211 in the thickness direction Z, and the hole wall of the main body insertion hole 64 is formed of the sealing resin 6 . Also, the sealing resin 6 is a synthetic resin having electrical insulation. By adopting such a configuration, a heat dissipating member such as a heat spreader can be attached to the pad back surface 211 b of the first pad portion 211 by inserting a conductive fastening member such as a screw through the main body insertion hole 64 . Therefore, the heat constantly generated from the first electrode 112a by the switching of the semiconductor device 11 can be dissipated more efficiently.

The semiconductor package A10 includes an exterior plating layer 51 that covers portions of the first terminal portion 212, the second lead 22, and the third lead 23 exposed from the sealing resin 6, respectively. When the semiconductor package A10 is surface-mounted on a circuit board by soldering, the exterior plating layer 51 ensures good solder adhesion to the respective portions of the first terminal portion 212, the second lead 22 and the third lead 23. In addition, it is possible to prevent erosion of the portion due to solder joint.

The semiconductor package A10 also includes internal plating layers 52 formed on respective portions of the first pad portion 211 , the second lead 22 and the third lead 23 covered with the sealing resin 6 . When mounting the semiconductor device 11 on the first pad portion 211 , when connecting the first bonding wire 31 to the second pad portion 221 of the second lead 22 , and when performing the second bonding of the third lead 23 to the third pad portion 231 . The internal plating layer 52 can protect the first pad portion 211 , the second pad portion 221 , and the third pad portion 231 from thermal shock during connection of the wire 32 .
<Second embodiment>
A semiconductor package A20 according to the second embodiment of the present disclosure will be described with reference to FIGS. 9 to 14. FIG. In these figures, elements that are the same as or similar to those of the semiconductor package A10 described above are denoted by the same reference numerals, and overlapping descriptions are omitted.

FIG. 9 is a perspective view of the semiconductor package A20. FIG. 10 is a plan view of the semiconductor package A20. FIG. 11 is a bottom view of the semiconductor package A20. 12 is a cross-sectional view along line XII-XII (one-dot chain line) in FIG. 13 is a cross-sectional view taken along line XIII--XIII of FIG. 10. FIG. FIG. 14 is a fragmentary plan view of the semiconductor device 11 of the semiconductor package A20. 10 omits the sealing resin 6 for convenience of understanding. The sealing resin 6 omitted in FIG. 10 is indicated by an imaginary line (chain double-dashed line).

In the semiconductor package A20 according to the present embodiment, the configuration of the first lead 21, the second lead 22, the third lead 23, and the sealing resin 6, and the layout of the first bonding wires 31 and the plurality of radiators 4 are It is different from the semiconductor package A10 described above.
First lead 21 includes first pad portion 211 and first terminal portion 212 . As shown in FIGS. 12 and 13, the first pad portion 211 has a pad main surface 211a and a pad rear surface 211b similar to those of the semiconductor package A10. However, as shown in FIGS. 10 and 11, the pad through holes 211c are not formed in the first pad portion 211 according to the present embodiment unlike the semiconductor package A10. The first terminal portion 212 is a portion extending along the first direction X1 and partly exposed from the sealing resin 6, as shown in FIGS. In the present embodiment, the first terminal portions 212 are plural, specifically four first terminal portions 212 . The length of the first terminal portion 212 according to this embodiment is shorter than the length of the first terminal portion 212 of the semiconductor package A10. The lower surface of the first terminal portion 212 shown in FIG. 12 is flush with the pad rear surface 211b. Moreover, as shown in FIGS. 12 and 13 , both the pad rear surface 211 b exposed from the sealing resin 6 and the respective portions of the plurality of first terminal portions 212 are covered with the exterior plating layer 51 .

The second lead 22 is a member extending along the second direction X2, as shown in FIGS. In the present embodiment, the second leads 22 are plural, specifically three second leads 22 . Each second lead 22 is electrically connected to the second electrode 111a formed on the main surface 111 of the element through the first bonding wire 31. As shown in FIG. The plurality of second leads 22 are arranged along the third direction Y so as to be spaced apart from each other. The length of the second lead 22 according to this embodiment is shorter than the length of the second terminal portion 222 of the semiconductor package A10. The lower surface of the second lead 22 shown in FIG. 12 is flush with the pad rear surface 211b. Further, as shown in FIG. 12 , each portion of the plurality of second leads 22 exposed from the sealing resin 6 is covered with the exterior plating layer 51 . Furthermore, an internal plating layer 52 is formed on the upper surface of the second lead 22 shown in FIG. 12 covered with the sealing resin 6 .

The third lead 23 is a member extending along the second direction X2 like the second lead 22, as shown in FIGS. The third lead 23 is arranged along the third direction Y together with the plurality of second leads 22 . The shape and size of the third lead 23 according to this embodiment are the same as those of the second lead 22 . As with the second lead 22 shown in FIG. 12, the portion of the third lead 23 exposed from the sealing resin 6 is covered with the exterior plating layer 51, and of the portion covered with the sealing resin 6, the second bonding is performed. An internal plating layer 52 is formed on the portion to which the wire 32 is connected.

As shown in FIGS. 10 and 14, the first bonding wires 31 are plural, and the second electrode 111a and the second lead 22 are connected by the plural first bonding wires 31. As shown in FIG. In this embodiment, the number of first bonding wires 31 that connect the second electrode 111a and one second lead 22 is three. 2 leads 22 are connected to each other, however, since it is merely an example like the semiconductor package A10, the actual number of the first bonding wires 31 arranged is not limited to this.

A plurality of radiators 4 are formed on the second electrode 111a while being spaced from the bonding portion 311, similarly to the semiconductor package A10. As shown in FIG. 14 , the bonding portion 311 and the plurality of heat radiators 4 are arranged in a grid pattern in the second electrode 111 a , and the heat radiators 4 are arranged adjacent to the bonding portions 311 .
The sealing resin 6 has a resin main surface 61, a resin back surface 62, a pair of resin first side surfaces 631, and a pair of resin second side surfaces 632, similarly to the semiconductor package A10. However, unlike the semiconductor package A10, the body insertion hole 64 is not formed in the sealing resin 6 according to this embodiment, as shown in FIGS. As shown in FIG. 11, in this embodiment, the pad back surface 211b and the first terminal portion 212, the second lead 22, and the third lead 23 are partially exposed from the resin back surface 62. As shown in FIG. 9, of the pair of resin first side surfaces 631, a part of the first terminal portion 212 is exposed from the resin first side surface 631 facing the first direction X1, and the resin side surface facing the second direction X2 is exposed. Part of each of the second lead 22 and the third lead 23 is exposed from the first side surface 631 .

Next, functions and effects of the semiconductor package A20 will be described.
As with the semiconductor package A10, the semiconductor package A20 is mounted with the semiconductor device 11 having the first electrode 112a formed on the element back surface 112 and the second electrode 111a formed on the element main surface 111, and the semiconductor device 11, A first lead 21 including a first pad portion 211 electrically connected to the first electrode 112a, a second lead 22 electrically connected to the second electrode 111a, and a first bonding connecting the second electrode 111a and the second lead 22. A wire 31 is provided. A bonding portion 311 in contact with the second electrode 111 a is formed at the tip of the first bonding wire 31 , and a plurality of radiators 4 are formed on the second electrode 111 a apart from the bonding portion 311 . Therefore, even with the semiconductor package A20, it is possible to prevent the circuit design of the semiconductor device 11 from becoming complicated, suppress an increase in the on-resistance, and improve the avalanche resistance.

Next, an example of a configuration in which the semiconductor device 11 described above is a power MISFET will be described.
<Schematic Configuration of Semiconductor Device>
FIG. 15A is a schematic configuration diagram showing a semiconductor device 1 according to an embodiment of the present disclosure. 15B is an enlarged plan view showing active region 9. FIG.

Referring to FIG. 15A, semiconductor device 1 corresponding to semiconductor device 11 described above includes substrate 2 having a rectangular shape in plan view. A semiconductor device 1 includes a switching circuit 3 having a plurality of power MISFETs (Metal Insulator Semiconductor Field Effect Transistors) as an example of a functional element of the present disclosure built into a surface layer of a substrate 2 .
The semiconductor device 1 includes a current sensor circuit 48, a temperature sensor circuit 5, an overcurrent protection (OCD: Over Charge Current Detection) circuit 49, an overheat protection (TSD: Thermal Shut Down) circuit 7, and a low voltage malfunction prevention ( UVLO (Under Voltage Lock Out) circuit 8 is further included. The current sensor circuit 48 , the temperature sensor circuit 5 , the overcurrent protection circuit 49 , the overheat protection circuit 7 , and the low voltage malfunction prevention circuit 8 are all built into the surface layer of the substrate 2 . That is, in the present embodiment, the semiconductor device 1 has the switching circuit 3 (power MISFET), the current sensor circuit 48, the temperature sensor circuit 5, the overcurrent protection circuit 49, the overheat protection circuit 7, and the low voltage malfunction prevention circuit 8 in common. It is an IPS (Intelligent Power Switch) built into the surface layer of the substrate 2 .

Referring to FIG. 15B, switching circuit 3 (power MISFET) is formed within active region 9 set in substrate 2 . In this embodiment, the active region 9 is formed in a rectangular shape in plan view and is covered with a source metal 10 . The source metal 10 may correspond to the aforementioned second electrode 111a. In FIG. 15B, the source metal 10 is indicated by thin dotted hatching. A plurality of bonding wires 53 are selectively connected to the source metal 10 as an example of the conductor wire of the present disclosure. A power MISFET formed in the active region 9 is driven based on power supplied from this bonding wire 53 .
<Electrical Structure of Semiconductor Device>
FIG. 16 is an electrical circuit diagram showing an example of the internal electrical structure of the semiconductor device 1. As shown in FIG.

As shown in FIG. 16, the semiconductor device 1 has a pair of input terminal 101 and input side ground terminal 102 and a pair of output terminal 103 and output side ground terminal 104 . FIG. 16 shows an example in which a series circuit 107 including a power source 105 and an inductive load 106 is externally connected to the output terminal 103 and output side ground terminal 104 . 16 shows an example in which the inductive load 106 is a relay including a switch Sw and a coil L. FIG.

The aforementioned switching circuit 3 is connected between the output terminal 103 and the output side ground terminal 104 . The switching circuit 3 includes the aforementioned power MISFET. The power MISFET has a gate terminal G, a drain terminal D and a source terminal S. The switching circuit 3 is provided so that the drain terminal D of the power MISFET is connected to the output terminal 103 and the source terminal S of the power MISFET is connected to the output side ground terminal 104 . Although the switching circuit 3 includes a plurality of power MISFETs, only one power MISFET is shown in FIG. 16 for convenience of explanation.

An input wiring 108 is connected between the input terminal 101 and the gate terminal G of the power MISFET. A ground wiring 109 is connected between the input side ground terminal 102 and the output side ground terminal 104 . Between the input wiring 108 and the ground wiring 109 are, in order from the input terminal 101 side, a diode Di ₁ , a first resistor R ₁ , the overcurrent protection circuit 49 described above, the overheat protection circuit 7 described above, and the low voltage malfunction described above. A prevention circuit 8 and a second resistor _R2 are connected in parallel in a ladder-like fashion. A _third resistor R3 is connected in series with the input wiring 108 between the first resistor _R1 and the overcurrent protection circuit 49 . A fourth resistor _R4 is connected in series to the input wiring 108 between the low voltage malfunction prevention circuit 8 and the _second resistor R2.

The aforementioned current sensor circuit 48 is connected to an overcurrent protection circuit 49 . Current sensor circuit 48 detects current flowing through input wiring 108, for example. A current value detected by the current sensor circuit 48 is applied to the overcurrent protection circuit 49 . Overcurrent protection circuit 49 is driven based on the current value provided from current sensor circuit 48 . For example, when a current (overcurrent) exceeding a predetermined value flows through the input wiring 108 due to a short circuit or static electricity, the overcurrent protection circuit 49 causes the overcurrent to flow from the input wiring 108 side to the ground wiring 109 side, protect the circuit.

The aforementioned temperature sensor circuit 5 is connected to an overheat protection circuit 7 . A temperature sensor circuit 5 detects the temperature of the substrate 2 . The temperature detected by temperature sensor circuit 5 is applied to overheat protection circuit 7 . Overheat protection circuit 7 is driven based on the temperature given from temperature sensor circuit 5 . For example, when the temperature of the substrate 2 reaches or exceeds a predetermined value, the overheat protection circuit 7 prohibits energization of the input wiring 108 to suppress the temperature rise of the substrate 2 .

The low-voltage malfunction prevention circuit 8 prohibits the switching circuit 3 from operating when the potential difference between the input wiring 108 and the ground wiring 109 is less than a predetermined value, and when the potential difference exceeds the predetermined value, the switching circuit 3 is configured to allow it to operate.
_A clamp diode Di2 is connected between the gate terminal G and the drain terminal D of the power MISFET. The clamp diode Di2 is formed by _two diodes connected in reverse bias. The two diodes may include Zener diodes. _The clamp diode Di2 has _a breakdown voltage V2 _{lower than} the breakdown voltage V1 between the drain terminal D and the source terminal S in the power MISFET ₍ breakdown voltage V1>breakdown voltage V2). Therefore, the clamp diode _{Di2 breaks} down before the power MISFET when the breakdown voltage V1 is applied between the drain terminal D and the source terminal S.

When the inductive load 106 is turned off and a back electromotive voltage V _L (back electromotive voltage V _L > breakdown voltage V ₁ ) that is higher than the breakdown voltage V ₁ between the drain terminal D and the source terminal S is generated in the coil L, the clamp Diode Di2 _breaks down. When the clamp diode Di2 breaks down, a current flows through the _second resistor _R2 and a voltage (gate voltage) is generated between the gate terminal G and the source terminal S. Since the power MISFET is turned on by this gate voltage, a current generated due to the back electromotive voltage _VL flows between the drain terminal D and the source terminal S.

Thus, the load on the power MISFET is reduced by the clamp diode _Di2 and the energy stored in the inductive load 106 is absorbed by the power MISFET. How much energy stored in the inductive load 106 is absorbed is represented by the dynamic clamping capability _Eac , which is one of the characteristics of the power MISFET. The greater the value of dynamic clamping capability _Eac , the more energy stored in inductive load 106 is absorbed.

The current sensor circuit 48, the temperature sensor circuit 5, the overcurrent protection circuit 49, the overheat protection circuit 7, the low voltage malfunction prevention circuit ₈ , the clamp diode Di2, various resistors _R1 to _R4 , etc. are part of the IPS. This is an example of a circuit to be configured, and is not necessarily a configuration required for an IPS. Moreover, the semiconductor device 1 is not limited to the IPS. Therefore, the semiconductor device 1 may be a so-called discrete component including only the switching circuit 3 (power MISFET). In this case, the current sensor circuit 48, the temperature sensor circuit 5, the overcurrent protection circuit 49, the overheat protection circuit 7, the low voltage malfunction prevention circuit ₈ , the clamp diode Di2, various resistors _R1 to _R4 , etc. It may be configured by another component that is externally connected to it.
<Planar structure of active region>
FIG. 17 is an enlarged plan view of active area 9 of FIG. 15B, with structures on substrate 2 removed.

Referring to FIG. 17, a plurality of trench gate structures 54 are linearly formed along the same direction on the surface of substrate 2 in active region 9 . A functional element forming region 14 including a channel forming region 13 serving as a current path is formed along each trench gate structure 54 between adjacent trench gate structures 54 . A plurality of functional element forming regions 14 are linearly arranged along each trench gate structure 54 . Therefore, the trench gate structures 54 and the functional element forming regions 14 are alternately arranged when viewed in the lateral direction crossing the trench gate structures 54 .

In FIG. 17, for clarity, the trench gate structure 54 is indicated by thick cross hatching, and the channel forming region 13 is indicated by thin dot-like hatching. A region (not hatched) outside the channel forming region 13 between the trench gate structures 54 is the surface of the substrate 2 .
The feature of the semiconductor device 1 according to the present embodiment is that the plurality of functional element forming regions 14 are divided into the first functional element forming region 15 in which the area of the channel forming region 13 per unit area is relatively small, and the The second functional element forming region 16 occupied by the channel forming region 13 has a relatively large area, and the first functional element forming region 15 is provided in a region where heat generation should be suppressed. In this embodiment, the area of the channel forming region 13 per unit area between the first functional element forming region 15 and the second functional element forming region 16 is larger than that of the first functional element forming region 15. An example is shown in which a third functional element forming region 17 smaller than the second functional element forming region 16 is further provided.

The area of the channel forming region 13 per unit area is the area of the channel forming region 13 that occupies a predetermined region between the trench gate structures 54 . The predetermined region is a region having a predetermined area obtained by multiplying the width between the trench gate structures 54 by an arbitrary length along the longitudinal direction of the trench gate structures 54 .
In the first functional element forming region 15, the area of the channel forming region 13 per unit area is smaller than that of the second functional element forming region 16 and the third functional element forming region 17, so the amount of heat generated is also relatively high. small. On the other hand, the first functional element formation region 15 has a larger _on -resistance RON than the second functional element formation region 16 and the third functional element formation region 17 due to the relatively small area of the channel formation region 13 . there is

On the contrary, in the second functional element forming region 16 and the third functional element forming region 17, the area of the channel forming region 13 per unit area is larger than that of the first functional element forming region 15. The amount of heat generated is also relatively large. On the other hand, the second functional element forming region 16 and the third functional element forming region 17 have an _on -resistance RON smaller than that of the first functional element forming region 15 due to the channel forming region 13 having a relatively large area. there is

The relationship between the amounts of heat generated in the first to third functional element forming regions 15 to 17 is as follows: amount of heat generated in the first functional element forming area 15 < amount of heat generated in the third functional element forming area 17 < second functional element forming area 16 . is the calorific value of On-resistance R ON of the first to third functional element forming regions 15 to 17 is as follows: ON-resistance R _ON of second functional element forming region 16 < _ON -resistance R _ON of third functional element forming region 17 < 1 is the _ON resistance RON of the functional element forming region 15; The dynamic clamping tolerance E _ac of the first to third functional element forming regions 15 to 17 is such that the dynamic clamping tolerance E _ac of the second functional element forming region 16 < the dynamic clamping tolerance E of the third functional element forming region 17 . _ac <dynamic clamping capacity _Eac of the first functional element formation region 15 .

In the semiconductor device 1 according to this embodiment, by devising the arrangement pattern of the first functional element forming region 15, the second functional element forming region 16, and the third functional element forming region 17, the temperature rise in the entire semiconductor device 1 can be suppressed. An object of the present invention is to provide a semiconductor device 1 capable of achieving both excellent dynamic clamping capability _Eac and _on -resistance RON while suppressing them. In the semiconductor device 1, the first functional element formation region 15 is arranged in a portion where the temperature is particularly likely to rise, and the second functional element formation region 16 and the third functional element formation region 17 are arranged in the other portions. It is intended to surely achieve the above-mentioned purpose.

Areas where temperature rise is likely to occur and whose temperature rise should be suppressed include an inner area spaced inward from the periphery of the active area 9 by a predetermined distance, and a plurality of channel formation areas 13 (a plurality of functional element formation areas). A region surrounded by the region 14), a region that does not overlap the end of the bonding wire 53 (the connection portion between the bonding wire 53 and the source metal 10) in plan view, or a combination of these regions selectively. can be exemplified. In these areas, it is difficult for heat to dissipate and heat tends to accumulate. In particular, the inner region of the active region 9 surrounded by a plurality of channel forming regions 13 (a plurality of functional element forming regions 14) is likely to be heated, and tends to be relatively high in temperature compared to other portions. .

Therefore, in the present embodiment, the first functional element forming region 15 is arranged in the central portion of the inner region of the active region 9, and the second functional element forming region 16 and the third functional element forming region 17 are arranged around it. , the area of the channel forming region 13 per unit area gradually increases from the central portion of the active region 9 toward the peripheral portion thereof. That is, in a region between the first functional element forming region 15 and the active region 9, a third functional element forming region 17 and a second functional element forming region 16 are formed in order from the first functional element forming region 15 side. . The arrangement of the plurality of functional element forming regions 14 will be described in more detail below.

17, the plurality of functional element formation regions 14 are composed of a first functional element formation region unit U1 including a plurality (four in the present embodiment) of _first functional element formation regions 15, and a plurality of (this In the embodiment, the second functional element formation region unit U2 includes the _second functional element formation regions 16 (four), and the third functional element formation region unit U2 includes a plurality (four in the present embodiment) of the third functional element formation regions 17. and a functional element formation region unit _U3 .

In this embodiment, each of the first to third functional element forming region units U ₁ to U ₃ has a rectangular shape (square shape) in a plan view with substantially the same area, and the active regions are arranged in a predetermined layout. 9 are arranged in a matrix. From another point of view, the first to third functional element formation region units U ₁ to U ₃ are arranged in a predetermined layout within a plurality of square regions partitioning the active region 9 in a matrix. .

The _first functional element forming region unit U1 is provided in the central portion of the active region 9 in the region where heat generation is to be suppressed, which is the present embodiment. The _third functional element formation area unit U3 is arranged around the _first functional element formation area unit U1 so as to surround the _first functional element formation area unit U1. The plurality of _third functional element forming area units U3 form an annular (square annular) area _XA in plan view.

The _second functional element forming area unit _U2 is arranged around the area XA so as to surround the area _XA . Thus, the plurality of _second functional element forming area units U2 form an annular (square annular) area _XB in a plan view. Thus, in this embodiment, the area of the channel forming region 13 per unit area gradually increases from the central portion of the active region 9 toward the peripheral portion thereof.

A specific planar structure of the first to third functional element formation region units U ₁ to U ₃ will be described below with reference to FIGS. 18A to 18C. 18A is an enlarged plan view showing the first functional element formation region 15 (first functional element formation region unit U ₁ ) shown in FIG. 17. FIG. 18B is an enlarged plan view showing the second functional element formation region 16 (second functional element formation region unit U ₂ ) shown in FIG. 17. FIG. 18C is an enlarged plan view showing the third functional element formation region 17 (third functional element formation region unit U ₃ ) shown in FIG. 17. FIG.

18A to 18C, the first to third functional element forming region units U ₁ to U ₃ are adjusted in the area of the channel forming region 13 per unit area, and the first to third functional element forming region units U 1 to U 3 The layout of formation regions 15 to 17 is changed. In the following description, the ratio of the area of the channel formation region 13 to the unit area is 100% when the channel formation region 13 exists in the entire region (that is, the functional element formation region 14) between the trench gate structures 54. defined and explained.

Referring to FIG. 18A, first functional element formation region unit U1 includes a plurality of _first functional element formation regions 15 in which the ratio of the area of channel formation regions 13 to the unit area is approximately 25%. Referring to FIG. 18B, second functional element formation region unit U2 includes a plurality of _second functional element formation regions 16 in which channel formation regions 13 account for about 75% of the unit area. Referring to FIG. 18C, third functional element formation region unit U3 includes a plurality of _third functional element formation regions 17 in which channel formation regions 13 account for about 50% of the unit area.

18A to 18C, in the present embodiment, a plurality of channel forming regions 13 are arranged in first to third functional element forming regions 15 to 17 in a zigzag arrangement or zigzagging layout. formed.
Referring to FIG. 18A, in each first functional element formation region 15 of _first functional element formation region unit U1, a plurality of channel formation regions 13 are arranged in a zigzag pattern along the length direction of trench gate structure 54 . It is For each trench gate structure 54 , the plurality of channel forming regions 13 are alternately spaced along one side and the other side of each trench gate structure 54 along the length of the trench gate structure 54 . are arranged as follows. The plurality of channel forming regions 13 are arranged only on one lateral side or the other lateral side crossing the trench gate structure 54 .

In the _first functional element forming region unit U1, the proportion of the area of the channel forming region 13 per unit area is set to about 25% due to such a configuration. In the first functional element formation region unit U1, the channel formation region 13 is arranged on _one side or the other side of the trench gate structure 54 with a gap from the other channel formation region 13. It can effectively disperse the source.

Moreover, the channel forming region 13 arranged on one side does not face the channel forming region 13 arranged on the other side with the trench gate structure 54 interposed therebetween. Therefore, in the lateral direction intersecting the trench gate structure 54, multiple heat sources do not face each other with the trench gate structure 54 interposed therebetween. As a result, the heat generated in one channel forming region 13 can be prevented from being propagated to the other channel forming regions 13, so that the occurrence of thermal interference can be effectively suppressed. In this manner, the _first functional element formation region unit U1 is configured to effectively suppress the temperature rise.

Referring to FIG. 18B, each second functional element formation region 16 of _second functional element formation region unit U2 corresponds to each channel formation region 13 along the length direction of trench gate structure 54 in the configuration shown in FIG. 18A. along its length. In the lateral direction crossing the trench gate structures 54, the channel forming region 13 formed on one trench gate structure 54 side is integrally formed with the channel forming region 13 formed on the other trench gate structure 54 side. there is In this manner, the zigzagging channel formation regions 13 are formed in the respective second functional element formation regions 16 . In the _second functional element forming region unit U2, the proportion of the area of the channel forming region 13 per unit area is about 75% due to such a configuration.

Referring to FIG. 18C, each third functional element formation region 17 of _third functional element formation region unit U3 corresponds to each channel formation region 13 along the length direction of trench gate structure 54 in the configuration shown in FIG. 18A. along its length. In the _third functional element forming region unit U3, the ratio of the area of the channel forming region 13 per unit area is about 50% due to such a configuration.

In this embodiment, an example in which the first to third functional element forming regions 15 to 17 are employed in which the ratio of the area of the channel forming region 13 per unit area is set to about 25%, 50%, and 75% will be described. bottom. However, the ratio of the area of the channel forming region 13 to the unit area is appropriately within the range of 0% or more and 100% or less in each functional element forming region 14 (each of the first to third functional element forming regions 15 to 17). May be changed. For example, one functional element forming region unit may include a plurality of functional element forming regions 14 having different ratios of the area of the channel forming region 13 per unit area within the range of 0% or more and 100% or less. .
<Cross-sectional structure of functional element forming region>
Next, specific cross-sectional structures of the first to third functional element formation region units U ₁ to U ₃ will be described with reference to FIGS. 19A and 19B. FIG. 19A is a longitudinal sectional view along line XIXA--XIXA shown in FIG. 18A. FIG. 19B is a vertical cross-sectional view along line XIXB-XIXB shown in FIG. 18A. As is clear from FIGS. 18A to 18C, the _second functional element formation region unit U2 and the _third functional element formation region unit U3 have substantially the same cross-sectional structure as the _first functional element formation region unit U1. Therefore, the description thereof is omitted.

19A and 19B, the substrate 2 described above includes an n ⁺ -type semiconductor substrate 20 and an n ⁻ -type epitaxial layer 55 formed on the semiconductor substrate 20 . A drain region 56 is formed by semiconductor substrate 20 and epitaxial layer 55 . The front surface of the substrate 2 is formed by the epitaxial layer 55 and the rear surface of the substrate 2 is formed by the semiconductor substrate 20 .

The source metal 10 described above is formed on the front surface of the substrate 2 , and the drain metal 57 is formed on the rear surface of the substrate 2 . The drain metal 57 may correspond to the aforementioned first electrode 112a. The trench gate structure 54 described above is built into the surface layer of the epitaxial layer 55, and includes a trench 24 formed by digging down the epitaxial layer 55 and a gate electrode embedded in the trench 24 with a gate insulating film 25 interposed therebetween. 26.

19A and 19B show an example in which the trench 24 is formed substantially perpendicular to the surface of the epitaxial layer 55. FIG. However, the trench 24 may be formed in a tapered cross-sectional shape in which the opening width gradually narrows along the depth direction. 19A and 19B show an example in which the bottom portion of trench 24 is rounded outward from the side surface of trench 24 . However, the bottom of trench 24 may be formed parallel to the surface of epitaxial layer 55 .

On the sides (both side surfaces) of the trench gate structure 54, an n ⁺ -type source region 27, a p ⁻ -type body region 28 and a drain region 56 (epitaxial layer 55) are formed in the depth direction from the surface side of the substrate 2. ) are provided in order. Source region 27 , body region 28 and drain region 56 are all formed in contact with trench gate structure 54 and face gate electrode 26 with gate insulating film 25 interposed therebetween.

Body region 28 is shared by trench gate structure 54 on one side and trench gate structure 54 on the other side between adjacent trench gate structures 54 . Source region 27 is formed to be exposed from the surface of body region 28 . The planar shape of the source region 27 corresponds to the planar shape of the channel forming region 13 . The body region 28 forming the side surface of the trench gate structure 54 below the source region 27 is the channel forming region 13 . Formation of a channel in the channel forming region 13 is controlled by a trench gate structure 54 (gate electrode 26).

Therefore, the area of the channel forming region 13 described above is defined by the area of the region serving as the current path in plan view. More specifically, the area of the channel forming region 13 is defined by the facing area of the source region 27 facing the drain region 56 (epitaxial layer 55) with the body region 28 interposed therebetween in plan view.
A p ⁺ -type body contact region 30 is further formed between the plurality of trench gate structures 54 so as to be exposed from the surface of the body region 28 outside the source region 27 (see also FIGS. 18A to 18C). .). Body contact region 30 is formed in contact with the side surface of trench gate structure 54 and faces gate electrode 26 with gate insulating film 25 interposed therebetween. The bottom of body contact region 30 is located in the region between the bottom of body region 28 and the bottom of source region 27 .

FIGS. 19A and 19B show an example in which the end portion of the body contact region 30 not in contact with the trench gate structure 54 includes an overlap portion selectively covering the source region 27 . However, body contact regions 30 that do not include overlapping portions may be provided. Also, a configuration in which the body contact region 30 does not exist may be adopted. In this case, body region 28 is exposed from the surface of epitaxial layer 55 outside source region 27 .

A surface insulating film 58 is formed on the surface of the epitaxial layer 55 so as to cover the trench gate structure 54 . A contact hole 59 is formed in the surface insulating film 58 to selectively expose the source region 27 and the body contact region 30 . The aforementioned source metal 10 enters the contact hole 59 from above the surface insulating film 58 and is electrically connected to the source region 27 and the body contact region 30 within the contact hole 59 .
<Effect of semiconductor device>
Next, effects of the semiconductor device 1 will be described with reference to FIGS. 20 and 21. FIG. FIG. 20 is a graph showing on-resistance R _ON -dynamic clamping capability E _ac characteristics. In FIG. 20, the vertical axis is the dynamic clamping capacity E _ac [mJ/mm ² ], and the horizontal axis is the on-resistance R _ON [mΩ·mm ² ]. The graph of FIG. 20 shows a plot P ₁ , a plot P ₂ , a plot P ₃ and an approximate straight line A connecting these three plots P ₁ , P ₂ and P ₃ .

A plot P ₁ shows the on-resistance R _ON vs. dynamic clamp when only the first functional element formation region units U ₁ (ratio of the area occupied by the channel formation region 13=25%) are laid out in a matrix in the active region 9. It shows the withstand E _ac characteristics.
A plot P ₂ plots the ON resistance R _ON vs. the dynamic clamp when only the second functional element formation region units U ₂ (ratio of the area occupied by the channel formation region 13=75%) are laid out in a matrix in the active region 9. It shows the withstand E _ac characteristics.

A plot P ₃ shows the on-resistance R _ON vs. dynamic clamp when only the third functional element formation region units U ₃ (ratio of the area occupied by the channel formation region 13=50%) are laid out in a matrix in the active region 9. It shows the withstand E _ac characteristics.
From the approximate straight line A, it can be understood that the area of the channel forming region 13 per unit area and the _on -resistance RON are in an inversely proportional relationship. That is, when the area of the channel forming region 13 per unit area increases, the on-resistance _RON decreases, and when the area of the channel forming region 13 per unit area decreases, the _on -resistance RON increases.

Further, from the approximation line A, it is understood that the area of the channel forming region 13 per unit area and the dynamic clamping capability _Eac are in an inversely proportional relationship. That is, when the area of the channel forming region 13 per unit area increases, the dynamic clamping resistance _Eac decreases, and when the area of the channel forming region 13 per unit area decreases, the dynamic clamping resistance _Eac increases.

Referring to plot P ₁ , when only first functional element formation region units U ₁ (ratio of area occupied by channel formation region 13=25%) are laid out in a matrix in active region 9, relatively high A good dynamic clamping capability E _ac can be achieved, but the on-resistance R _ON is relatively high. On the other hand, referring to the plot P2, when only the _second functional element formation region units U2 ₍ ratio of the area occupied by the channel formation region 13=75%) are laid out in a matrix in the active region 9, the comparison Although it is possible to realize a relatively low on-resistance _RON , the dynamic clamping capability _Eac is relatively low.

From this, it is understood that there is a trade- _off relationship between the dynamic clamping capability _Eac and the on-resistance RON. Therefore, by mixing various functional element forming regions 14 having different areas of the channel forming regions 13 per unit area within the limited region (area) of one active region 9, the It is understood that the values of the on-resistance R _ON and the dynamic clamping capability E _ac can be set in the region.

Therefore, in the present embodiment, the first functional element formation region unit U1, which is configured to generate less heat and have _a greater dynamic clamping tolerance _Eac , is placed in the region where heat generation is to be suppressed, that is, the active region 9. is placed in the center of As a result, it is possible to effectively suppress the temperature rise of the active region 9 and also suppress the transient and local high temperature in the central portion of the active region 9 . In addition, the dynamic clamp tolerance _Eac can be increased by the _first functional element formation region unit U1.

On the other hand, a _second functional element formation region unit U2 having a larger area of the channel formation region 13 per unit area than the _first functional element formation region unit U1 is provided outside the region where heat generation is to be suppressed. are placed. Therefore, in the _second functional element formation region unit U2, since a relatively large area of the channel formation region 13 can ensure a relatively large area of the current path, the _first functional element formation region unit U1 and the like can coexist. By doing so, it is possible to suppress the reduction in the current path as a whole. This makes it possible to suppress an increase in on-resistance by utilizing the region outside the region where heat generation should be suppressed.

In addition, in the present embodiment, in the region between the first functional element forming region 15 (first functional element forming region unit U ₁ ) and the second functional element forming region 16 (second functional element forming region unit U ₂ ), A third functional element forming region 17 (third functional element forming region unit U ₃ ) is provided. The third functional element forming region 17 (third functional element forming region unit U ₃ ) consists of the first functional element forming region 15 (first functional element forming region unit U ₁ ) and the second functional element forming region 16 (second functional element forming region unit U 1 ). It has an on-resistance R _ON -dynamic clamping capability E _ac characteristic between the element formation region unit U ₂ ). As a result, it is possible to suppress abrupt changes in characteristics between the _first functional element forming region unit U1 and the _second functional element forming region unit U2, and to adjust the on-resistance R _ON -dynamic clamping capability E _ac characteristic to the desired characteristic. Better matching is possible.

FIG. 21 is a plan view for explaining the arrangement relationship between the bonding wires 53 and the _second functional element formation region unit U2. It should be noted that FIG. 21 is a simplified diagram of the aforementioned active region 9, and for convenience of explanation, the _second functional element formation region unit U2 is shown with thick cross hatching.
Referring to FIG. 21, _second functional element forming region unit U2 is provided in a region overlapping with the end of bonding wire 53 (connection portion between bonding wire 53 and source metal 10) in plan view. Heat generated in the active region 9 normally takes a propagation path of being radiated to the outside through the source metal 10 . On the other hand, in the end portion of the bonding wire 53 or a region close to it, the heat generated in the active region 9 can take a propagation path of dissipating to the outside via the bonding wire 53 in addition to the source metal 10 . can.

Therefore, by providing the _second functional element formation region unit U2, which generates a relatively large amount of heat, in a region that overlaps with the end of the bonding wire 53 in plan view, the heat generated in the _second functional element formation region unit U2 can be dissipated. In addition to the source metal 10, the bonding wires 53 can be used to dissipate to the outside. Thereby, the temperature rise in the active region 9 (the temperature rise in the substrate 2) can be effectively suppressed. Moreover, this can satisfactorily suppress an increase in the on-resistance _RON , and favorably increase the dynamic clamping resistance _Eac .

In such a configuration, source metal 10 preferably comprises an electrically conductive material with relatively high thermal conductivity, such as copper or aluminum. The source metal 10 may be a copper plating film formed by plating. Similarly, bonding wires 53 preferably comprise a conductive material with relatively high thermal conductivity, such as copper or aluminum. By adopting source metal 10 containing copper or aluminum and bonding wires 53, heat dissipation can be further improved.

In the present embodiment, the example in which the end portion of the bonding wire 53 is arranged at the peripheral portion of the active region 9 in plan view has been described. However, the ends of the bonding wires 53 can be provided anywhere within the active region 9 in plan view, as shown in FIG. In the case of such a configuration, the _second functional element forming region unit U2 may be arranged in accordance with the position of the end of the bonding wire 53. FIG. In this configuration, the _first functional element formation area unit U1 and the _third functional element formation area unit U3 are arranged in areas outside the _second functional element formation area unit U2, where heat generation is to be suppressed, and where heat generation is to be suppressed. It may be selectively arranged around the region.

As described above, according to the semiconductor device 1 according to the present embodiment, the temperature rise can be suppressed by devising the layout of the channel forming region 13 . Further, according to the semiconductor device 1 according to the present embodiment, it is possible to increase the dynamic clamping capability _Eac while suppressing an increase in the on-resistance _RON .
<Manufacturing Method of Power MISFET>
Next, an example of a method of manufacturing the power MISFET formed in the active region 9 will be described with reference to FIGS. 23A to 23G. 23A to 23G are vertical cross-sectional views showing one step of the method of manufacturing the power MISFET. 23A to 23G are longitudinal sectional views of the portion corresponding to FIG. 19A.

First, as shown in FIG. 23A, substrate 2 including semiconductor substrate 20 and epitaxial layer 55 formed on semiconductor substrate 20 is prepared. Next, an ion implantation mask (not shown) having selective openings in regions where body regions 28 are to be formed is formed over substrate 2 . Then, p-type impurities are implanted into the surface layer portion of the epitaxial layer 55 (substrate 2) through the ion implantation mask. Thereby, the body region 28 is formed in the surface layer portion of the epitaxial layer 55 . After the body regions 28 are formed, the ion implantation mask is removed.

Next, as shown in FIG. 23B, a hard mask 35 having selective openings 35a in regions where trenches 24 are to be formed is formed on epitaxial layer 55. As shown in FIG. Then, the surface layer portion of the epitaxial layer 55 is selectively removed by etching through the hard mask 35 . A plurality of trenches 24 are thus formed. After trenches 24 are formed, hard mask 35 is removed.

Next, as shown in FIG. 23C, a gate insulating film 25 made of silicon oxide is formed on the inner wall surfaces of trenches 24 by, for example, thermal oxidation. Gate insulating film 25 may be formed by depositing an insulating material on the inner wall surface of trench 24 by, for example, a CVD method.
Next, as shown in FIG. 23D, an electrode material (eg, polysilicon) is deposited to fill the trenches 24 and cover the epitaxial layer 55 by, eg, CVD. The deposited layer of electrode material is then selectively etched back to form gate electrode 26 within trench 24 . A trench gate structure 54 is thereby obtained.

Next, as shown in FIG. 23E , source region 27 and body contact region 30 are formed in the surface layer of body region 28 . The source region 27 is formed by implanting n-type impurities through an ion implantation mask having selective openings in regions where the source region 27 is to be formed. As a result, the source region 27 having a relatively small area per unit area in plan view and the source region 27 having a relatively large area per unit area in plan view are selectively selected. It is formed. In other words, this results in a first functional element forming region 15 (first functional element forming region unit U ₁ ), a second functional element forming region 16 (second functional element forming region unit U ₂ ), and a third functional element forming region. A region 17 (third functional element formation region unit U ₃ ) is formed.

The body contact regions 30 are formed by implanting p-type impurities through an ion implantation mask having selective openings in regions where the body contact regions 30 are to be formed.
Next, as shown in FIG. 23F, an insulating material (silicon oxide in this embodiment) is deposited on the epitaxial layer 55 by, for example, CVD. Thereby, a surface insulating film 58 is formed on the epitaxial layer 55 . Next, surface insulating film 58 is selectively etched to form contact holes 59 in surface insulating film 58 that selectively expose source region 27 and body contact region 30 .

Thereafter, as shown in FIG. 23G, a copper plating film that will become the source metal 10 is formed on the surface insulating film 58 by, for example, copper plating. The source metal 10 may be an aluminum film formed by sputtering. Further, an aluminum film to be the drain metal 57 is formed on the rear surface side of the substrate 2 by sputtering, for example. Drain metal 57 may be a copper-plated film formed by copper plating, for example. A power MISFET (switching circuit 3) is manufactured through the above steps.

In addition to the power MISFET (switching circuit 3), the current sensor circuit 48, the temperature sensor circuit 5, the overcurrent protection circuit 49, the overheat protection circuit 7, and the low voltage malfunction prevention circuit 8 are also formed on the same substrate 2. be. Therefore, part of the process for forming the current sensor circuit 48, the temperature sensor circuit 5, the overcurrent protection circuit 49, the overheat protection circuit 7, and the low voltage malfunction prevention circuit 8 is utilized to You may make it form a part.

On the contrary, using part of the process of the power MISFET (switching circuit 3), the current sensor circuit 48, the temperature sensor circuit 5, the overcurrent protection circuit 49, the overheat protection circuit 7 and the low voltage malfunction prevention circuit 8 may form part of the That is, part of the process of forming the current sensor circuit 48, the temperature sensor circuit 5, the overcurrent protection circuit 49, the overheat protection circuit 7, and the low voltage malfunction prevention circuit 8, and the process of forming the power MISFET (switching circuit 3). By sharing the part with the semiconductor device 1, the number of man-hours for manufacturing the semiconductor device 1 can be reduced.
<Semiconductor package>
The semiconductor device 1 may be incorporated in a semiconductor package 41 as shown in FIG. 24 in addition to the semiconductor packages shown in FIGS. FIG. 24 is a plan view showing a semiconductor package 41 in which the semiconductor device 1 is incorporated, a part of which is cut away.

As shown in FIG. 24, the semiconductor package 41 is a so-called TO (Transistor Outline) resin package such as TO-220. The semiconductor package 41 includes a semiconductor device 1, a die pad 42 on which the semiconductor device 1 is mounted, a plurality of leads 43 arranged around the die pad 42, and a mold resin 44 sealing them. Semiconductor device 1 is bonded to die pad 42 via a conductive bonding material (solder), for example.

The multiple leads 43 include three terminals 45 , 46 , 47 . Three terminals 45 , 46 , 47 are spaced apart from each other on one side of the die pad 42 . A center terminal 46 of the three terminals 45 , 46 , 47 is formed integrally with one side end of the die pad 42 . Terminals 45 and 47 on both sides of the three terminals are spaced apart from the die pad 42 . Terminals 45 and 47 on both sides are selectively electrically connected to predetermined portions of semiconductor device 1 via bonding wires 53, respectively. A part of the three terminals 45, 46, 47 is exposed from the mold resin 44 as an external terminal to be externally connected.

FIG. 24 shows a configuration in which the other end 42a of the die pad 42 (the end opposite to the side where the lead 43 is arranged) is exposed from the mold resin 44 and functions as a radiator. ing. However, a configuration in which the other end portion 42a of the die pad 42 is covered with the molding resin 44 may be employed.
The form of the semiconductor package in which the semiconductor device 1 is incorporated is not limited to the form shown in FIG. Therefore, the semiconductor device 1 includes SOP (Small Outline Package), QFN (Quad For Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package). , SOJ (Small Outline J-leaded Package), or other similar semiconductor packages.

Although the embodiments of the present disclosure have been described above, the present disclosure can also be implemented in other forms.
For example, in the above-described embodiments, the example in which the _first functional element formation region unit U1 is provided in the central portion of the active region 9 as the region where heat generation should be suppressed has been described. However, depending on the layout with the various circuits 48, 5, 49, 7, 8 (see FIGS. 15A and 15B) provided around the active region 9, the high-temperature region may be the central portion of the active region 9. It can also occur in other areas. In such a case, the first functional element forming area 15 (first functional element forming area unit U ₁ ) may be arranged in the high temperature area. Further, the end portion of the bonding wire 53 (the connection portion between the bonding wire 53 and the source metal 10) may be arranged so as to overlap such a high-temperature region in plan view.

Further, in the above-described embodiment, the _first functional element formation region unit U1 may be provided in a region that overlaps the end portion of the bonding wire 53 (the connection portion between the bonding wire 53 and the source metal 10) in plan view. . With this configuration, the temperature rise in the _first functional element formation region unit U1 can be further suppressed.
Further, in the above-described embodiments, an example in which a plurality of trench gate structures 54 extending linearly is formed has been described. However, by integrally forming a plurality of laterally extending trench gate structures 54 intersecting with the trench gate structure 54 and a plurality of linearly extending trench gate structures 54, the trench gate structure 54 having a lattice shape in plan view can be obtained. good too.

Also, in the above-described embodiments, a configuration in which the conductivity type of each semiconductor portion is reversed may be employed. That is, the p-type portion may be n-type, and the n-type portion may be p-type.
Also, in the above-described embodiments, the substrate 2 may include a p-type semiconductor substrate 20 instead of the n-type semiconductor substrate 20 . That is, the switching circuit 3 including the IGBT may be formed in the active region 9 by forming an IGBT (Insulated Gate Bipolar Transistor) instead of the MISFET. In this case, drain region 56 and drain metal 57 correspond to the collector region and collector metal of the IGBT, and source metal 10 and source region 27 correspond to the emitter metal and emitter region of the IGBT.

The semiconductor device 1 drives an electric motor used as a power source for, for example, automobiles (including electric automobiles), trains, industrial robots, air conditioners, air compressors, fans, vacuum cleaners, dryers, refrigerators, and the like. It can be incorporated into a power module used in an inverter circuit that In addition, the semiconductor device 1 can be incorporated into power modules used in inverter circuits such as solar cells, wind power generators, and other power generators, and can also be incorporated into circuit modules constituting analog-controlled power sources, digital-controlled power sources, and the like. be able to.

In addition, various design changes can be made within the scope of the matters described in the claims.
In addition to the inventions described in the claims, the following inventions can be extracted from the descriptions of this specification and drawings with respect to the following second background art and problems.
<Second Background Art>
The performance of power semiconductors such as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) is characterized by low on-resistance and low loss, high-speed switching characteristics in the high-frequency region, and high breakdown voltage resistance against increases in drive voltage. etc., are required.

Here, inductive loads such as mechanical relays and solenoid coils are generally used in vehicle-mounted ECUs (Electronic Control Units) and home appliances to which power semiconductors are applied. In this case, when the power semiconductor is switched, a back electromotive force is generated due to the inductance of the inductive load, and a reverse voltage is generated between the drain electrode and the source electrode of the power semiconductor (when the power semiconductor is a power MOSFET). is applied. When the reverse voltage exceeds a certain value, an avalanche breakdown occurs. When an avalanche breakdown occurs in a power semiconductor, the power semiconductor may generate heat and eventually break down.

Therefore, in the past, in order to avoid the occurrence of avalanche breakdown in power semiconductors, measures such as installing active clamp circuits using avalanche diodes etc. have been taken, but this has led to the reduction of the number of parts and the miniaturization of electronic devices. Therefore, at present, efforts are being made to improve the durability of power semiconductors against avalanche breakdown, that is, to improve the avalanche resistance of power semiconductors.

For example, in a power semiconductor such as a power MOSFET in which a plurality of trench gates are formed, it is possible to improve the avalanche resistance by ensuring a wide interval between the trench gates. However, securing a wide interval between trench gates lowers the channel density and increases the on-resistance.
Therefore, as disclosed in Patent Document 2, the specifications (length and width) of each trench gate in a semiconductor element are individually set, and a region in which the channel density is set low in one semiconductor element, A semiconductor device has been proposed in which an increase in on-resistance is suppressed and avalanche resistance is improved by forming a region with a high channel density. However, the semiconductor device has a problem that the circuit design of the semiconductor element becomes more complicated than before, and the cost of the device increases.
<Second issue>
SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor device in which an increase in on-resistance is suppressed and avalanche resistance is improved while avoiding complication of the circuit design of a semiconductor element.
<Means for solving the second problem>
(Section 1)
A semiconductor element having an element main surface and an element back surface facing opposite sides in a thickness direction, a first electrode formed on the element back surface, and a second electrode and a third electrode formed on the element main surface. a first pad portion on which the semiconductor element is mounted and electrically connected to the first electrode; and a first terminal portion extending along a first direction perpendicular to the thickness direction of the semiconductor element. a second lead that is electrically connected to the second electrode; a third lead that is electrically connected to the third electrode; and a sealing resin that covers the semiconductor element, and a first bonding wire that connects the second electrode and the second lead, and the tip of the first bonding wire is connected to the second electrode. A semiconductor device, wherein a bonding portion is formed in contact with the second electrode, and a plurality of radiators are formed on the second electrode so as to be spaced apart from the bonding portion.
(Section 2)
Item 2. The semiconductor device according to Item 1, wherein the shape of the radiator is the same as the shape of the bonding portion.
(Section 3)
Item 3. The semiconductor device according to Item 2, wherein the first bonding wire and the radiator are both made of the same metal.
(Section 4)
Item 4. The semiconductor device according to Item 3, wherein the first bonding wire and the radiator are both made of Cu.
(Section 5)
5. The semiconductor device according to any one of Items 2 to 4, wherein the heat radiator has a diameter of 60 to 100 μm.
(Section 6)
5. The semiconductor device according to any one of Items 2 to 4, wherein the heat radiator has a height of 10 to 30 μm.
(Section 7)
Item 7. The semiconductor device according to any one of Items 2 to 6, wherein the first bonding wire has a wire diameter of 30 to 70 μm.
(Section 8)
Item 8. The semiconductor device according to any one of Items 1 to 7, wherein in the second electrode, the bonding portion and the plurality of radiators are arranged in a grid pattern.
(Section 9)
Item 9. The semiconductor device according to any one of Items 1 to 8, wherein the first bonding wires are plural, and the second electrode and the second lead are connected by the plural first bonding wires.
(Section 10)
10. The semiconductor device according to any one of Items 1 to 9, wherein the area of the second electrode is larger than the area of the third electrode.
(Item 11)
Item 11. The semiconductor device according to Item 10, wherein both the second electrode and the third electrode are composed of a Cu layer and an Al layer that are laminated to each other.
(Item 12)
Item 12. The semiconductor device according to Item 10 or 11, wherein a passivation film having electrical insulation properties and surrounding the periphery of the second electrode and the third electrode is formed on the main surface of the element.
(Item 13)
13. The semiconductor device according to any one of Items 1 to 12, wherein the semiconductor element is a power MOSFET or an IGBT.
(Item 14)
Item 14. The semiconductor device according to any one of Items 1 to 13, wherein the sealing resin is a thermosetting synthetic resin having electrical insulation.
(Item 15)
Item 15. The semiconductor device according to Item 14, wherein the sealing resin is an epoxy resin.
(Item 16)
Items 1 to 1, wherein the sealing resin has a resin main surface and a resin back surface facing opposite sides in the thickness direction of the semiconductor element, and a part of the first pad section is exposed from the resin back surface. 16. The semiconductor device according to any one of 15.
(Item 17)
The second lead and the third lead both extend along the first direction, and extend in the direction perpendicular to both the thickness direction of the semiconductor element and the first direction, and the first terminal portion. Item 17. The semiconductor device according to Item 16, wherein is positioned between the second lead and the third lead.
(Item 18)
Item 17, wherein, in the thickness direction of the semiconductor element, a body insertion hole is formed from the resin main surface to the first pad portion, and a hole wall of the body insertion hole is formed of the sealing resin. The semiconductor device according to .
(Item 19)
The second lead and the third lead extend in a second direction opposite to the first direction, and the first terminal portion, the second lead, and the third lead extend from the back surface of the resin. 17. The semiconductor device according to Item 16, wherein each part is exposed.
(Section 20)
Item 20. The semiconductor device according to any one of Items 1 to 19, wherein the first lead, the second lead, and the third lead are all made of an alloy containing Cu as a main component.
(Section 21)
Item 21. The semiconductor device according to any one of Items 1 to 20, further comprising an exterior plating layer covering respective portions of said first lead, said second lead and said third lead exposed from said sealing resin.
(Section 22)
Item 22. The semiconductor device according to Item 21, wherein the exterior plating layer is made of an alloy containing Sn as a main component.
(Section 23)
Item 23. The semiconductor device according to any one of Items 1 to 22, further comprising an internal plating layer formed on respective portions of said first lead, said second lead and said third lead covered with said sealing resin.
(Section 24)
Item 24. The semiconductor device according to Item 23, wherein the inner plating layer is made of Ag.
<Effect of means for solving the second problem>
The semiconductor device includes a semiconductor element having a first electrode formed on the rear surface of the element and a second electrode formed on the main surface of the element, and a first bonding wire connecting the second electrode and the second lead, A bonding portion contacting the second electrode is formed at the tip of the first bonding wire. Moreover, a plurality of radiators are formed on the second electrode so as to be spaced apart from the bonding portion. In this case, when the semiconductor element is switched, a reverse voltage is applied between the first electrode and the second electrode due to the inductance of the inductive load, and heat is generated in the second electrode. At this time, the heat generated in the second electrode is radiated to the periphery of the semiconductor element by the plurality of radiators, thereby suppressing the temperature rise of the semiconductor element. Therefore, by forming the plurality of heat sinks, the occurrence of avalanche breakdown can be avoided without changing the specifications of the trench gate in the semiconductor element, and as a result, the avalanche resistance of the semiconductor element is improved. do. Therefore, according to the above-described semiconductor device, it is possible to suppress an increase in on-resistance and improve avalanche resistance while avoiding complication of the circuit design of the semiconductor element.

DESCRIPTION OF SYMBOLS 2... Substrate 4... Heat sink 6... Encapsulation resin 9... Active region 11... Semiconductor device (power MOSFET/IGBT) 12... Junction layer 13... Channel forming region 14... Functional element forming region 15 1st functional element forming region 16 2nd functional element forming region 17 3rd functional element forming region 21 first lead 22 second lead 23 third lead 24 trench 25 Gate insulating film 26 Gate electrode 27 Source region 28 Body region 31 First bonding wire 32 Second bonding wire 51 Exterior plating layer 52 Interior plating layer 53 Bonding wire 54... Trench gate structure 56... Drain region 61... Resin main surface 62... Resin back surface 64... Main body insertion hole 111... Element main surface 111a... Second electrode 111b... Third electrode 111c... Passivation film , 112 Back surface of element 112a First electrode 211 First pad portion 211a Main surface of pad 211b Back surface of pad 211c Pad through hole 212 First terminal portion 213 Intermediate connection portion 221 2nd pad portion 222 2nd terminal portion 231 3rd pad portion 232 3rd terminal portion 311 bonding portion 631 resin first side surface 632 resin second side surface A10 semiconductor package , A20... semiconductor package, d... diameter, E _ac ... dynamic clamping capacity, h... height, RON... _ON resistance, U1... _first functional element forming area unit, U2... _second functional element forming area unit, U3... _Third functional element formation region unit, X1...First direction, X2...Second direction, Y...Third direction, Z...Thickness direction

Claims (14)

a substrate having an active region on which functional elements are formed;
a first functional element forming region formed in a central portion of the active region;
a peripheral functional element forming region formed around the first functional element forming region in the active region;
A plurality of gate structures formed on the substrate, linearly extending continuously in the same direction between the first functional element forming region and the peripheral functional element forming region, and arranged at equal intervals. and
each of the first functional element formation region and the peripheral functional element formation region includes a channel formation region serving as a current path between the adjacent gate structures;
In a predetermined unit area obtained by multiplying the width between the adjacent gate structures by the unit length along the length direction of the gate structure, the first functional element forming region occupies the unit area. the first area of the channel forming region is smaller than the second area of the channel forming region per unit area of the peripheral functional element forming region;
The semiconductor device according to claim 1, wherein the first functional element forming region has a higher on-resistance than the peripheral functional element forming region. The peripheral functional element forming region includes a second functional element forming region and a third functional element forming region having a higher on-resistance than the second functional element forming region,
2. The device according to claim 1, wherein said third functional element forming region is arranged around said first functional element forming region, and said second functional element forming region is arranged around said third functional element forming region. semiconductor device. 3. The semiconductor device according to claim 1, wherein an on-resistance gradually decreases from a central portion of said active region in which said first functional element forming region is formed toward a peripheral portion thereof. a substrate having an active region on which functional elements are formed;
a first functional element forming region formed in a central portion of the active region;
a peripheral functional element forming region formed around the first functional element forming region in the active region;
the first functional element forming region has a higher on-resistance than the peripheral functional element forming region;
The peripheral functional element forming region includes a second functional element forming region and a third functional element forming region having a higher on-resistance than the second functional element forming region,
the third functional element forming region is arranged around the first functional element forming region, and the second functional element forming region is arranged around the third functional element forming region;
the first functional element forming region, the second functional element forming region, and the third functional element forming region are respectively formed between a plurality of gate structures linearly formed along the same direction, and including a channel formation region that serves as a current path,
the channel formation region of the first functional element formation region includes a plurality of channel formation regions arranged in a zigzag pattern along the length direction of the gate structure;
The semiconductor device according to claim 1, wherein the channel formation region of the second functional element formation region is formed in a serpentine shape. When each gate structure is viewed, the plurality of channel formation regions of the first functional element formation region are arranged on one side surface side and the other side surface side of each gate structure along the length direction of the gate structure. 5. The semiconductor device according to claim 4, arranged alternately at intervals. In the second functional element forming region, the channel forming region formed on one side of the gate structure in the lateral direction crossing the gate structure is integrated with the channel forming region formed on the other side of the gate structure. 6. The semiconductor device according to claim 4, wherein the semiconductor device is formed in 7. The channel formation region of the third functional element formation region according to any one of claims 4 to 6, wherein said channel formation region includes a plurality of channel formation regions arranged in a zigzag pattern contacting each other at corners along the length direction of said gate structure. 1. The semiconductor device according to claim 1. a substrate having an active region on which functional elements are formed;
a first functional element forming region formed in a central portion of the active region;
a peripheral functional element forming region formed around the first functional element forming region in the active region;
the first functional element forming region has a higher on-resistance than the peripheral functional element forming region;
The peripheral functional element forming region includes a second functional element forming region and a third functional element forming region having a higher on-resistance than the second functional element forming region,
the third functional element forming region is arranged around the first functional element forming region, and the second functional element forming region is arranged around the third functional element forming region;
the first functional element forming region, the second functional element forming region, and the third functional element forming region are respectively formed between a plurality of gate structures linearly formed along the same direction, and including a channel formation region that serves as a current path,
the channel formation region of the first functional element formation region includes a plurality of channel formation regions arranged in a zigzag pattern along the length direction of the gate structure;
The semiconductor device, wherein the channel formation region of the third functional element formation region includes a plurality of channel formation regions arranged in a zigzag pattern contacting each other at corners along the length direction of the gate structure. 9. The semiconductor device according to claim 1, wherein said gate structure includes a trench gate structure. a trench formed in the substrate;
a gate electrode embedded in the trench via an insulating film;
A source region and a body formed in order from the front surface side to the back surface side of the substrate in surface layer regions of the substrate located laterally of each of the trenches in the first functional element formation region and the peripheral functional element formation region. A semiconductor device according to any one of claims 1 to 9, comprising a region and a drain region. a body contact region formed between the plurality of trenches and exposed from the surface of the body region outside the source region;
11. The semiconductor device according to claim 10, wherein said body contact region is formed in contact with side surfaces of said trench. 12. The semiconductor device according to claim 11, wherein said body contact region includes an overlap portion selectively covering said source region at an end thereof not in contact with said trench. 13. The semiconductor device according to claim 1, wherein the dynamic clamp tolerance of said first functional element formation region is greater than the dynamic clamp tolerance of said peripheral functional element formation region. 14. The semiconductor device according to claim 1, wherein the amount of heat generated in said first functional element formation region is smaller than the amount of heat generated in said peripheral functional element formation region.

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