CN115132711A

CN115132711A - Power semiconductor module structure based on copper-clad ceramic substrate

Info

Publication number: CN115132711A
Application number: CN202210593174.8A
Authority: CN
Inventors: 高崎哲; 王玉林
Original assignee: Shanghai Zhenghai Shikun Semiconductor Co ltd
Current assignee: Shanghai Zhenghai Shikun Semiconductor Co ltd
Priority date: 2022-05-28
Filing date: 2022-05-28
Publication date: 2022-09-30

Abstract

The invention discloses a power semiconductor module structure based on a copper-clad ceramic substrate, positive copper-clad lines are arranged on two sides of the copper-clad ceramic substrate, negative copper-clad lines and three-phase copper-clad lines are arranged between the positive copper-clad lines, an upper bridge gate electrode and Kelvin source electrode signal lines are hollowed in the middle of the three-phase copper-clad lines, a lower bridge gate electrode and Kelvin source electrode signal lines are hollowed in the middle of the negative copper-clad lines, an upper bridge power semiconductor chip is arranged on the positive copper-clad lines and is connected with the three-phase copper-clad lines through a current binding line, and a gate electrode and the Kelvin source electrode are connected with an upper bridge gate electrode and the Kelvin source electrode signal lines through a signal binding line, the lower bridge power semiconductor chip is arranged on the three-phase copper-clad grains and is connected with the negative copper-clad grains through a current binding line, and the gate pole and the Kelvin source electrode are connected with the lower bridge gate pole and the Kelvin source electrode signal grains through a signal binding line. The structure realizes the current sharing characteristic of the power semiconductor module, ensures the reliability of the open pipe of the module, and improves the service life and the performance of the module.

Description

Power semiconductor module structure based on copper-clad ceramic substrate

Technical Field

The invention relates to the technical field of power semiconductors, in particular to a power semiconductor module structure based on a copper-clad ceramic substrate.

Background

The power semiconductor module is a circuit module which combines and packages power semiconductor chips into a whole according to certain functions, and has the advantages of small size, high power density and the like, so that the power semiconductor module is widely applied to the field of new energy automobiles. With the development of high power and long endurance of new energy vehicles, the application environment of the power semiconductor module is increasingly severe, and the current sharing characteristic of the power semiconductor module is widely concerned.

With the rapid development of new energy automobiles, Si-based and SiC-based power semiconductor modules are continuously developed. In these high-power applications, increasingly higher requirements are placed on the switching frequency of the power semiconductor modules. To achieve higher current ratings and lower manufacturing costs, these power semiconductor modules typically employ a multi-chip parallel package structure. Then, due to the fact that a current loop of the copper-clad ceramic substrate is asymmetric and dynamic and static parameters of the power chips are inconsistent, large transient unbalanced current can occur among the parallel chips, and therefore the safety and stability of the power semiconductor module are challenged.

In a three-phase alternating-current motor control system, a circuit diagram of a power semiconductor module is shown in fig. 1, and a plurality of power semiconductor chips, such as upper bridge power semiconductor chips a 1-a 6 and lower bridge power semiconductor chips b 1-b 6 of a U phase in the diagram, are connected in parallel in a three-phase loop. As shown in fig. 2, which is a U-phase circuit diagram, in the circuit diagram of fig. 2, when the upper bridge power semiconductor chips a1 to a6 are turned on and the lower bridge power semiconductor chips b1 to b6 are turned off, the current Ia flows from the positive bus bar to the three-phase bus bar. The resistance value and the length of the source and gate control loop signals of each power semiconductor chip, the inductance generated by the length, the resistance and the inductance between the power semiconductor chips and the like determine the on-off time of each power semiconductor chip. If the switching time of the power semiconductor chip a1 is earlier than that of other power semiconductor chips, a large current flows intensively through the power semiconductor chip a1, which may lead to damage of the power semiconductor chip a1 in an extreme case. Meanwhile, as shown in fig. 3, when the lower bridge power semiconductor chips b1 to b6 are turned on and the upper bridge power semiconductor chips a1 to a6 are turned off, the current Ia flows from the three-phase bus bar to the negative bus bar. In this case, if the power semiconductor chip b6 closest to the three-phase bus bar is turned on earlier than the other power semiconductor chips, as described above, the current flows intensively through the power semiconductor chip b6, and in an extreme case, the power semiconductor chip b6 is damaged. Therefore, the service life and the performance of the power semiconductor module are reduced, the control performance of the motor is seriously influenced, and certain potential safety hazards exist.

Generally, a block diagram of a power semiconductor module in a three-phase ac motor control system is shown in fig. 4, which has a positive busbar and a negative busbar on one side of the power semiconductor module, and a three-phase busbar on the other side of the power semiconductor module, and each power semiconductor module is connected in parallel with a plurality of power semiconductor chips for carrying a large current.

Some SiC power semiconductors intended for high-speed driving have kelvin sources. The kelvin source connection is a circuit that separates the source of the power semiconductor chip into two parts, one part being the main path through which a large current flows and the other part being the return path for the gate drive signal. The Kelvin source connection is the same as the gate signal line, so that the wiring length of the power semiconductors connected from the signal terminal to the power semiconductors is uniform, and the variation of the switching time of different power semiconductors can be reduced. In the case of the kelvin source connection, it is preferable that the total length Ltn of the gate signal line and the kelvin source signal line in each power semiconductor satisfies the following equation:

Ltn=Lgn+Lkn

where Ltn is the total length, Lgn is the gate signal line length, and Lkn is the kelvin source signal line length.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a power semiconductor module structure based on a copper-clad ceramic substrate, and the structure adjusts the lengths of a source electrode and a gate pole loop signal wire of a power semiconductor chip through the current line design and the bonding wire connection of the copper-clad ceramic substrate, so as to adjust the tube opening time of each power semiconductor chip, thereby realizing the current sharing characteristic, ensuring the tube opening reliability of the power semiconductor module, and improving the service life and the performance of the power semiconductor module.

In order to solve the technical problems, the power semiconductor module structure based on the copper-clad ceramic substrate comprises the copper-clad ceramic substrate, a positive electrode bus bar, a negative electrode bus bar, a three-phase terminal, a plurality of upper bridge power semiconductor chips and a plurality of lower bridge power semiconductor chips, wherein the positive electrode bus bar comprises a first positive electrode terminal and a second positive electrode terminal, positive copper-clad lines are arranged on two sides of the copper-clad ceramic substrate in an extending mode from the upper edge to the lower edge, negative copper-clad lines are arranged between the positive copper-clad lines on the two sides from the upper edge to the middle part, three-phase copper-clad lines are arranged on the lower part of the copper-clad ceramic substrate in an extending mode from the lower edge to the upper edge of the copper-clad ceramic substrate and between the positive copper-clad lines and the negative copper-clad lines, the three-phase copper-clad lines on the lower part of the copper-clad ceramic substrate are hollowed in the middle, and strip-shaped upper bridge gate line signals and strip-bridge kelvin source signals are arranged at intervals on the hollowed-out parts, the negative electrode is provided with a hollow center, strip-shaped lower bridge gate electrode signal lines and strip-shaped lower bridge Kelvin source electrode signal lines are arranged at intervals at the hollow part, the first positive electrode terminal and the second positive electrode terminal are respectively arranged on the positive electrode copper-clad lines at two sides of the copper-clad ceramic substrate and are positioned at the upper edge, the negative electrode bus bar is arranged on the negative electrode copper-clad lines and is positioned at the upper edge, the three-phase terminals are arranged on the three-phase copper-clad lines and are positioned at the lower edge, the plurality of upper bridge power semiconductor chips are equally divided into single lines and are arranged on the positive electrode copper-clad lines at two sides of the copper-clad ceramic substrate and are positioned at the lower part of the copper-clad ceramic substrate, the plurality of upper bridge power semiconductor chips are connected with adjacent three-phase copper-clad lines, gate electrodes and Kelvin source electrodes through current binding lines and are respectively connected with strip-shaped upper bridge gate electrode signal lines and strip-shaped upper bridge Kelvin source electrode signal lines through signal binding lines, the lower bridge power semiconductor chips are equally divided into single lines and are arranged on the three-phase copper-clad lines and located on two sides of the negative copper-clad line, and the lower bridge power semiconductor chips are connected with the adjacent negative copper-clad lines through current binding lines, and the gate and the Kelvin source are respectively connected with the strip-shaped lower bridge gate signal line and the strip-shaped lower bridge Kelvin source signal line through signal binding lines.

Furthermore, the strip-shaped upper bridge gate electrode signal lines and the strip-shaped lower bridge gate electrode signal lines are respectively bent at the farthest ends by 180 degrees, and the gate electrodes of the plurality of upper bridge power semiconductor chips and the plurality of lower bridge power semiconductor chips are respectively connected to the bending sections through signal binding lines.

Furthermore, the strip-shaped upper bridge Kelvin source electrode signal lines and the strip-shaped lower bridge Kelvin source electrode signal lines are respectively bent by 180 degrees at the farthest ends, and Kelvin source electrodes of the plurality of upper bridge power semiconductor chips and the plurality of lower bridge power semiconductor chips are respectively connected to the bending sections through signal binding lines.

Furthermore, the strip-shaped upper bridge gate signal grains and the strip-shaped upper bridge Kelvin source signal grains are arranged in parallel at intervals, and the strip-shaped lower bridge gate signal grains and the strip-shaped lower bridge Kelvin source signal grains are arranged in parallel at intervals.

Further, the arrangement of the strip-shaped upper bridge gate electrode signal grains, the strip-shaped upper bridge Kelvin source electrode signal grains, the strip-shaped lower bridge gate electrode signal grains and the strip-shaped lower bridge Kelvin source electrode signal grains follows the following rules: if the distance from the gate pole of the power semiconductor chip to the gate pole signal line is the shortest, the distance from the Kelvin source of the power semiconductor chip to the Kelvin source signal line is the farthest; and if the distance from the gate pole of the power semiconductor chip to the gate pole signal line is farthest, the distance from the Kelvin source of the power semiconductor chip to the Kelvin source signal line is nearest.

Further, the difference between the length of the gate-to-gate signal trace of each power semiconductor chip and the sum of the lengths of the kelvin source-to-kelvin source signal traces is equal.

Further, the difference between the length of the gate-to-gate signal trace and the sum of the lengths of the kelvin source-to-kelvin source signal traces of each power semiconductor chip is less than 5 mm.

Furthermore, the plurality of upper bridge power semiconductor chips and the plurality of lower bridge power semiconductor chips are respectively four or six power semiconductor chips and are divided into two groups, and each group of power semiconductor chips are arranged in a single row.

The power semiconductor module structure based on the copper-clad ceramic substrate adopts the technical scheme, namely, positive copper-clad lines are respectively arranged on two sides of the copper-clad ceramic substrate, negative copper-clad lines and three-phase copper-clad lines are arranged between the positive copper-clad lines on the two sides, the upper parts of the three-phase copper-clad lines extend to the positions between the positive copper-clad lines and the negative copper-clad lines, upper bridge gate signal lines and upper bridge Kelvin source signal lines are hollowed in the middle of the three-phase copper-clad lines, lower bridge gate signal lines and lower bridge Kelvin source signal lines are hollowed in the middle of the negative copper-clad lines, two positive terminals are arranged on the positive copper-clad lines on the two sides, a negative bus bar is arranged on the negative copper-clad lines, three-phase terminals are arranged on the three-phase copper-clad lines, and an upper bridge power semiconductor chip is arranged on the positive copper-clad lines on the two sides and is connected with the adjacent three-phase copper-clad lines through current binding lines, The gate and the Kelvin source are connected with the upper bridge gate signal line and the upper bridge Kelvin source signal line through signal binding lines, the lower bridge power semiconductor chip is arranged on the three-phase copper-clad line and is connected with the adjacent negative copper-clad line through a current binding line, and the gate and the Kelvin source are connected with the lower bridge gate signal line and the lower bridge Kelvin source signal line through signal binding lines. The structure realizes the current sharing characteristic of the power semiconductor module, ensures the open-pipe reliability of the power semiconductor module, and improves the service life and the performance of the power semiconductor module.

Drawings

The invention is described in further detail below with reference to the following figures and embodiments:

FIG. 1 is a circuit diagram of a power semiconductor module in a three-phase AC motor control system;

FIG. 2 is a schematic diagram showing the flow direction of the U-phase upper bridge current in FIG. 1;

FIG. 3 is a schematic view showing the flow direction of the U-phase lower bridge current in FIG. 1;

FIG. 4 is a block diagram of a power semiconductor module in a three-phase AC motor control system;

FIG. 5 is a schematic structural diagram of a power semiconductor module based on a copper-clad ceramic substrate according to the present invention;

FIG. 6 is an enlarged view of portion A of FIG. 5;

FIG. 7 is an enlarged view of portion B of FIG. 5;

FIG. 8 is a schematic structural diagram of the module structure in which the upper bridge and the lower bridge are respectively four power semiconductor chips;

FIG. 9 is a schematic view of bending source signal lines of an upper bridge and a lower bridge in the module structure;

FIG. 10 is a schematic view of the module structure for bending the upper and lower bridges of four power semiconductor chips and gate signal lines;

FIG. 11 is a schematic view of a semiconductor structure with a positive bus bar in the middle of the module structure;

FIG. 12 is a schematic view of the module structure without bending gate signal lines and Kelvin source signal lines;

fig. 13 is a schematic diagram of a series circuit of an inductor L and a resistor R.

Detailed Description

For example, as shown in fig. 5, 6 and 7, the power semiconductor module structure based on the copper-clad ceramic substrate of the present invention includes a copper-clad ceramic substrate 1, a positive electrode bus bar, a negative electrode bus bar 3, a three-phase terminal 4, a plurality of upper bridge power semiconductor chips a 1-a 6 and a plurality of lower bridge power semiconductor chips b 1-b 6, the positive electrode bus bar includes a first positive electrode terminal 21 and a second positive electrode terminal 22, two sides of the copper-clad ceramic substrate 1 are provided with positive copper-

clad lines

11, 12 extending from an upper edge to a lower edge, a negative electrode copper-clad line 13 is provided between the positive electrode copper-

clad lines

11, 12 at the two sides, a three-phase copper-clad line 14 is provided between the positive electrode copper-

clad lines

11, 12 at the two sides and the negative electrode copper-

clad lines

11, 12 extending from the lower edge to the upper portion of the copper-clad ceramic substrate 1 and the negative electrode copper-clad line 13, the copper-clad ceramic substrate comprises a copper-clad ceramic substrate 1, a plurality of upper bridge power semiconductor chips a 1-a 6, a plurality of upper bridge power semiconductor chips a 11-a 6, a plurality of upper bridge power semiconductor chips a 1-a 11, a plurality of lower bridge power semiconductor chips a 11, a plurality of upper bridge copper lines 11, a plurality of lower bridge power semiconductor chips a6, a plurality of upper bridge power semiconductor chips a 1-a 6, a plurality of upper bridge power semiconductor chips a6, a plurality of lower bridge power semiconductor chips a 11, a plurality of upper bridge power semiconductor chips a6, a plurality of lower bridge power semiconductor chips a 9, a plurality of lower bridge power semiconductor chips a6, a plurality of upper bridge power semiconductor chips a 9, a plurality of lower bridge power semiconductor chips a6, a plurality of upper bridge power semiconductor chips a 9, a lower bridge power semiconductor chips a3, a plurality of upper bridge power semiconductor chips a lower bridge power semiconductor chips a, 12 and is located the lower part of the copper-clad ceramic substrate 1, the plurality of upper bridge power semiconductor chips a 1-a 6 are connected with the adjacent three-phase copper-clad lines 14 through the current binding line 5, the gate and the Kelvin source are respectively connected with the strip-shaped upper bridge gate signal line 16 and the strip-shaped upper bridge Kelvin source signal line 15 through the signal binding line 6, the plurality of lower bridge power semiconductor chips b 1-b 6 are equally divided and are arranged in the three-phase copper-clad lines 14 in a single row and are located at two sides of the negative copper-clad line 13, the plurality of lower bridge power semiconductor chips b 1-b 6 are connected with the adjacent negative copper-clad line 13 through the current binding line 7, the gate and the Kelvin source are respectively connected with the strip-shaped lower bridge gate signal line 18 and the strip-shaped lower bridge Kelvin source signal line 17 through the signal binding line 8.

Preferably, the strip-shaped upper bridge gate electrode signal line 16 and the strip-shaped lower bridge gate electrode signal line 18 are respectively bent at the farthest ends by 180 degrees, and the gate electrodes of the plurality of upper bridge power semiconductor chips a 1-a 6 and the plurality of lower bridge power semiconductor chips b 1-b 6 are respectively connected to the bending sections through the

signal binding lines

6 and 8.

As shown in fig. 9 and 10, preferably, the elongated upper bridge kelvin source signal lines 15 and the elongated lower bridge kelvin source signal lines 17 are respectively bent at the farthest ends by 180 °, and the kelvin sources of the plurality of upper bridge power semiconductor chips a 1-a 6 and the plurality of lower bridge power semiconductor chips b 1-b 6 are respectively connected to the bending sections through

signal binding lines

6 and 8.

Preferably, the strip-shaped upper bridge gate signal lines 16 and the strip-shaped upper bridge kelvin source signal lines 15 are arranged in parallel at intervals, and the strip-shaped lower bridge gate signal lines 18 and the strip-shaped lower bridge kelvin source signal lines 17 are arranged in parallel at intervals.

Preferably, the arrangement of the strip-shaped upper bridge gate signal line 16 and the strip-shaped upper bridge kelvin source signal line 15, and the arrangement of the strip-shaped lower bridge gate signal line 18 and the strip-shaped lower bridge kelvin source signal line 17 follow the following rules: if the distance from the gate pole of the power semiconductor chip to the gate pole signal line is the shortest, the distance from the Kelvin source of the power semiconductor chip to the Kelvin source signal line is the farthest; and if the distance from the gate pole of the power semiconductor chip to the gate pole signal line is farthest, the distance from the Kelvin source of the power semiconductor chip to the Kelvin source signal line is nearest.

Preferably, the difference between the length of the gate-to-gate signal trace of each power semiconductor chip and the sum of the lengths of the kelvin source-to-kelvin source signal traces is equal.

Preferably, the difference between the length of the gate-to-gate signal trace and the sum of the lengths of the kelvin source-to-kelvin source signal traces of each power semiconductor chip is less than 5 mm.

Preferably, the plurality of upper bridge power semiconductor chips a 1-a 6 and the plurality of lower bridge power semiconductor chips b 1-b 6 are respectively four or six power semiconductor chips and are divided into two groups, and each group of power semiconductor chips is arranged in a single column.

In the module structure, current flowing in from a positive busbar is divided into a left positive copper-clad line 11 and a right positive copper-clad line 12, an upper bridge power semiconductor chip a 1-a 6 is respectively listed on the positive copper-

clad lines

11 and 12, the current respectively flows into upper bridge power semiconductor chips a 1-a 6 which are arranged left and right, as seen from fig. 5 and 7, the left three power semiconductor chips form a group, the right three power semiconductor chips form a group, and the current passes through the left and right upper bridge power semiconductor chips a 1-a 6 to transmit the current to a three-phase copper-clad line 14 and flows into a three-phase terminal 4. In addition, the current flowing from the three-phase terminal 4 flows into the lower bridge power semiconductor chips b 1-b 6 through the three-phase copper-clad lines 14, as can be seen from fig. 5 and 6, the lower bridge power semiconductor chips b 1-b 6 are located on the three-phase copper-clad lines 14, the left three power semiconductor chips are in one group, the right three power semiconductor chips are in one group, and the current passes through the lower bridge power semiconductor chips b 1-b 6 to transmit the current to the negative copper-clad lines 13 and flows into the negative busbar 3; in fig. 6, the gate poles of the three power semiconductor chips on the left side of the lower bridge arm are connected to the gate signal line 18, and the gate poles of the three power semiconductor chips on the right side are also connected to the gate signal line 18; kelvin source electrodes of the three power semiconductor chips on the left side are connected to the kelvin source electrode signal lines 17, and the kelvin source electrodes of the three power semiconductor chips on the right side are connected to the kelvin source electrode signal lines 17; the gate signal lines 18 and the Kelvin source signal lines 17 are arranged in parallel, the gate signal lines 18 are bent at the farthest end by 180 degrees, and the gate is connected to a bending section, so that the gates of the b1, b2 and b3 chips are closest to the gate signal lines, and the Kelvin source is farthest from the Kelvin source signal lines; the gate of the b4, b5 and b6 chips is farthest away from the gate signal line, and the Kelvin source is nearest to the Kelvin source signal line; the total length Ltn of the b 1-b 6 chips is equal; as shown in fig. 6, the specific distance is calculated as follows:

ltn = Lgn + Lkn of b1 chip

Lgn=Ly1+L5+Lx1，Lkn=L3+Lx1+Lx2，

Since L3+ L5= Ly1, Ltn = Lgn + Lkn =2Ly1+2Lx1+ Lx2

Ltn = Lgn + Lkn for b2 chips

Lgn=Ly1+L4+Lx1，Lkn=L2+Lx1+Lx2，

Since L2+ L4= Ly1, Ltn = Lgn + Lkn =2Ly1+2Lx1+ Lx2

Ltn = Lgn + Lkn for the b3 chip,

Lgn=L1+Lx1，Lkn=L1+Lx1+Lx2，

since L1= Ly1, Ltn = Lgn + Lkn =2Ly1+2Lx1+ Lx2

Wherein L1= Ly1 is the distance between the gate signal line and both ends of the kelvin source signal line, L2 is the distance between the near end of the gate signal line and the gate terminals of chip b2 and chip b5, L3 is the distance between the near end of the gate signal line and the gate terminals of chip b1 and chip b4, L4 is the distance between the gate terminals of chip b2 and chip 5 and chip b3 and chip b6, L5 is the distance between the gate terminals of chip b1 and chip 4 and the gate terminals of chip b3 and chip b6, Lx1 is the distance between the center of chip b3 and the center of the gate signal line, Lx3 is the distance between the center of chip b6 and the center of the kelvin source signal line, and Lx2 is the distance between the gate signal line and the kelvin source signal.

Since the b1 chip is symmetrical to the b4 chip, the b2 chip is symmetrical to the b5 chip, the b3 chip is symmetrical to the b6 chip, and Lx1= Lx3, the total length Ltn of the b1 to b6 chips is equal; the total length Ltn of each chip of the lower bridge is ensured to be equal through the measures, so that the open-pipe time of each power semiconductor chip is controlled to be equal, the current sharing characteristic is realized, and the open-pipe reliability of the power semiconductor module is ensured;

as shown in fig. 7, the gate electrodes of the three power semiconductor chips on the left side of the upper bridge arm are connected to the gate signal trace 16, and the gate electrodes of the three power semiconductor chips on the right side are also connected to the gate signal trace 16; kelvin source electrodes of the left three power semiconductor chips are connected to the Kelvin source electrode signal lines 15, and Kelvin source electrodes of the right three power semiconductor chips are connected to the Kelvin source electrode signal lines 15; the gate signal lines 16 and the Kelvin source signal lines 15 are arranged in parallel, and the gate signal lines 16 are bent at the farthest end by 180 degrees; the gate of the power semiconductor chip is connected to the bending section, so that the gates of the a1, a2 and a3 chips are closest to the gate signal line, and the Kelvin source is farthest from the Kelvin source signal line; the gate of a4, a5 and a6 chip is farthest away from the gate signal line, and the Kelvin source is nearest to the Kelvin source signal line; the total length Ltn of the a 1-a 6 chips is equal; as shown in fig. 7, the specific distance is calculated as follows:

ltn = Lgn + Lkn for a1 chip

Lgn=Ly2+L9+Lx4，Lkn=L6+Lx4+Lx5，

Since L6+ L9= Ly2, Ltn = Lgn + Lkn =2Ly2+2Lx4+ Lx5

Ltn = Lgn + Lkn of a2 chip

Lgn=Ly2+L10+Lx4，Lkn=L7+Lx4+Lx5，

Since L7+ L10= Ly2, Ltn = Lgn + Lkn =2Ly2+2Lx4+ Lx5

Ltn = Lgn + Lkn for a3 chips,

Lgn=Ly2+L11+Lx4，Lkn=L8+Lx4+Lx5，

since L11+ L8= Ly2, Ltn = Lgn + Lkn =2LLy2+2Lx4+ Lx5

Where Ly2 is the distance between the gate signal line and both ends of the kelvin source signal line, L6 is the distance between the near end of the gate signal line and the gate terminals of chip a1 and chip a4, L7 is the distance between the near end of the gate signal line and the gate terminals of chip a2 and chip a5, L8 is the distance between the near end of the gate signal line and the gate terminals of chip a3 and chip a6, L9 is the distance between the far end of the gate signal line and the gate terminals of chip a1 and chip a4, L10 is the distance between the far end of the gate signal line and the gate terminals of chip a2 and chip a5, L11 is the distance between the far end of the gate signal line and the gate terminals of chip a3 and chip a6, Lx4 is the distance between the center of chip a3 and the center of the signal, Lx6 is the distance between the center of chip a6 and the center of the kelvin source signal, and Lx source signal pitch 5 is the distance between the gate signal line and the kelvin source signal.

Since the a1 chip is symmetrical to the a4 chip, the a2 chip is symmetrical to the a5 chip, the a3 chip is symmetrical to the a6 chip, and Lx4= Lx6, the total length Ltn of the a1 to a6 chips is equal; the total length Ltn of each chip of the upper bridge is ensured to be equal through the measures, so that the open-pipe time of each power semiconductor chip is controlled to be equal, the current sharing characteristic is realized, and the open-pipe reliability of the power semiconductor module is ensured to be optimal.

Fig. 8 shows a structure in which the upper bridge and the lower bridge are respectively four power semiconductor chips in the module structure, and other principles are shown in fig. 5 to 7, and similarly, the total lengths Ltn of the chips a1 to a4 are equal, and the total lengths Ltn of the chips b1 to b4 are equal; therefore, the open-tube time of each power semiconductor is controlled to be equal, the current sharing characteristic is realized, and the open-tube reliability of the power semiconductor module is ensured.

As shown in fig. 9, the module structure is a modification of fig. 5, where the upper bridge has six power semiconductor chips, and the lower bridge also has six power semiconductor chips, except that the source signal patterns of the upper and lower bridges are bent 180 ° at the farthest end, and the source of the chip is connected to the bent section of the source signal pattern, and other principles refer to fig. 5 to 7, so as to ensure that the total lengths Ltn of the chips a 1-a 6 are equal, and the total lengths Ltn of the chips b 1-b 6 are equal; and then the open-pipe time of each power semiconductor chip is controlled to be equal, the current sharing characteristic is realized, and the open-pipe reliability of the power semiconductor module is ensured.

Fig. 10 shows a modification of fig. 9, in which the upper bridge has four power semiconductor chips, the lower bridge also has four power semiconductor chips, and the source signal patterns of the upper and lower bridges are bent at the farthest ends by 180 °, and the source of each chip is connected to the bent section of the source signal pattern, and other principles are shown in fig. 5 to 7, where the total length Ltn of the chips a1 to a4 at the long ends is equal, and the total length Ltn of the chips b1 to b4 is equal; therefore, the open-pipe time of each power semiconductor chip is controlled to be equal, the current sharing characteristic is realized, and the open-pipe reliability of the power semiconductor module is ensured.

As shown in fig. 11, the module structure is a modification of fig. 5, and the upper bridge has six power semiconductor chips, and the lower bridge also has six power semiconductor chips, except that the positive and negative busbars are interchanged, and the copper-clad lines are modified, and other principles are as shown in fig. 5 to 7, so as to ensure that the total lengths Ltn of the a 1-a 6 chips are equal, and the total lengths Ltn of the b 1-b 6 chips are equal; and then the open-pipe time of each power semiconductor chip is controlled to be equal, the current sharing characteristic is realized, and the open-pipe reliability of the power semiconductor module is ensured.

Fig. 12 is a schematic view of a structure in which gate signal traces and kelvin source signal traces are not bent in the module structure, in the figure, the distance from the gate of the b1 chip to the gate signal traces is closest, the distance from the kelvin source of the b1 chip to the kelvin source signal material is farthest, the distance from the gate of the b3 chip to the gate signal traces is farthest, and the distance from the kelvin source of the b3 chip to the kelvin source signal traces is also closest to other chips, so that the total length Ltn of the b 1-b 3 chips is equal to ensure that the switching time of each chip is basically the same, and the upper bridges a 1-a 6 chips are the same to achieve the current sharing characteristic and ensure the open-loop reliability of the power semiconductor module.

Through the module structure design, the Ltn = Lgn + Lkn of the four or six chips of the upper bridge arm are equal, so that the deviation of the switching time of the semiconductor chips with different powers of the upper bridge arm is weakened, the Ltn = Lgn + Lkn of the four or six chips of the lower bridge arm is equal, the deviation of the switching time of the semiconductor chips with different powers of the lower bridge arm is weakened, the problem of uneven current of the semiconductor chips is solved, and the reliability of the power semiconductor module is improved.

As shown in fig. 13, the inductance L represents the inductance between the power semiconductor chips, the resistance R represents the resistance of the power semiconductor chip on, and in this circuit, the current i (t) generated instantaneously when the switch S is on is shown in formula 1:

（1）

(2)

that is, when the inductance is large, the current i (t) does not flow immediately even if the voltage E is applied. According to the principle, through the application of the module structure, the current in each power semiconductor chip can achieve the effect of gradually increasing, so that the large current generated by the concentrated current flowing through a certain power semiconductor chip is reduced, the current sharing characteristic of the module is improved, and the damage to the chip is avoided.

Claims

1. The utility model provides a power semiconductor module structure based on cover copper ceramic substrate, includes that cover copper ceramic substrate, anodal female arranging, female, the three-phase terminal of negative pole, a plurality of power semiconductor chip of going up a bridge and a plurality of power semiconductor chip of lower bridge, its characterized in that: the positive busbar comprises a first positive terminal and a second positive terminal, the two sides of the copper-clad ceramic substrate extend from the upper edge to the lower edge to form positive copper-clad lines, the two sides of the copper-clad ceramic substrate are provided with negative copper-clad lines from the upper edge to the middle part between the two positive copper-clad lines, the lower part of the copper-clad ceramic substrate extends from the lower edge to the two positive copper-clad lines to form three-phase copper-clad lines, the three-phase copper-clad lines of the lower part of the copper-clad ceramic substrate are hollowed in the middle, strip-shaped upper bridge gate signal lines and strip-shaped upper bridge Kelvin source signal lines are arranged at intervals of hollowed parts, the negative copper-clad lines are hollowed in the middle, strip-shaped lower bridge gate signal lines and strip-shaped lower bridge Kelvin source signal lines are arranged at intervals of the hollowed parts, and the first positive terminal and the second positive terminal are respectively arranged on the two sides of the copper-clad ceramic substrate and the copper-clad lines are arranged at intervals The upper edge is located, the negative busbar is located the negative pole covers copper line and is located the upper edge, three-phase terminal is located three-phase and is covered copper line and is located the lower part edge, a plurality of upper bridge power semiconductor chips divide and be single row and locate the positive pole that covers copper ceramic substrate both sides covers copper line and be located cover copper ceramic substrate lower part, a plurality of upper bridge power semiconductor chips divide and be single row through current binding line and connect adjacent three-phase and cover copper line, gate pole and kelvin source electrode connect rectangular shape upper bridge gate pole signal line and rectangular shape upper bridge kelvin source electrode signal line respectively through signal binding line, a plurality of lower bridge power semiconductor chips divide and be single row and locate the three-phase covers copper line and be located negative pole covers copper line both sides, a plurality of lower bridge power semiconductor chips connect adjacent negative pole through current binding line and cover copper line, gate pole and kelvin source electrode connect rectangular shape lower bridge gate pole signal line and rectangular shape lower bridge gate pole signal line respectively through signal binding line Bridge Kelvin source signal lines.

2. The copper-clad ceramic substrate-based power semiconductor module structure according to claim 1, wherein: the strip-shaped upper bridge gate electrode signal lines and the strip-shaped lower bridge gate electrode signal lines are respectively bent at the farthest ends by 180 degrees, and the gate electrodes of the plurality of upper bridge power semiconductor chips and the gate electrodes of the plurality of lower bridge power semiconductor chips are respectively connected to the bending sections through signal binding lines.

3. The copper-clad ceramic substrate-based power semiconductor module structure according to claim 1, wherein: the rectangular upper bridge Kelvin source electrode signal lines and the rectangular lower bridge Kelvin source electrode signal lines are bent 180 degrees at the farthest ends respectively, and Kelvin source electrodes of the plurality of upper bridge power semiconductor chips and the plurality of lower bridge power semiconductor chips are connected to the bending sections respectively through signal binding lines.

4. The copper-clad ceramic substrate-based power semiconductor module structure according to claim 1, 2 or 3, wherein: the strip-shaped upper bridge gate electrode signal grains and the strip-shaped upper bridge Kelvin source electrode signal grains are arranged in parallel at intervals, and the strip-shaped lower bridge gate electrode signal grains and the strip-shaped lower bridge Kelvin source electrode signal grains are arranged in parallel at intervals.

5. The copper-clad ceramic substrate-based power semiconductor module structure according to claim 4, wherein: the arrangement of the strip-shaped upper bridge gate electrode signal grains, the strip-shaped upper bridge Kelvin source electrode signal grains, the strip-shaped lower bridge gate electrode signal grains and the strip-shaped lower bridge Kelvin source electrode signal grains follows the following rules: if the distance from the gate pole of the power semiconductor chip to the gate pole signal line is the shortest, the distance from the Kelvin source of the power semiconductor chip to the Kelvin source signal line is the farthest; and if the distance from the gate pole of the power semiconductor chip to the gate pole signal line is farthest, the distance from the Kelvin source of the power semiconductor chip to the Kelvin source signal line is nearest.

6. The copper-clad ceramic substrate-based power semiconductor module structure according to claim 5, wherein: the difference between the length of the gate-to-gate signal trace of each power semiconductor chip and the sum of the lengths of the Kelvin source-to-Kelvin source signal traces is equal.

7. The copper-clad ceramic substrate-based power semiconductor module structure according to claim 5, wherein: the difference between the length of the gate-to-gate signal line of each power semiconductor chip and the sum of the lengths of the Kelvin source-to-Kelvin source signal lines is less than 5 mm.

8. The copper-clad ceramic substrate-based power semiconductor module structure according to claim 1, wherein: the upper bridge power semiconductor chips and the lower bridge power semiconductor chips are four or six power semiconductor chips respectively and are divided into two groups, and each group of power semiconductor chips are arranged in a single row.