CN218632045U - High-performance TFT array substrate with etching barrier layer - Google Patents
High-performance TFT array substrate with etching barrier layer Download PDFInfo
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- CN218632045U CN218632045U CN202222976709.8U CN202222976709U CN218632045U CN 218632045 U CN218632045 U CN 218632045U CN 202222976709 U CN202222976709 U CN 202222976709U CN 218632045 U CN218632045 U CN 218632045U
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Abstract
The utility model relates to a liquid crystal display technical field provides a high performance TFT array substrate with etching barrier layer, include: a glass substrate; a first metal layer forming a gate; the grid insulating layer is fixedly arranged on the upper surfaces of the first metal layer and the glass substrate; the left active layer and the right active layer are fixedly arranged on the upper surface of the gate insulating layer; the left end and the right end of the bridging layer are respectively connected with the left active layer and the right active layer; the left etching barrier layer is fixedly arranged on the upper surfaces of the gate insulating layer and the left active layer; the right etching barrier layer is fixedly arranged on the upper surfaces of the gate insulating layer and the right active layer; the second metal layer is connected with the left active layer to form a source electrode; and the third metal layer is connected with the right active layer to form a drain electrode. The utility model has the advantages that: under the prerequisite of the source electrode drain electrode distance of not shortening the TFT device, shorten active layer channel length, the utility model discloses a TFT array substrate has advantages such as the reaction is fast, the on-state current is big, threshold voltage is little.
Description
Technical Field
The utility model relates to a liquid crystal display technical field specifically relates to a high performance TFT array substrate with etching barrier layer.
Background
With the rapid development of artificial intelligence, the technology of the TFT-LCD liquid crystal screen is continuously improved, and the TFT-LCD liquid crystal screen has high definition, high speed, low power consumption and the like and is a development trend of the TFT-LCD liquid crystal screen.
In order to realize a high-performance display screen, one of the current manufacturers is to realize miniaturization of a TFT device by shortening the channel length of an active layer of the TFT device, and the shortening of the channel length of the active layer can realize a large on-state current, improve the response speed of the device, reduce the threshold voltage, and the like. However, in practice, the design of the channel length of the active layer is limited to the distance between the source and drain electrodes of the TFT device, and mainly takes into consideration the risk of short circuit and the like when the source and drain electrodes are too close to each other. Through technological development for many years, the source-drain spacing of the current Thin Film Transistor (TFT) is selected to be a safe minimum distance, which is generally controlled to be 5-6 μm.
Referring to fig. 1, a schematic structural diagram of a conventional TFT device is shown. The active layer is a semiconductor, and the active layer channel length refers to the length of the semiconductor between the source and the drain.
Therefore, how to shorten the channel length of the active layer without shortening the distance between the source and the drain of the TFT device is a technical problem to be solved in the art.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model lies in providing a high performance TFT array substrate with etching barrier layer, under the prerequisite of the source electrode drain electrode distance of not shortening the TFT device, shortens active layer channel length.
The utility model discloses a realize like this: a high-performance TFT array substrate having an etch stopper, comprising:
a glass substrate;
the first metal layer is fixedly arranged on the upper surface of the glass substrate to form a grid;
the grid insulating layer is fixedly arranged on the upper surfaces of the first metal layer and the glass substrate;
the left active layer is fixedly arranged on the upper surface of the gate insulating layer and is also positioned above the left end of the first metal layer;
the right active layer is fixedly arranged on the upper surface of the gate insulating layer and is also positioned above the right end of the first metal layer;
the bridging layer is fixedly arranged on the upper surface of the gate insulating layer, and the left end and the right end of the bridging layer are respectively connected with the left active layer and the right active layer;
the left etching barrier layer is fixedly arranged on the upper surfaces of the gate insulating layer and the left active layer and is also provided with a left digging hole;
the right etching barrier layer is fixedly arranged on the upper surfaces of the gate insulating layer and the right active layer and is also provided with a right digging hole;
the second metal layer is fixedly arranged on the upper surface of the left etching barrier layer and is connected with the left active layer through the left digging hole to form a source electrode;
and the third metal layer is fixedly arranged on the upper surface of the right etching barrier layer and is also connected with the right active layer through the right digging hole to form a drain electrode.
Further, the method also comprises the following steps:
the pixel electrode is fixedly arranged on the upper surface of the right etching barrier layer and is also connected with the third metal layer;
the conducting layer is fixedly arranged on the upper surface of the right etching barrier layer;
the passivation layer is fixedly arranged on the upper surfaces of the second metal layer, the third metal layer, the left etching barrier layer, the right etching barrier layer, the bridging layer, the pixel electrode and the conductive layer, and is provided with a through hole;
and the common electrode is fixedly arranged on the upper surface of the passivation layer and is also connected with the conductive layer through the through hole.
Further, the method also comprises the following steps:
the common electrode is fixedly arranged on the upper surface of the right etching barrier layer;
the conducting layer is fixedly arranged on the upper surface of the right etching barrier layer and is also connected with the common electrode;
the passivation layer is fixedly arranged on the upper surfaces of the second metal layer, the third metal layer, the left etching barrier layer, the right etching barrier layer, the bridging layer, the common electrode and the conducting layer, and is provided with a through hole;
and the pixel electrode is fixedly arranged on the upper surface of the passivation layer and is also connected with the third metal layer through the through hole.
Further, the first metal layer, the second metal layer, the third metal layer and the conductive layer are any one of an MO single-layer structure, a Ti single-layer structure, an MO/AL/MO three-layer structure, a Ti/AL/Ti three-layer structure, an AL/MO two-layer structure and an AL/Ti two-layer structure.
Furthermore, the left active layer and the right active layer are both made of IGZO materials, the left etching barrier layer and the right etching barrier layer are both made of SiOx materials, and the bridge layer, the pixel electrode and the common electrode are all made of ITO materials.
Furthermore, the gate insulating layer is of a SiOx single-layer structure or a SiNx/SiOx double-layer structure, and the passivation layer is made of SiOx, siNO or SiNx.
Furthermore, the left dug hole, the right dug hole and the through hole are all inverted cones.
The utility model has the advantages of: 1. the difference with traditional TFT device lies in, the utility model discloses a replace one section in the middle of the active layer with a bridging layer, the bridging layer is the conductor, the active layer is the semiconductor to holistic active layer channel length has just shortened, but the distance between source electrode and the drain electrode still remains unchanged this moment, has guaranteed the security of device; under the prerequisite of the source drain electrode distance of not shortening the TFT device promptly, shorten active layer channel length, the utility model discloses a TFT array substrate has advantages such as the reaction is fast, the on-state current is big, threshold voltage is little, improves the performance of display screen behind the practical application. 2. The left etching barrier layer and the right etching barrier layer are used for preventing etching acid liquor used in the next ITO film layer process from damaging the left active layer and the right active layer. 3. Because the ITO material has good electric conductivity and non-light tight characteristics, the utility model discloses a material that the bridging layer and the picture element electrode of TFT device chooseed for use all is ITO, and the bridging layer and the picture element electrode film forming under this structure are gone on at same process, just so simplify array substrate's structure, improve and produce reduce cost.
Drawings
The invention will be further described with reference to the following examples with reference to the accompanying drawings.
Fig. 1 is a schematic structural view of a conventional TFT device in the background art.
Fig. 2 is a first flow chart of the fabrication of the high performance TFT array substrate with an etching stop layer according to the present invention.
Fig. 3 is a second flow chart of the fabrication of the high performance TFT array substrate with an etching stop layer according to the present invention.
Fig. 4 is a third flow chart of the manufacturing process of the high-performance TFT array substrate with the etching stop layer according to the present invention.
Fig. 5 is a fourth flowchart illustrating a manufacturing process of the high-performance TFT array substrate with an etching stop layer according to the present invention.
Fig. 6 is a fifth flowchart illustrating a manufacturing process of the high-performance TFT array substrate with an etching stop layer according to the present invention.
Fig. 7 is a sixth flowchart illustrating a method for manufacturing a high performance TFT array substrate with an etching stop layer according to the present invention.
Fig. 8 is a seventh flowchart illustrating a manufacturing process of a high-performance TFT array substrate with an etching stop layer according to the present invention.
Fig. 9 is a flow chart eight illustrating the manufacturing process of the high performance TFT array substrate with the etching stop layer according to the present invention.
Fig. 10 is a flowchart nine illustrating a manufacturing process of the high-performance TFT array substrate with an etching stop layer according to the present invention.
Fig. 11 is a schematic diagram illustrating positions of the pixel electrode and the common electrode in fig. 10 being interchanged.
Reference numerals: a glass substrate 1; a gate electrode 2; a gate insulating layer 3; an active layer 4; a left active layer 41; the right active layer 42; a bridging layer 5; a source electrode 6; a drain electrode 7; a pixel electrode 8; a conductive layer 9; a passivation layer 10; a through hole 101; a common electrode 20; a left etch stop layer 30; digging a hole 301 on the left; a right etch stop layer 40; and (6) digging a hole 401 at the right.
Detailed Description
The embodiment of the utility model provides a through providing a high performance TFT array substrate with etching barrier layer, solved among the background art active layer channel length's design and restricted to the distance between TFT device source drain, when source drain interval is at safe minimum distance, if continue to shorten source drain interval, the shortcoming of short circuit can appear in the source drain; realized not shortening under the prerequisite of the source electrode drain electrode distance of TFT device, shortening active layer channel length, the utility model discloses a TFT device that array substrate carried on has advantages such as the reaction is fast, the on-state current is big, threshold voltage is little, improves the performance of display screen behind the practical application.
The embodiment of the utility model provides an in technical scheme for solving above-mentioned shortcoming, the general thinking is as follows:
the difference with traditional TFT device lies in, the utility model discloses a TFT device has replaced one section in the middle of the active layer with a bridging layer, and the bridging layer is the conductor, and the active layer is the semiconductor to holistic active layer channel length has just been shortened, and the length of semiconductor shortens promptly, but the distance between source electrode and the drain electrode still remains unchanged this moment, has guaranteed the security of device; the length of the active layer channel is shortened on the premise of not shortening the distance between the source electrode and the drain electrode of the TFT device.
Before the bridging layer is plated, a left etching barrier layer and a right etching barrier layer are plated on the left active layer and the right active layer, and the left etching barrier layer and the right etching barrier layer are used for preventing etching acid liquor of an ITO film layer in a subsequent process from damaging the left active layer and the right active layer.
The influence of the active layer channel length on the gate characteristics of Thin Film Transistors (TFTs) is significant, and the general trend is: the shorter the channel, the greater the on-current, and the longer the channel, the smaller the on-current. This is due to the fact that as the channel length increases, the probability of carriers being trapped in the drift increases, and the decrease in carrier density causes the threshold voltage to increase, which also causes the source-drain current I DS The increase becomes slower, resulting in an increased subthreshold swing, i.e. a decreased response speed of the device.
For better understanding of the above technical solutions, the following detailed descriptions will be provided in conjunction with the drawings and the detailed description of the embodiments.
Referring to fig. 1 to 11, a preferred embodiment of the present invention.
Referring to fig. 10, a high performance TFT array substrate having an etch stopper includes:
a glass substrate 1;
the first metal layer is fixedly arranged on the upper surface of the glass substrate 1 to form a grid 2;
the gate insulating layer 3 is fixedly arranged on the first metal layer and the upper surface of the glass substrate 1;
the left active layer 41 is fixedly arranged on the upper surface of the gate insulating layer 3 and is also positioned above the left end of the first metal layer;
a right active layer 42 fixedly disposed on the upper surface of the gate insulating layer 3 and located above the right end of the first metal layer;
the bridging layer 5 is fixedly arranged on the upper surface of the gate insulating layer 3, and the left end and the right end of the bridging layer are respectively connected with the left active layer 41 and the right active layer 42;
the left etching barrier layer 30 is fixedly arranged on the upper surfaces of the gate insulating layer 3 and the left active layer 41, and is also provided with a left dug hole 301;
the right etching barrier layer 40 is fixedly arranged on the upper surfaces of the gate insulating layer 3 and the right active layer 42 and is also provided with a right digging hole 401;
the second metal layer is fixedly arranged on the upper surface of the left etching barrier layer 30 and is also connected with the left active layer 41 through the left digging hole 301 to form a source electrode 6;
and a third metal layer fixedly disposed on the upper surface of the right etching stopper layer 40 and connected to the right active layer 42 through the right cutout 401 to form a drain electrode 7.
The difference with traditional TFT device lies in, the utility model discloses a TFT device has replaced one section in the middle of the active layer with a bridging layer 5, and bridging layer 5 is the conductor, and left active layer 41 and right active layer 42 are all semiconductors to holistic active layer channel length has just been shortened, and the length of semiconductor shortens promptly, but the distance between source electrode 6 and drain electrode 7 still remains unchanged this moment, has guaranteed the security of device; under the prerequisite of the 6 drain electrodes of source electrode 7 distances of TFT device that do not shorten promptly, shorten active layer channel length, the utility model discloses a TFT array substrate has advantages such as the reaction is fast, the on-state current is big, threshold voltage is little, improves the performance of display screen behind the practical application.
Arranging a left etching barrier layer 30 and a right etching barrier layer 40 on the upper surfaces of the left active layer 41 and the right active layer 42; the left and right etch stoppers 30 and 40 function to prevent the left and right active layers 41 and 42 from being damaged by etching acid solution used in the subsequent ITO film process.
Further comprising: a pixel electrode 8 fixedly disposed on the upper surface of the right etching stop layer 40 and connected to the third metal layer;
the conductive layer 9 is fixedly arranged on the upper surface of the right etching barrier layer 40;
the passivation layer 10 is fixedly arranged on the upper surfaces of the second metal layer, the third metal layer, the left etching barrier layer 30, the right etching barrier layer 40, the bridging layer 5, the pixel electrode 8 and the conductive layer 9, and the passivation layer 10 is provided with a through hole 101;
and the common electrode 20 is fixedly arranged on the upper surface of the passivation layer 10 and is also connected with the conductive layer 9 through the through hole 101.
The first metal layer (grid 2), the second metal layer (source 6), the third metal layer (drain 7) and the conducting layer 9 are any one of an MO single-layer structure, a Ti single-layer structure, an MO/AL/MO three-layer structure, a Ti/AL/Ti three-layer structure, an AL/MO double-layer structure and an AL/Ti double-layer structure.
The left active layer 41 and the right active layer 42 are IGZO materials, the left etching stopper layer 30 and the right etching stopper layer 40 are SiOx materials, and the bridge layer 5, the pixel electrode 8, and the common electrode 20 are ITO materials.
The gate insulating layer 3 is a SiOx single-layer structure or a SiNx/SiOx double-layer structure, and the passivation layer 10 is made of SiOx, siNO or SiNx material.
The left dug hole 301, the right dug hole 401 and the through hole 101 are all in inverted cone shapes. The deposition of the material is convenient to fix at the hole position.
With reference to fig. 2 to 10, the method for manufacturing a high performance TFT array substrate with an etching stop layer according to the present embodiment includes the following steps:
s1, plating a first metal layer on the upper surface of a glass substrate 1 to form a grid 2;
the gate 2 is used for transmitting a signal of the gate 2 to turn on and off the TFT device, and the material may be any one of an MO single-layer structure, a Ti single-layer structure, an MO/AL/MO three-layer structure, a Ti/AL/Ti three-layer structure, an AL/MO two-layer structure, and an AL/Ti two-layer structure, and is formed by PVD and wet etching with an acid solution.
S2, plating a gate insulating layer 3 on the first metal layer and the upper surface of the glass substrate 1;
the gate insulating layer 3 is used as an insulating medium and a capacitance medium between the gate 2 and the active layer, and is made of a SiOx single-layer structure or a SiNx/SiOx double-layer structure by CVD film forming and dry etching.
Considering that the requirements of the TFT device are fast response and low power consumption, which are achieved by shrinking the TFT device, and in order to achieve the miniaturization of the device, it is necessary to select a suitable high-K material (such as HfO 2), but considering that the interface of HfO2 has many defects, which may affect the stability of the device if directly contacting with the active layer or the gate metal, it may be considered to use SiOx or SiNx (SiNx only can be used as a contact film layer with the gate metal layer, and if it is used as a contact surface with IGZO, H remaining in the SiNx film layer during the film forming process may destroy IGZO characteristics) with a relatively good interface as a contact surface, such as a SiOx/HfO2/SiOx tri-layer structure as a GI insulating layer, wherein in order to ensure that the advantages of the high-K material are embodied, the thickness of HfO2 in the tri-layer structure needs to be relatively larger.
S3, plating a left active layer 41 and a right active layer 42 on the upper surface of the gate insulating layer 3, wherein the left active layer 41 and the right active layer 42 are positioned above the first metal layer;
the left active layer 41 and the right active layer 42 function as semiconductor layers, provide a carrier channel or close the carrier channel under the action of the voltage of the gate 2, are made of metal oxide semiconductors such as IGZO, and are subjected to PVD film forming and acid wet etching.
S4, plating a left etching barrier layer 30 on the upper surfaces of the gate insulating layer 3 and the left active layer 41, and plating a right etching barrier layer 40 on the upper surfaces of the gate insulating layer 3 and the right active layer 42;
the left etch stop layer 30 and the right etch stop layer 40 are used to prevent the metal oxide semiconductor (i.e., the left active layer and the right active layer) from being damaged by etching acid solution used in the subsequent ITO film process, and are made of SiOx, formed by CVD, and dry etched.
S5, plating a bridge layer 5 on the upper surface of the gate insulating layer 3, wherein the left end and the right end of the bridge layer 5 are respectively connected with the left active layer 41 and the right active layer 42;
plating a pixel electrode 8 on the upper surface of the right etching barrier layer 40, wherein the pixel electrode 8 is positioned at the side of the bridge layer 5;
the bridging layer 5 serves to connect the left and right active layers together, the pixel electrode 8 serves as an electrode for providing a liquid crystal molecular electric field, and the two active layers are made of ITO (indium tin oxide), so that films are formed together in a PVD (physical vapor deposition) mode, and wet etching is carried out by using acid liquid.
S6, forming a left via 301 in the left etching stop layer 30, exposing the left active layer 41 to the left via 301, forming a right via 401 in the right etching stop layer 40, and exposing the right active layer 42 to the right via 401;
the etch stop layer is dug by dry etching in order to provide small holes for the source 6 and drain 7 to be connected to the active layer.
S7, plating a second metal layer on the upper surface of the left etching barrier layer 30, wherein the second metal layer also penetrates through the left digging hole 301 to be connected with the left active layer 41 to form a source electrode 6;
plating a third metal layer on the upper surface of the right etching barrier layer 40, wherein the third metal layer further passes through the right cut hole 401 to be connected with the right active layer 42, and the third metal layer is further connected with the pixel electrode 8 to form a drain electrode 7;
plating a conductive layer 9 on the upper surface of the right etching barrier layer 40, wherein the conductive layer 9 is positioned at the side of the pixel electrode 8;
the source electrode 6, the drain electrode 7 and the conducting layer 9 are used for providing signals for the pixel electrode 8 and the common electrode 20, the film forming mode is a PVD magnetron sputtering film forming mode, the material can be any one of an MO single-layer structure, a Ti single-layer structure, an MO/AL/MO three-layer structure, a Ti/AL/Ti three-layer structure, an AL/MO two-layer structure and an AL/Ti two-layer structure, and the etching mode is acid liquid wet etching.
S8, plating a passivation layer 10 on the upper surfaces of the second metal layer, the third metal layer, the left etching barrier layer 30, the right etching barrier layer 40, the bridge layer 5, the pixel electrode 8 and the conductive layer 9, wherein the passivation layer 10 is provided with a through hole 101, and the conductive layer 9 is exposed out of the through hole 101;
the passivation layer 10 serves to protect the TFT device and serves as a capacitance medium between the pixel electrode 8 and the common electrode 20, and may be made of insulating material such as SiOx, siNO, or SiNx, and may be formed by CVD or dry etching. The purpose of punching holes in the conductive layer 9 is to transmit the signal of the conductive layer 9 to the common electrode 20.
And S9, plating a common electrode 20 on the upper surface of the passivation layer 10, wherein the common electrode 20 is also connected with the conductive layer 9 through the through hole 101.
The common electrode 20 serves as an electrode for providing an electric field for liquid crystal molecules, and is made of ITO, and is subjected to PVD film forming and acid wet etching.
With reference to fig. 11, in the present invention, the positions of the common electrode 20 and the pixel electrode 8 are interchangeable, that is:
a common electrode 20 fixedly disposed on an upper surface of the right etching stopper layer 40;
the conducting layer 9 is fixedly arranged on the upper surface of the right etching barrier layer 40 and is also connected with the common electrode 20;
the passivation layer 10 is fixedly arranged on the upper surfaces of the second metal layer, the third metal layer, the left etching barrier layer 30, the right etching barrier layer 40, the bridging layer 5, the common electrode 20 and the conducting layer 9, and the passivation layer 10 is provided with a through hole 101;
and a pixel electrode 8 fixedly disposed on the upper surface of the passivation layer 10 and connected to the third metal layer through the via hole 101.
Because the ITO material has good electric conductivity and non-light tight characteristics, the utility model discloses a material that TFT array substrate's bridging layer 5 and pixel electrode 8 chooseed for use all is the ITO, and the bridging layer 5 under this structure and pixel electrode 8's film forming are gone on at same process, can simplify array substrate's structure like this, improve the productivity, reduce cost.
Although specific embodiments of the invention have been described herein, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, as equivalent modifications and variations within the spirit of the invention are intended to be covered by the appended claims.
Claims (7)
1. A high-performance TFT array substrate having an etch stop layer, comprising:
a glass substrate;
the first metal layer is fixedly arranged on the upper surface of the glass substrate to form a grid;
the grid insulating layer is fixedly arranged on the upper surfaces of the first metal layer and the glass substrate;
the left active layer is fixedly arranged on the upper surface of the gate insulating layer and is also positioned above the left end of the first metal layer;
the right active layer is fixedly arranged on the upper surface of the gate insulating layer and is also positioned above the right end of the first metal layer;
the bridging layer is fixedly arranged on the upper surface of the gate insulating layer, and the left end and the right end of the bridging layer are respectively connected with the left active layer and the right active layer;
the left etching barrier layer is fixedly arranged on the upper surfaces of the gate insulating layer and the left active layer and is also provided with a left digging hole;
the right etching barrier layer is fixedly arranged on the upper surfaces of the gate insulating layer and the right active layer and is also provided with a right digging hole;
the second metal layer is fixedly arranged on the upper surface of the left etching barrier layer and is connected with the left active layer through the left digging hole to form a source electrode;
and the third metal layer is fixedly arranged on the upper surface of the right etching barrier layer and is also connected with the right active layer through the right digging hole to form a drain electrode.
2. The high-performance TFT array substrate with an etching stopper layer according to claim 1, further comprising:
the pixel electrode is fixedly arranged on the upper surface of the right etching barrier layer and is also connected with the third metal layer;
the conducting layer is fixedly arranged on the upper surface of the right etching barrier layer;
the passivation layer is fixedly arranged on the upper surfaces of the second metal layer, the third metal layer, the left etching barrier layer, the right etching barrier layer, the bridging layer, the pixel electrode and the conductive layer, and is provided with a through hole;
and the common electrode is fixedly arranged on the upper surface of the passivation layer and is also connected with the conductive layer through the through hole.
3. The high-performance TFT array substrate with an etching stopper layer according to claim 1, further comprising:
the common electrode is fixedly arranged on the upper surface of the right etching barrier layer;
the conducting layer is fixedly arranged on the upper surface of the right etching barrier layer and is also connected with the common electrode;
the passivation layer is fixedly arranged on the upper surfaces of the second metal layer, the third metal layer, the left etching barrier layer, the right etching barrier layer, the bridging layer, the common electrode and the conducting layer, and is provided with a through hole;
and the pixel electrode is fixedly arranged on the upper surface of the passivation layer and is also connected with the third metal layer through the through hole.
4. The high-performance TFT array substrate of claim 2, wherein the first metal layer, the second metal layer, the third metal layer, and the conductive layer are any one of MO single layer structure, ti single layer structure, MO/AL/MO triple layer structure, ti/AL/Ti triple layer structure, AL/MO double layer structure, and AL/Ti double layer structure.
5. The high-performance TFT array substrate with the etching stop layer as claimed in claim 2, wherein the left and right active layers are IGZO material, the left and right etching stop layers are SiOx material, and the bridge layer, the pixel electrode and the common electrode are ITO material.
6. The high-performance TFT array substrate with an etch stopper of claim 2, wherein the gate insulating layer is a SiOx single layer structure or a SiNx/SiOx double layer structure, and the passivation layer is made of SiOx or SiNO or SiNx material.
7. The high-performance TFT array substrate with the etching barrier layer according to claim 2, wherein the left cut, the right cut and the through hole are all in an inverted cone shape.
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