CN218632046U

CN218632046U - High-performance TFT array substrate with active layer bridging block

Info

Publication number: CN218632046U
Application number: CN202222984131.0U
Authority: CN
Inventors: 毛清平
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2022-11-09
Filing date: 2022-11-09
Publication date: 2023-03-14
Anticipated expiration: 2032-11-09

Abstract

The utility model relates to a liquid crystal display technical field provides a high performance TFT array substrate with active layer bridging piece, include: a glass substrate; a first metal layer forming a gate; the grid insulating layer is fixedly arranged on the upper surfaces of the first metal layer and the glass substrate; a left active layer, a right active layer; the left end and the right end of the bridging layer are respectively connected with the left active layer and the right active layer; the left etching barrier layer is fixedly arranged on the upper surfaces of the gate insulating layer and the left active layer and is also provided with a left digging hole; the right etching barrier layer is fixedly arranged on the upper surfaces of the gate insulating layer and the right active layer and is also provided with a right digging hole; the left bridging block is fixedly arranged in the left digging hole; and the right bridging block is fixedly arranged in the right digging hole. The utility model has the advantages that: under the prerequisite of the source electrode drain electrode distance of not shortening the TFT device, shorten active layer channel length, the utility model discloses a TFT array substrate has advantages such as the reaction is fast, the on-state current is big, threshold voltage is little.

Description

High-performance TFT array substrate with active layer bridging block

Technical Field

The utility model relates to a liquid crystal display technical field specifically relates to a high performance TFT array substrate with active layer bridging piece.

Background

With the rapid development of artificial intelligence, the technology of the TFT-LCD liquid crystal screen is continuously improved, and the TFT-LCD liquid crystal screen has high definition, high speed, low power consumption and the like and becomes the development trend of the TFT-LCD liquid crystal screen.

In order to realize a high-performance display screen, one of the current manufacturers is to realize miniaturization of a TFT device by shortening the channel length of an active layer of the TFT device, and the shortening of the channel length of the active layer can realize a large on-state current, improve the response speed of the device, reduce the threshold voltage, and the like. However, in practice, the design of the channel length of the active layer is limited to the distance between the source and drain electrodes of the TFT device, and mainly takes into consideration the risk of short circuit and the like when the source and drain electrodes are too close to each other. Through technological development for many years, the source-drain spacing of the current Thin Film Transistor (TFT) is selected to be a safe minimum distance, which is generally controlled to be 5-6 μm.

Referring to fig. 1, a schematic structural diagram of a conventional TFT device is shown. The active layer is a semiconductor, and the active layer channel length refers to the length of the semiconductor between the source and the drain.

Therefore, how to shorten the channel length of the active layer without shortening the distance between the source and the drain of the TFT device is a technical problem to be solved in the art.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model lies in providing a high performance TFT array substrate with active layer bridging piece, under the prerequisite of the source drain electrode distance of not shortening the TFT device, shortens active layer channel length.

The utility model discloses a realize like this: a high performance TFT array substrate having an active layer bridging block, comprising:

a glass substrate;

the first metal layer is fixedly arranged on the upper surface of the glass substrate to form a grid;

the grid insulating layer is fixedly arranged on the upper surfaces of the first metal layer and the glass substrate;

the left active layer is fixedly arranged on the upper surface of the gate insulating layer and is also positioned above the left end of the first metal layer;

the right active layer is fixedly arranged on the upper surface of the gate insulating layer and is also positioned above the right end of the first metal layer;

the bridging layer is fixedly arranged on the upper surface of the gate insulating layer, and the left end and the right end of the bridging layer are respectively connected with the left active layer and the right active layer;

the left etching barrier layer is fixedly arranged on the upper surfaces of the gate insulating layer and the left active layer and is also provided with a left digging hole;

the right etching barrier layer is fixedly arranged on the upper surfaces of the gate insulating layer and the right active layer and is also provided with a right digging hole;

the left bridging block is fixedly arranged in the left digging hole;

the right bridging block is fixedly arranged in the right digging hole;

the second metal layer is fixedly arranged on the upper surface of the left etching barrier layer and is connected with the left active layer through a left bridging block to form a source electrode;

the third metal layer is fixedly arranged on the upper surface of the right etching barrier layer and is connected with the right active layer through a right bridging block to form a drain electrode;

the left bridging block, the right bridging block and the bridging layer are made of the same material.

Further, still include:

the pixel electrode is fixedly arranged on the upper surface of the right etching barrier layer and is also connected with the third metal layer;

the conducting layer is fixedly arranged on the upper surface of the right etching barrier layer;

the passivation layer is fixedly arranged on the upper surfaces of the second metal layer, the third metal layer, the left etching barrier layer, the right etching barrier layer, the bridging layer, the pixel electrode and the conductive layer, and is provided with a through hole;

and the common electrode is fixedly arranged on the upper surface of the passivation layer and is also connected with the conductive layer through the through hole.

Further, still include:

the common electrode is fixedly arranged on the upper surface of the right etching barrier layer;

the conducting layer is fixedly arranged on the upper surface of the right etching barrier layer and is also connected with the common electrode;

the passivation layer is fixedly arranged on the upper surfaces of the second metal layer, the third metal layer, the left etching barrier layer, the right etching barrier layer, the bridging layer, the common electrode and the conducting layer, and is provided with a through hole;

and the pixel electrode is fixedly arranged on the upper surface of the passivation layer and is also connected with the third metal layer through the through hole.

Further, the first metal layer, the second metal layer, the third metal layer and the conductive layer are any one of an MO single-layer structure, a Ti single-layer structure, an MO/AL/MO three-layer structure, a Ti/AL/Ti three-layer structure, an AL/MO two-layer structure and an AL/Ti two-layer structure.

Furthermore, the left active layer and the right active layer are both made of IGZO materials, the left etching blocking layer and the right etching blocking layer are both made of SiOx materials, and the bridging layer, the pixel electrode, the left bridging block, the right bridging block and the common electrode are all made of ITO materials.

Further, the gate insulating layer is of a SiOx single-layer structure or a SiNx/SiOx double-layer structure, and the passivation layer is made of SiOx, siNO or SiNx.

Furthermore, the left dug hole, the right dug hole and the through hole are all inverted cones.

The utility model has the advantages that: 1. the difference with traditional TFT device lies in, the utility model discloses a replace one section in the middle of the active layer with a bridging layer, the bridging layer is the conductor, the active layer is the semiconductor to holistic active layer channel length has just shortened, but the distance between source electrode and the drain electrode still remains unchanged this moment, has guaranteed the security of device; under the prerequisite of the source electrode drain electrode distance of not shortening the TFT device promptly, shorten active layer channel length, the utility model discloses a TFT array substrate has advantages such as the reaction is fast, the on-state current is big, threshold voltage is little, improves the performance of display screen behind the practical application. 2. The left etching barrier layer and the right etching barrier layer are used for preventing etching acid liquor used in the next ITO film layer process from damaging the left active layer and the right active layer. 3. The left bridging block, the right bridging block and the bridging layer are made of the same materials, when the process of plating the bridging layer between the two active layers is carried out, the left bridging block is plated on a reserved left digging hole, the right bridging block is plated on a reserved right digging hole, the process is carried out in the same process, the productivity is improved, and the cost is reduced. 4. Because the ITO material has good electric conductivity and non-light tight characteristics, the utility model discloses a material that bridging layer, left bridging piece, right bridging piece and the pixel electrode of TFT device chose for use all is the ITO, and bridging layer, left bridging piece, right bridging piece and the pixel electrode film forming under this structure are gone on at same process, just so simplify array substrate's structure, improve the productivity, reduce cost.

Drawings

The present invention will be further described with reference to the following examples and drawings.

Fig. 1 is a schematic structural view of a conventional TFT device in the background art.

Fig. 2 is a first flowchart illustrating a manufacturing process of a high-performance TFT array substrate with an active layer bridging block according to the present invention.

Fig. 3 is a second flowchart illustrating the manufacturing process of the high-performance TFT array substrate with the active layer bridging block according to the present invention.

Fig. 4 is a third flow chart of the manufacturing process of the high-performance TFT array substrate with the active layer bridging block of the present invention.

Fig. 5 is a fourth flowchart illustrating the manufacturing process of the high-performance TFT array substrate with the active layer bridging block according to the present invention.

Fig. 6 is a fifth flowchart illustrating a manufacturing process of the high-performance TFT array substrate with the active layer bridging block according to the present invention.

Fig. 7 is a sixth flowchart illustrating a manufacturing process of the high-performance TFT array substrate with the active layer bridging block according to the present invention.

Fig. 8 is a seventh flowchart illustrating a manufacturing process of the high-performance TFT array substrate with the active layer bridging block according to the present invention.

Fig. 9 is a manufacturing flowchart eight of the high-performance TFT array substrate with the active layer bridging block of the present invention.

Fig. 10 is a schematic diagram illustrating positions of the pixel electrode and the common electrode in fig. 9 being interchanged.

Reference numerals: a glass substrate 1; a gate electrode 2; a gate insulating layer 3; an active layer 4; a left active layer 41; a right active layer 42; a bridging layer 5; a source electrode 6; a drain electrode 7; a pixel electrode 8; a conductive layer 9; a passivation layer 10; a through hole 101; a common electrode 20; a left etch stop layer 30; digging a hole 301 on the left; a right etch stop layer 40; a right dug hole 401; a left bridge block 50; and a right bridge block 60.

Detailed Description

The embodiment of the utility model provides a through providing a high performance TFT array substrate with active layer bridging piece, solved the design of active layer channel length among the background art and restricted to the distance between TFT device source drain, when source drain interval is at safe minimum distance, if continue to shorten source drain interval, the shortcoming of source drain short circuit can appear; realized not shortening under the prerequisite of the source electrode drain electrode distance of TFT device, shortening active layer channel length, the utility model discloses a TFT device that array substrate carried on has advantages such as the reaction is fast, the on-state current is big, threshold voltage is little, improves the performance of display screen behind the practical application.

The embodiment of the utility model provides an in technical scheme for solving above-mentioned shortcoming, the general thinking is as follows:

the difference with the traditional TFT device lies in that the utility model discloses a TFT device has replaced one section in the middle of the active layer with a bridging layer, and the bridging layer is the conductor, and the active layer is the semiconductor to holistic active layer channel length has just shortened, promptly the length of semiconductor shortens, but the distance between source electrode and the drain electrode still remains unchanged this moment, has guaranteed the security of device; the length of the active layer channel is shortened on the premise of not shortening the distance between the source electrode and the drain electrode of the TFT device.

Before the bridging layer is plated, a left etching barrier layer and a right etching barrier layer are plated on the left active layer and the right active layer, and the left etching barrier layer and the right etching barrier layer are used for preventing etching acid liquor used in a subsequent ITO film layer process from damaging the left active layer and the right active layer.

The left bridging block, the right bridging block and the bridging layer are made of the same materials, when the process of plating the bridging layer between the two active layers is carried out, the left bridging block is plated on a reserved left digging hole, the right bridging block is plated on a reserved right digging hole, the process is carried out in the same process, the productivity is improved, and the cost is reduced.

The effect of the active layer channel length on the gate characteristics of Thin Film Transistors (TFTs) is significant, and the general trend is: the shorter the channel, the greater the on-current, and the longer the channel, the smaller the on-current. This is due to the fact that as the channel length increases, the probability of carriers being trapped in the drift increases, and the decrease in carrier density causes the threshold voltage to increase, which also causes the source-drain current I _DS The growth becomes slow, which causes the subthreshold swing to increase, i.e. the response speed of the device will decrease.

For better understanding of the above technical solutions, the following detailed descriptions will be provided in conjunction with the drawings and the detailed description of the embodiments.

Referring to fig. 1 to 10, the preferred embodiment of the present invention.

Referring to fig. 9, a high performance TFT array substrate having an active layer bridging block includes:

a glass substrate 1;

the first metal layer is fixedly arranged on the upper surface of the glass substrate 1 to form a grid 2;

the gate insulating layer 3 is fixedly arranged on the first metal layer and the upper surface of the glass substrate 1;

the left active layer 41 is fixedly arranged on the upper surface of the gate insulating layer 3 and is also positioned above the left end of the first metal layer;

a right active layer 42 fixedly disposed on the upper surface of the gate insulating layer 3 and located above the right end of the first metal layer;

the bridging layer 5 is fixedly arranged on the upper surface of the gate insulating layer 3, and the left end and the right end of the bridging layer are respectively connected with the left active layer 41 and the right active layer 42;

the left etching barrier layer 30 is fixedly arranged on the upper surfaces of the gate insulating layer 3 and the left active layer 41, and is also provided with a left dug hole 301;

the right etching barrier layer 40 is fixedly arranged on the upper surfaces of the gate insulating layer 3 and the right active layer 42 and is also provided with a right digging hole 401;

the left bridging block 50 is fixedly arranged in the left digging hole 301;

the right bridge block 60 is fixedly arranged in the right digging hole 401;

the second metal layer is fixedly arranged on the upper surface of the left etching barrier layer 30 and is connected with the left active layer 41 through a left bridging block 50 to form a source electrode 6;

a third metal layer fixedly disposed on the upper surface of the right etching stop layer 40, and connected to the right active layer 42 through a right bridge block 60 to form a drain electrode 7;

the left bridging block 50, the right bridging block 60 and the bridging layer 5 are all made of the same material.

The difference with traditional TFT device lies in, the utility model discloses a TFT device has replaced one section in the middle of the active layer with a bridging layer 5, and bridging layer 5 is the conductor, and left active layer 41 and right active layer 42 are all semiconductors to holistic active layer channel length has just been shortened, and the length of semiconductor shortens promptly, but the distance between source electrode 6 and drain electrode 7 still remains unchanged this moment, has guaranteed the security of device; under the prerequisite of the source electrode 6 drain electrode 7 distance of TFT device that does not shorten promptly, shorten active layer channel length, the utility model discloses a TFT array substrate has advantages such as the reaction is fast, the on-state current is big, threshold voltage is little, improves the performance of display screen behind the practical application.

Further comprising: a pixel electrode 8 fixedly disposed on the upper surface of the right etching stop layer 40 and connected to the third metal layer;

the conductive layer 9 is fixedly arranged on the upper surface of the right etching barrier layer 40;

the passivation layer 10 is fixedly arranged on the upper surfaces of the second metal layer, the third metal layer, the left etching barrier layer 30, the right etching barrier layer 40, the bridging layer 5, the pixel electrode 8 and the conductive layer 9, and the passivation layer 10 is provided with a through hole 101;

and the common electrode 20 is fixedly arranged on the upper surface of the passivation layer 10 and is also connected with the conductive layer 9 through the through hole 101.

The first metal layer (grid 2), the second metal layer (source 6), the third metal layer (drain 7) and the conducting layer 9 are any one of an MO single-layer structure, a Ti single-layer structure, an MO/AL/MO three-layer structure, a Ti/AL/Ti three-layer structure, an AL/MO double-layer structure and an AL/Ti double-layer structure.

The left active layer 41 and the right active layer 42 are IGZO materials, the left etching stopper layer 30 and the right etching stopper layer 40 are SiOx materials, and the bridge layer 5, the pixel electrode 8, the left bridge block 50, the right bridge block 60, and the common electrode 20 are ITO materials.

The gate insulating layer 3 is a SiOx single-layer structure or a SiNx/SiOx double-layer structure, and the passivation layer 10 is made of SiOx, siNO or SiNx material.

The left dug hole 301, the right dug hole 401 and the through hole 101 are all in inverted cone shapes. The deposition of the material is convenient to fix at the hole position.

With reference to fig. 2 to 9, the method for manufacturing a high performance TFT array substrate with an active layer bridging block of the present embodiment includes the following steps:

s1, plating a first metal layer on the upper surface of a glass substrate 1 to form a grid 2;

the grid electrode 2 is used for transmitting a signal of the grid electrode 2 so as to open and close the TFT device, the material can be any one of an MO single-layer structure, a Ti single-layer structure, an MO/AL/MO three-layer structure, a Ti/AL/Ti three-layer structure, an AL/MO double-layer structure and an AL/Ti double-layer structure, and PVD film forming and acid wet etching are adopted.

S2, plating a gate insulating layer 3 on the first metal layer and the upper surface of the glass substrate 1;

the gate insulating layer 3 serves as an insulating medium and a capacitance medium between the gate 2 and the active layer, and is formed by CVD (chemical vapor deposition) and dry etching by using a SiOx single-layer structure or a SiNx/SiOx double-layer structure.

Considering that the requirements of the TFT device are fast response and low power consumption, which are achieved by shrinking the TFT device, and in order to achieve the miniaturization of the device, it is necessary to select a suitable high-K material (such as HfO 2), but considering that the interface of HfO2 has many defects, which may affect the stability of the device if directly contacting with the active layer or the gate metal, it may be considered to use SiOx or SiNx (SiNx only can be used as a contact film layer with the gate metal layer, and if it is used as a contact surface with IGZO, H remaining in the SiNx film layer during the film forming process may destroy IGZO characteristics) with a relatively good interface as a contact surface, such as a SiOx/HfO2/SiOx tri-layer structure as a GI insulating layer, wherein in order to ensure that the advantages of the high-K material are embodied, the thickness of HfO2 in the tri-layer structure needs to be relatively larger.

S3, plating a left active layer 41 and a right active layer 42 on the upper surface of the gate insulating layer 3, wherein the left active layer 41 and the right active layer 42 are positioned above the first metal layer;

the left active layer 41 and the right active layer 42 function as semiconductor layers, provide a carrier channel or close the carrier channel under the action of the voltage of the gate 2, are made of metal oxide semiconductors such as IGZO, and are subjected to PVD film forming and acid wet etching.

S4, plating a left etching barrier layer 30 on the upper surfaces of the gate insulating layer 3 and the left active layer 41, wherein a left digging hole 301 is formed in the left etching barrier layer 30, and the left active layer 41 is exposed out of the left digging hole 301;

plating a right etching barrier layer 40 on the upper surfaces of the gate insulating layer 3 and the right active layer 42, wherein the right etching barrier layer 40 is provided with a right dug hole 401, and the right active layer 42 is exposed out of the right dug hole 401;

the left etch stop layer 30 and the right etch stop layer 40 are used to prevent the metal oxide semiconductor (i.e., the left active layer and the right active layer) from being damaged by etching acid solution used in the subsequent ITO film process, and are made of SiOx, formed by CVD, and dry etched.

S5, plating a bridge layer 5 on the upper surface of the gate insulating layer 3, wherein the left end and the right end of the bridge layer 5 are respectively connected with the left active layer 41 and the right active layer 42;

plating a pixel electrode 8 on the upper surface of the right etching barrier layer 40, wherein the pixel electrode 8 is positioned at the side of the bridge layer 5;

plating a left bridging block 50 in the left dug hole 301, wherein the left bridging block 50 is further connected with the left active layer 41;

plating a right bridge block 60 in the right cutout hole 401, the right bridge block 60 further connected to the right active layer 42;

the bridging layer 5 is used for connecting the left and right active layers together, the pixel electrode 8 is used as an electrode for providing a liquid crystal molecular electric field, the left bridging block 50 is used for connecting the source electrode 6 and the left active layer 41, the right bridging block 60 is used for connecting the drain electrode 7 and the right active layer 42, and the four materials are all ITO, so that the film is formed together by a PVD (physical vapor deposition) method, and the acid liquid is used for wet etching.

S6, plating a second metal layer on the upper surface of the left etching barrier layer 30, wherein the second metal layer is further connected with the left bridging block 50 to form a source electrode 6;

plating a third metal layer on the upper surface of the right etching barrier layer 40, wherein the third metal layer is further connected with the right bridge block 60 and the pixel electrode 8 to form a drain electrode 7;

plating a conductive layer 9 on the upper surface of the right etching barrier layer 40, wherein the conductive layer 9 is located at the side of the pixel electrode 8;

the source electrode 6, the drain electrode 7 and the conducting layer 9 are used for providing signals for the pixel electrode 8 and the common electrode 20, the film forming mode is a PVD magnetron sputtering film forming mode, the material can be any one of an MO single-layer structure, a Ti single-layer structure, an MO/AL/MO three-layer structure, a Ti/AL/Ti three-layer structure, an AL/MO two-layer structure and an AL/Ti two-layer structure, and the etching mode is acid liquid wet etching.

S7, plating a passivation layer 10 on the upper surfaces of the second metal layer, the third metal layer, the left etching barrier layer 30, the right etching barrier layer 40, the bridge layer 5, the pixel electrode 8 and the conductive layer 9, wherein the passivation layer 10 is provided with a through hole 101, and the conductive layer 9 is exposed out of the through hole 101;

the passivation layer 10 serves to protect the TFT device and serves as a capacitance medium between the pixel electrode 8 and the common electrode 20, and may be made of insulating material such as SiOx, siNO, or SiNx, and may be formed by CVD or dry etching. The purpose of punching holes in the conductive layer 9 is to transmit the signal of the conductive layer 9 to the common electrode 20.

And S8, plating a common electrode 20 on the upper surface of the passivation layer 10, wherein the common electrode 20 is also connected with the conductive layer 9 through the through hole 101.

The common electrode 20 serves as an electrode for providing an electric field for liquid crystal molecules, and is made of ITO, and is subjected to PVD film forming and acid wet etching.

Referring to fig. 10, in the embodiment, the positions of the common electrode 20 and the pixel electrode 8 are interchangeable, that is:

a common electrode 20 fixedly disposed on an upper surface of the right etching stopper layer 40;

the conducting layer 9 is fixedly arranged on the upper surface of the right etching barrier layer 40 and is also connected with the common electrode 20;

the passivation layer 10 is fixedly arranged on the upper surfaces of the second metal layer, the third metal layer, the left etching barrier layer 30, the right etching barrier layer 40, the bridging layer 5, the common electrode 20 and the conducting layer 9, and the passivation layer 10 is provided with a through hole 101;

and the pixel electrode 8 is fixedly arranged on the upper surface of the passivation layer 10 and is also connected with the third metal layer through the through hole 101.

Because the ITO material has good electric conductivity and non-light tight characteristics, the utility model discloses a material that TFT array substrate's bridging layer 5, left bridging piece 50, right bridging piece 60 and pixel electrode 8 chooseed for use all is the ITO, and the bridging layer 5, left bridging piece 50, right bridging piece 60 and pixel electrode 8's under this structure film-forming is gone on at same process, can simplify array substrate's structure like this, improves the productivity, reduce cost.

Although specific embodiments of the present invention have been described, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the claims appended hereto.

Claims

1. A high performance TFT array substrate having an active layer bridging block, comprising:

a glass substrate;

the left bridging block is fixedly arranged in the left digging hole;

the right bridging block is fixedly arranged in the right digging hole;

2. The high-performance TFT array substrate with the active layer bridging block according to claim 1, further comprising:

3. The high-performance TFT array substrate with the active layer bridging block according to claim 1, further comprising:

and the pixel electrode is fixedly arranged on the upper surface of the passivation layer and is connected with the third metal layer through the through hole.

4. The high-performance TFT array substrate with active layer bridging blocks according to claim 2, wherein the first metal layer, the second metal layer, the third metal layer and the conductive layer are any one of MO single layer structure, ti single layer structure, MO/AL/MO triple layer structure, ti/AL/Ti triple layer structure, AL/MO double layer structure and AL/Ti double layer structure.

5. The substrate of claim 2, wherein the left active layer and the right active layer are both IGZO material, the left etching stop layer and the right etching stop layer are both SiOx material, and the bridge layer, the pixel electrode, the left bridge block, the right bridge block and the common electrode are all ITO material.

6. The high-performance TFT array substrate having an active layer bridging block as set forth in claim 2, wherein the gate insulating layer has a single-layer structure of SiOx or a double-layer structure of SiNx/SiOx, and the passivation layer is made of SiOx or SiNO or SiNx.

7. The high-performance TFT array substrate with the active layer bridge block as claimed in claim 2, wherein the left dug hole, the right dug hole and the through hole are all reverse tapered.