CN218498823U - Anti-reverse-connection circuit with ultra-low static power consumption - Google Patents
Anti-reverse-connection circuit with ultra-low static power consumption Download PDFInfo
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- CN218498823U CN218498823U CN202222184223.0U CN202222184223U CN218498823U CN 218498823 U CN218498823 U CN 218498823U CN 202222184223 U CN202222184223 U CN 202222184223U CN 218498823 U CN218498823 U CN 218498823U
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Abstract
The application provides an anti-reverse connection circuit with ultra-low static power consumption, which comprises an anti-reverse connection circuit and a circuit for reducing static current, wherein the anti-reverse connection circuit comprises a P-type field effect tube, a first resistor and an overvoltage protection circuit, the drain electrode of the P-type field effect tube is respectively connected with the positive electrode of a power supply and one end of the first resistor, the source electrode of the P-type field effect tube is respectively connected with one end of the overvoltage protection circuit, the negative electrode of the power supply and one end of a load, and the grid electrode of the P-type field effect tube is respectively connected with the other end of the overvoltage protection circuit, the other end of the first resistor and one end of a current limiting element; the static current reducing circuit comprises an NPN type triode, wherein the base electrode of the NPN type triode is connected with the general input and output interface, the emitting electrode of the NPN type triode is grounded, and the collecting electrode of the NPN type triode is connected with the other end of the current limiting element. According to the application, the ultralow static current consumption can be realized under the condition of realizing the application of reverse connection prevention of the large current with the load.
Description
Technical Field
The application relates to the technical field of protection circuits, in particular to an ultralow static power consumption reverse connection prevention circuit.
Background
With the development of automotive electronics, vehicle-mounted systems become more and more complex, so that hundreds of loads need to be powered by batteries at the same time, and the working states of the loads are different at the same time. Therefore, when designing the power supply of the electronic product of the automobile, the reverse connection of the circuit can be caused when a plurality of loads are under different working conditions and under various potential fault states. Therefore, an anti-reverse connection circuit is usually connected to the circuit, but in the anti-reverse connection circuit in the conventional technology, the power consumption of the circuit is large due to the large static circuit. Therefore, there is a need to solve the above problems.
SUMMERY OF THE UTILITY MODEL
The present application is proposed to solve the above problems. According to an aspect of the present application, there is provided an ultra-low static power anti-reverse connection circuit including an anti-reverse connection circuit and a reduced static current circuit,
the reverse connection preventing circuit comprises a P-type field effect transistor, a first resistor and an overvoltage protection circuit, wherein a drain electrode of the P-type field effect transistor is respectively connected with an anode of a power supply and one end of the first resistor, a source electrode of the P-type field effect transistor is respectively connected with one end of the overvoltage protection circuit, a cathode of the power supply and one end of a load, and a grid electrode of the P-type field effect transistor is respectively connected with the other end of the overvoltage protection circuit, the other end of the first resistor and one end of a current limiting element;
the static current reducing circuit comprises an NPN type triode, wherein the base electrode of the NPN type triode is connected with a general input/output interface, the emitting electrode of the NPN type triode is grounded, and the collecting electrode of the NPN type triode is connected with the other end of the current limiting element.
In one embodiment of the present application, the overvoltage protection circuit includes a zener diode and a capacitor connected in parallel, wherein an anode of the zener diode and one end of the capacitor are both connected to the gate of the pfet, and the anode of the zener diode and one end of the capacitor are also connected to one end of the current limiting element; and the cathode of the voltage stabilizing diode and the other end of the capacitor are both connected with the source electrode of the P-type field effect transistor.
In one embodiment of the present application, the current limiting element includes a second resistor.
In one embodiment of the present application, the second resistor has a resistance value at least 5 times greater than that of the first resistor.
In one embodiment of the present application, the first resistor has a resistance of 10K ohms.
In one embodiment of the present application, the second resistor has a resistance of 2K ohms.
In one embodiment of the present application, the gate-source threshold voltage of the PFET is not greater than 20V.
In one embodiment of the present application, the gate-source threshold voltage of the PFET is 18V.
In one embodiment of the present application, the power supply is a dc power supply.
In one embodiment of the present application, the source of the pfet includes 5 pins.
According to the ultralow static power consumption reverse connection prevention circuit, the reverse connection prevention circuit is grounded through the static current reduction circuit, the situation that an overvoltage protection circuit and a current limiting element cannot form a loop under the condition that a triode in the static current circuit is not conducted is reduced, and the ultralow static power consumption reverse connection prevention circuit is free of static current consumption, so that the ultralow static current consumption can be realized under the application condition that reverse connection prevention load high current is realized.
Drawings
The above and other objects, features and advantages of the present application will become more apparent by describing in more detail embodiments of the present application with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings, like reference numbers generally indicate like parts or steps.
Fig. 1 shows a schematic diagram of an ultra-low static power consumption anti-reverse connection circuit according to an embodiment of the application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, exemplary embodiments according to the present application will be described in detail below with reference to the accompanying drawings. It should be understood that the described embodiments are only some embodiments of the present application and not all embodiments of the present application, and that the present application is not limited by the example embodiments described herein. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the application described in the application without inventive step, shall fall within the scope of protection of the application.
In the conventional technology, in order to prevent the circuit from being damaged due to the reverse connection of the power supply, a P-type Field Effect Transistor (MOSFET), referred to as PMOS for short, may be connected in series on the high side. When the power supply is reversely connected, the PMOS channel is closed, the function of reverse connection prevention is realized by using the parasitic body diode, the reverse connection prevention circuit can be used for the design of a reverse connection prevention circuit of a large-current power supply, and the reverse connection prevention circuit has the advantages that the driving circuit is simple, but the driving circuit causes larger static current.
In another scheme, a Schottky diode can be connected in series in the circuit in order to reduce the static current in the circuit while achieving the purpose of reverse connection prevention. The method has the advantages of simplicity and low cost, and can reduce the quiescent current in the circuit. However, the loss caused by the method is large, and the method is only suitable for the design of the low-current power supply reverse-connection preventing circuit with the current not exceeding 2-3A.
Therefore, the above two schemes can not better reduce the static current consumption while realizing the function of preventing the reverse connection of the power supply.
Based on the foregoing technical problem, the present application provides an anti-reverse connection circuit with ultra-low static power consumption, the circuit includes an anti-reverse connection circuit and a circuit for reducing static current: the reverse connection preventing circuit comprises a P-type field effect transistor, a first resistor and an overvoltage protection circuit, wherein a drain electrode of the P-type field effect transistor is respectively connected with an anode of a power supply and one end of the first resistor, a source electrode of the P-type field effect transistor is respectively connected with one end of the overvoltage protection circuit, a cathode of the power supply and one end of a load, and a grid electrode of the P-type field effect transistor is respectively connected with the other end of the overvoltage protection circuit, the other end of the first resistor and one end of a current limiting element; the static current reducing circuit comprises an NPN type triode, wherein the base electrode of the NPN type triode is connected with a general input and output interface, the emitting electrode of the NPN type triode is grounded, and the collecting electrode of the NPN type triode is connected with the other end of the current limiting element. The anti-reverse-connection circuit reduces the grounding of the static current circuit, and reduces the phenomenon that an overvoltage protection circuit and a current-limiting element cannot form a loop under the condition that a triode in the static current circuit is not conducted, so that the ultra-low static power consumption anti-reverse-connection circuit has no static current consumption, and the ultra-low static power consumption is realized under the condition that the ultra-low static power consumption anti-reverse-connection circuit is powered off.
The scheme of the ultra-low static power consumption anti-reverse connection circuit according to the embodiment of the application is described in detail in the following with reference to the accompanying drawings. The features of the various embodiments of the present application may be combined with each other without conflict.
FIG. 1 shows a schematic diagram of an ultra-low static power anti-reverse connection circuit according to an embodiment of the application; as shown in fig. 1, the ultra-low static power consumption anti-reverse connection circuit 100 according to the embodiment of the present application may include an anti-reverse connection circuit 101 and a reduced static current circuit 102:
wherein the reverse connection preventing circuit 101 comprises a PMOS Q 1 A first resistor R 1 And the drain electrode of the PMOS is respectively connected with the anode BATT of a power supply and the first resistor R 1 A source of the PMOS is connected to one end of the overvoltage protection circuit, a negative terminal VOUT of the power supply, and one end of a load (not shown), and a gate of the PMOS is connected to the other end of the overvoltage protection circuit, the first resistor R, and the second resistor R, respectively 1 And one end of the current limiting element.
In one example, the overvoltage protection circuit includes a zener diode D connected in parallel 1 And a capacitor C 1 Wherein the voltage stabilizing diode D 1 And said capacitor C 1 One end of the voltage stabilizing diode D is connected with the grid electrode of the PMOS 1 And said capacitor C 1 One end of the current limiting element is also connected with one end of the current limiting element; the voltage stabilizing diode D 1 And said capacitor C 1 And the other ends of the two PMOS transistors are connected with the source electrode of the PMOS.
In one example, the gate-source threshold voltage V of the PMOS gs Not greater than 20 volts.
In a specific example, the gate-source threshold voltage V of the PMOS is gs Is 18 volts.
In one example, the power supply is a direct current power supply.
In one example, the PMOS includes 7 pins for connecting other parts of the circuit, wherein the source of the PMOS includes 5 pins, as shown by pins 2, 3, 5, 6, and 7, for connecting the negative terminal of the power supply, one terminal of the load, and one terminal of the overvoltage protection circuit. And the pin 1 is used as the grid electrode of the PMOS and is connected with the other end of the overvoltage protection circuit, and the pin 4 is used as the drain electrode of the PMOS and is connected with the anode of the power supply.
In an embodiment of the present application, the static current reducing circuit 102 includes an NPN transistor Q 2 Wherein, the NPN type triode Q 2 The base electrode of the NPN type triode is connected with a general input/output interface MCU _ IO and the NPN type triode Q 2 The emitting electrode of the NPN type triode Q is grounded, and the NPN type triode Q 2 Is connected to the other end of the current limiting element.
In an embodiment of the application, the current limiting element comprises a second resistor R 2 。
The second resistor R 2 Is at least the first resistor R 1 Resistance value is 5 times.
In a specific example, the first resistor has a resistance of 10K ohms.
In a specific example, the second resistor has a resistance of 2K ohms.
With continuing reference to fig. 1, the present application adds an NPN transistor Q to the gate (G-pole) of the PMOS 2 Moreover, the power supply reverse connection circuit can be well controlled to enter an ultra-low static current mode through logic software of a GPIO (MCU _ IO) portThe design of preventing reverse connection of the power supply of the large-current circuit and the design of reducing the static current are effectively realized.
The working principle of the ultralow static power consumption anti-reverse connection circuit is that when the GPIO port is connected with a high level, the NPN type triode is controlled to be conducted, so that the G pole of the PMOS is connected with the second resistor R through the second resistor R 2 Grounding; when the drain (D pole) of the PMOS is used as an input end to connect a forward voltage, current flows through a body diode of the PMOS to a load end, and when the forward voltage is higher than the threshold voltage (Vgs) of the PMOS, the PMOS conducts a channel. V after conduction due to small internal resistance of PMOS ds The voltage drop is very small, so that the power supply to a heavy-current load is realized under the condition of low loss.
When the D pole of the PMOS is used as an input end to be connected with a negative voltage, the current cannot flow through the PMOS body diode, the PMOS cannot conduct, and therefore the current is prevented from flowing to a load when the voltage is reversely connected.
To prevent the gate source V from fluctuating when the power supply fluctuates gs Over-voltage occurs to break down PMOS, and a voltage stabilizing diode D is connected between the grid (G pole) and the source (S pole) 1 And a capacitor C 1 。R 2 Is D 1 Current limiting resistor, current limiting resistor R 2 The resistance should not be too large. This is because: on one hand, the normal clamping current of the common voltage stabilizing tube is basically mA level, if the current limiting resistor is overlarge, the voltage stabilizing tube cannot be reliably conducted, and therefore V can be enabled gs There is a risk of overpressure; on the other hand, the larger the current limiting resistor is, the smaller the driving current of the PMOS is, the slower the on and off time of the PMOS is, and when voltage fluctuation exists in the input, the PMOS may be in a linear region for a long time, resulting in over-temperature of the PMOS.
Therefore, due to the current limiting resistor R 2 The resistance value of the circuit can not be overlarge, the static current of the anti-reverse-connection circuit with ultra-low static power consumption can be very large, and the application adds the triode Q 2 At Q 2 In the case of non-conduction, D 1 、R 2 And a loop cannot be formed, namely no static current is consumed, and ultra-low static power consumption is realized under the condition of system power failure.
According to the ultralow static power consumption reverse-connection-prevention circuit, the reverse connection prevention of the circuit is realized by arranging the PMOS, and a large-current load can be loaded. And, through setting up and reducing quiescent current circuit, realize ultra-low quiescent current consumption. Therefore, the ultra-low static power consumption reverse connection prevention circuit can also realize ultra-low static current consumption under the condition of realizing reverse connection prevention and high load current application.
Although the example embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the above-described example embodiments are merely illustrative and are not intended to limit the scope of the present application thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present application. All such changes and modifications are intended to be included within the scope of the present application as claimed in the appended claims.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the description of exemplary embodiments of the present application, various features of the present application are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the application and aiding in the understanding of one or more of the various inventive aspects. However, the method of the present application should not be construed to reflect the intent: this application is intended to cover such departures from the present disclosure as come within known or customary practice in the art to which this invention pertains. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this application.
It will be understood by those skilled in the art that all of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where such features are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.
It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
The above description is only for the specific embodiments of the present application or the description thereof, and the protection scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope disclosed in the present application, and shall be covered by the protection scope of the present application. The protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. An ultra-low static power consumption reverse connection prevention circuit is characterized in that the ultra-low static power consumption reverse connection prevention circuit comprises a reverse connection prevention circuit and a static current reduction circuit,
the reverse connection preventing circuit comprises a P-type field effect transistor, a first resistor and an overvoltage protection circuit, wherein the drain electrode of the P-type field effect transistor is divided into
The source electrode of the P-type field effect transistor is respectively connected with one end of the overvoltage protection circuit, the cathode of the power supply and one end of a load, and the grid electrode of the P-type field effect transistor is respectively connected with the other end of the overvoltage protection circuit, the other end of the first resistor and one end of a current limiting element;
the static current reducing circuit comprises an NPN type triode, wherein the base electrode of the NPN type triode is connected with a general input/output interface, the emitting electrode of the NPN type triode is grounded, and the collecting electrode of the NPN type triode is connected with the other end of the current limiting element.
2. The ultra-low static power consumption anti-reverse connection circuit according to claim 1, wherein the over-voltage protection circuit comprises a zener diode and a capacitor connected in parallel, wherein an anode of the zener diode and one end of the capacitor are both connected to the gate of the P-type field effect transistor, and the anode of the zener diode and one end of the capacitor are also connected to one end of the current limiting element; and the cathode of the voltage stabilizing diode and the other end of the capacitor are both connected with the source electrode of the P-type field effect transistor.
3. The ultra-low quiescent power consumption anti-reverse connection circuit of claim 1 or 2, wherein the current limiting element comprises a second resistor.
4. The ultra-low static power consumption anti-reverse connection circuit according to claim 3, wherein the second resistor has a resistance value at least 5 times greater than the first resistor.
5. The ultra-low static power consumption anti-reverse connection circuit as claimed in claim 1, wherein said first resistor has a resistance of 10K ohms.
6. The ultra-low static power consumption anti-reverse connection circuit according to claim 3, wherein the second resistor has a resistance of 2K ohms.
7. The ultra-low static power consumption anti-reverse connection circuit as claimed in claim 1, wherein the gate-source threshold voltage of the P-type field effect transistor is not more than 20 v.
8. The ultra-low static power consumption anti-reverse connection circuit as claimed in claim 1, wherein the gate-source threshold voltage of the P-type field effect transistor is 18 volts.
9. The ultra-low static power consumption anti-reverse connection circuit of claim 1, wherein the power supply is a direct current power supply.
10. The ultra-low static power consumption anti-reverse connection circuit as claimed in claim 1, wherein the source of the P-type fet comprises 5 pins.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222184223.0U CN218498823U (en) | 2022-08-17 | 2022-08-17 | Anti-reverse-connection circuit with ultra-low static power consumption |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202222184223.0U CN218498823U (en) | 2022-08-17 | 2022-08-17 | Anti-reverse-connection circuit with ultra-low static power consumption |
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| CN218498823U true CN218498823U (en) | 2023-02-17 |
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| CN202222184223.0U Active CN218498823U (en) | 2022-08-17 | 2022-08-17 | Anti-reverse-connection circuit with ultra-low static power consumption |
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