CN217848944U - Power bus forbidding control circuit - Google Patents
Power bus forbidding control circuit Download PDFInfo
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- CN217848944U CN217848944U CN202221115941.6U CN202221115941U CN217848944U CN 217848944 U CN217848944 U CN 217848944U CN 202221115941 U CN202221115941 U CN 202221115941U CN 217848944 U CN217848944 U CN 217848944U
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- 230000005669 field effect Effects 0.000 claims description 6
- 230000005764 inhibitory process Effects 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 230000002401 inhibitory effect Effects 0.000 description 3
- 239000000470 constituent Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Abstract
The utility model relates to a power bus bar forbidding control circuit, which comprises an input end, a forbidding end, an output end, a first control circuit and a second control circuit, wherein the first control circuit and the second control circuit are respectively provided with a first end, a second end and a third end; the input end is connected with the first end of the first control circuit and the first end of the second control circuit, and the input end is used for providing power supplies for the first control circuit and the second control circuit; the forbidding end is connected with the second end of the first control circuit and used for receiving the control signal; the output end of the first control circuit is connected with the first end of the first control circuit, and the output end of the first control circuit is connected with the first end of the first control circuit; the third end of the first control circuit is connected with the third end of the second control circuit. The utility model discloses utilize switching on of the first control circuit of the high-low level control of forbidden end to end, and then control switching on of second control circuit to end to the realization is to power generating line's forbidden control under the condition that does not have the controllable chip foot.
Description
Technical Field
The utility model relates to a control circuit especially relates to a power bus forbids control circuit.
Background
In the prior art, a control circuit for inhibiting a power bus is usually designed by adopting a chip with a control feedback pin, but for devices such as a filter and the like which do not have a controllable chip pin, the circuit can not realize the control of inhibiting the power bus, so that a circuit which can realize the control of inhibiting the power bus under the condition of no controllable chip pin is needed.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a control circuit is forbidden to power bus realizes forbidding control to power bus under the condition that does not have controllable chip foot.
The present embodiment provides a power bus bar disable control circuit, including: the circuit comprises an input end, an inhibit end, an output end, a first control circuit and a second control circuit, wherein the first control circuit and the second control circuit are respectively provided with a first end, a second end and a third end;
the input end is connected with the first end of the first control circuit and the first end of the second control circuit and used for providing power supplies for the first control circuit and the second control circuit;
the forbidding end is connected with the second end of the first control circuit and used for receiving a control signal;
the output end is connected with the second end of the second control circuit, and the output end is used for connecting an external load;
and the third end of the first control circuit is connected with the third end of the second control circuit.
Further, the first control circuit includes: the utility model discloses a resistance, including first resistance, second resistance, first MOS pipe, first diode, the one end of first resistance constitutes first control circuit's first end, the negative pole of first diode constitutes first control circuit's second end, the drain electrode of first MOS pipe constitutes first control circuit's third end, the other end of first resistance and the one end of second resistance are connected, the other end ground connection of second resistance, the positive pole of first diode, the grid of first MOS pipe is connected respectively between first resistance, the second resistance, the source electrode ground connection of first MOS pipe.
Further, the second control circuit includes: the high-voltage power supply comprises a third resistor, a fourth resistor and a second MOS (metal oxide semiconductor) tube, wherein one end of the third resistor forms a first end of a second control circuit, a drain electrode of the second MOS tube forms a second end of the second control circuit, one end of the fourth resistor forms a third end of the second control circuit, the other end of the third resistor is connected with the other end of the fourth resistor, a source electrode of the second MOS tube is connected with the third resistor, and a grid electrode of the second MOS tube is connected with the fourth resistor.
Further, the first MOS transistor is an N-channel junction field effect transistor.
Further, the second MOS transistor is a P-channel junction field effect transistor.
Further, the first control circuit further includes: and the second diode is connected between the grid electrode and the source electrode of the first MOS tube.
Implement the embodiment of the utility model provides a, will have following beneficial effect:
the input end is used for providing a power supply source of the first control circuit and the second control circuit, the forbidden end is used for receiving a control signal, the output end is used for being connected with an external load, the forbidden end, the first control circuit and the second control circuit are connected, the conduction and the cut-off of the first control circuit are controlled by using the high and low levels of the forbidden end, the conduction and the cut-off of the second control circuit are further controlled, and therefore the forbidden control of the power bus is achieved under the condition that no controllable chip pin exists.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic block diagram of a power bus bar prohibition control circuit according to an embodiment of the present invention;
fig. 2 is a circuit diagram of a power bus bar prohibition control circuit according to an embodiment of the present invention.
Detailed Description
In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Hereinafter, the term "includes" or "may include" used in various embodiments of the present disclosure indicates the presence of the disclosed functions, operations, or elements, and does not limit the addition of one or more functions, operations, or elements.
Expressions (such as "first", "second", and the like) used in various embodiments of the present disclosure may modify various constituent elements in the various embodiments, but may not limit the respective constituent elements. For example, the above description does not limit the order and/or importance of the elements described. The foregoing description is for the purpose of distinguishing one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of various embodiments of the present disclosure.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1, the present embodiment provides a power bus bar disable control circuit, including: the circuit comprises an input end 100, a forbidden end 102, an output end 104, a first control circuit 106 and a second control circuit 108, wherein the first control circuit 106 and the second control circuit 108 are respectively provided with a first end, a second end and a third end;
the input terminal 100 is connected to a first terminal of the first control circuit 106 and a first terminal of the second control circuit 108, and the input terminal 100 is used for providing power supplies for the first control circuit 106 and the second control circuit 108;
the disable terminal 102 is connected to a second terminal of the first control circuit 106, and the disable terminal 102 is configured to receive a control signal;
the output end 104 is connected with a second end of the second control circuit 108, and the output end 104 is used for connecting an external load;
the third terminal of the first control circuit 106 is connected to the third terminal of the second control circuit 108.
Specifically, the input end 100 provides power supplies of the first control circuit 106 and the second control circuit, and provides input voltage for the power bus disable control circuit, so that the power bus disable control circuit is prevented from being powered off and incapable of working normally; the forbidding end 102 receives the control signal to realize the control of the power bus forbidding control circuit on the power bus, the forbidding end 102 is connected with the first control circuit 106, the first control circuit 106 is connected with the second control circuit 108, the high and low levels of the forbidding end 102 are used for controlling the on and off of the first control circuit 106, and further controlling the on and off of the second control circuit 108, so that the forbidding control on the power bus is realized; the output terminal 104 is connected to an external load, such as a power bus. The power bus bar inhibition control circuit realizes the inhibition control of the power bus bar under the condition without a controllable chip pin.
In one embodiment, as shown in fig. 2, the first control circuit includes: the first resistor R1, the second resistor R2, the first MOS pipe Q1, the first diode D1, the one end of first resistor R1 constitutes first control circuit's first end, the negative pole of first diode D1 constitutes first control circuit's second end, the drain electrode of first MOS pipe Q1 constitutes first control circuit's third end, the other end of first resistor R1 and the one end of second resistor R2 are connected, the other end ground connection of second resistor R2, the positive pole of first diode D1, the grid of first MOS pipe Q1 is connected respectively between first resistor R1, second resistor R2, the source electrode ground connection of first MOS pipe Q1. In this example, the first MOS transistor Q1 is an N-channel junction field effect transistor.
In one embodiment, as shown in fig. 2, the second control circuit includes: the three-phase current source circuit comprises a third resistor R3, a fourth resistor R4 and a second MOS transistor Q2, wherein one end of the third resistor R3 forms a first end of a second control circuit, a drain electrode of the second MOS transistor Q2 forms a second end of the second control circuit, one end of the fourth resistor R4 forms a third end of the second control circuit, the other end of the third resistor R3 is connected with the other end of the fourth resistor R4, a source electrode of the second MOS transistor Q2 is connected with the third resistor R3, and a grid electrode of the second MOS transistor Q2 is connected with the fourth resistor R4. In this example, the second MOS transistor Q2 is a P-channel junction field effect transistor.
In this embodiment, when the inhibit terminal INH is floating or receives a high-level control signal, the circuit is powered on, the voltage of the input terminal VIN + passes through the first resistor R1 and the second resistor R2 to ground, the bias voltage generated by the voltage of the input terminal VIN + on the first resistor R1 and the second resistor R2 satisfies the condition that the first MOS transistor Q1 is turned on, the voltage of the input terminal VIN + passes through the third resistor R3, the fourth resistor R4 and the first MOS transistor Q1 to ground, the bias voltage generated by the voltage of the input terminal VIN + on the third resistor R3 and the fourth resistor R4 turns on the second MOS transistor Q2, and the output terminal circuit connected to the second MOS transistor Q2 outputs a normal output.
When the inhibit terminal INH receives a low-level control signal, the circuit is powered on, the voltage of the input terminal VIN + passes through the first resistor R1 and the first diode D1 to the inhibit terminal INH, the inhibit terminal INH is connected with the low level and does not meet the condition that the first MOS transistor Q1 is conducted, the first MOS transistor Q1 is not conducted, the grid voltage of the second MOS transistor Q2 is equal to the source voltage, the second MOS transistor Q2 is cut off, the output of the connected output terminal circuit is stopped, and therefore the power bus is inhibited.
In one embodiment, the first control circuit further comprises: and a second diode D2, the second diode D2 being connected between the gate and the source of the first MOS transistor Q1. When the first MOS transistor Q1 receives a large voltage, in order to protect the first MOS transistor from being damaged by breakdown of the large voltage, the second diode D2 is connected between the gate and the source of the first MOS transistor Q1.
The input end is used for providing a power supply source of the first control circuit and the second control circuit, the forbidden end is used for receiving a control signal, the output end is used for being connected with an external load, the forbidden end, the first control circuit and the second control circuit are connected, the conduction and the cut-off of the first control circuit are controlled by using the high and low levels of the forbidden end, the conduction and the cut-off of the second control circuit are further controlled, and therefore the forbidden control of the power bus is achieved under the condition that no controllable chip pin exists. And the power bus prohibition control circuit is simple in design and high in reliability.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the claims. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (6)
1. A power bus bar disable control circuit, comprising: the circuit comprises an input end, an inhibit end, an output end, a first control circuit and a second control circuit, wherein the first control circuit and the second control circuit are respectively provided with a first end, a second end and a third end;
the input end is connected with the first end of the first control circuit and the first end of the second control circuit, and the input end is used for providing power supplies for the first control circuit and the second control circuit;
the forbidding end is connected with the second end of the first control circuit and used for receiving a control signal;
the output end is connected with the second end of the second control circuit, and the output end is used for connecting an external load;
and the third end of the first control circuit is connected with the third end of the second control circuit.
2. A power bus disable control circuit as recited in claim 1, wherein said first control circuit comprises: the power supply comprises a first resistor, a second resistor, a first MOS (metal oxide semiconductor) tube and a first diode, wherein one end of the first resistor forms a first end of a first control circuit, a cathode of the first diode forms a second end of the first control circuit, a drain electrode of the first MOS tube forms a third end of the first control circuit, the other end of the first resistor is connected with one end of the second resistor, the other end of the second resistor is grounded, an anode of the first diode and a grid electrode of the first MOS tube are respectively connected between the first resistor and the second resistor, and a source electrode of the first MOS tube is grounded.
3. A power bus disable control circuit as recited in claim 1, wherein said second control circuit comprises: the one end of third resistance constitutes the first end of second control circuit, the drain electrode of second MOS pipe constitutes the second end of second control circuit, the one end of fourth resistance constitutes the third end of second control circuit, the other end of third resistance with the other end of fourth resistance is connected, the source electrode of second MOS pipe with third resistance connects, the grid of second MOS pipe with fourth resistance connects.
4. The power bus bar inhibition control circuit as claimed in claim 2, wherein said first MOS transistor is an N-channel junction field effect transistor.
5. The power bus bar inhibition control circuit as claimed in claim 3, wherein said second MOS transistor is a P-channel junction field effect transistor.
6. A power bus disable control circuit as recited in claim 2, wherein said first control circuit further comprises: the second diode is connected between the grid electrode and the source electrode of the first MOS tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221115941.6U CN217848944U (en) | 2022-05-10 | 2022-05-10 | Power bus forbidding control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221115941.6U CN217848944U (en) | 2022-05-10 | 2022-05-10 | Power bus forbidding control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217848944U true CN217848944U (en) | 2022-11-18 |
Family
ID=84021030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221115941.6U Active CN217848944U (en) | 2022-05-10 | 2022-05-10 | Power bus forbidding control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217848944U (en) |
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2022
- 2022-05-10 CN CN202221115941.6U patent/CN217848944U/en active Active
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