CN218333767U - Packaging structure of power semiconductor device - Google Patents
Packaging structure of power semiconductor device Download PDFInfo
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- CN218333767U CN218333767U CN202222119583.2U CN202222119583U CN218333767U CN 218333767 U CN218333767 U CN 218333767U CN 202222119583 U CN202222119583 U CN 202222119583U CN 218333767 U CN218333767 U CN 218333767U
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- packaging frame
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Abstract
The utility model belongs to the technical field of power semiconductor device's packaging structure technique and specifically relates to a power semiconductor device's packaging structure, including last packaging frame, the downside of going up packaging frame is provided with down packaging frame, the standing groove has been seted up to packaging frame's bottom down, through heat-conducting plate, radiating fin, radiating basal plate and the louvre that sets up on power semiconductor device's packaging structure, on conducting the radiating fin through the heat-conducting plate with the heat that semiconductor chip produced, on giving radiating basal plate through radiating fin conduction, through the multiplicable radiating area of louvre, and can support packaging frame down through first backup pad and the second backup pad that sets up, thereby can make down packaging frame's bottom not be connected with the mounting panel, thereby more make things convenient for the heat dissipation, the radiating effect is better, thereby make the use that semiconductor chip can be fine, the simple structure of overall device and practicality are higher.
Description
Technical Field
The utility model relates to a power semiconductor device's packaging structure technical field specifically is a power semiconductor device's packaging structure.
Background
In the conventional packaging structure of the power semiconductor device, after a semiconductor chip is packaged, the heat dissipation of the semiconductor chip is poor, so that the semiconductor chip is easy to damage, and the normal use is influenced.
There is therefore a need for a packaging structure for a power semiconductor device that ameliorates the above-mentioned problems.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a power semiconductor device's packaging structure to solve the problem that proposes among the above-mentioned background art.
In order to achieve the above object, the utility model provides a following technical scheme:
the utility model provides a power semiconductor device's packaging structure, includes last encapsulation frame, the downside of going up encapsulation frame is provided with down encapsulation frame, the standing groove has been seted up to encapsulation frame's bottom down, the inside of standing groove is provided with radiating basal plate, the louvre has evenly been seted up to radiating basal plate's left surface and right flank, radiating basal plate's upside is provided with radiating fin, radiating fin's upside is provided with the heat-conducting plate, the upside of heat-conducting plate is provided with semiconductor chip, semiconductor chip's front and back symmetry are provided with the pin, the inside of going up encapsulation frame and lower encapsulation frame is provided with the plastic-sealed body, the front side of encapsulation frame bottom is provided with first backup pad down, the rear side of encapsulation frame bottom is provided with the second backup pad down, first fixed orifices has evenly been seted up in the left side of first backup pad and second backup pad base face, the second fixed orifices has evenly been seted up on the right side of first backup pad and second backup pad base face.
As the utility model discloses preferred scheme, go up encapsulation frame and lower encapsulation frame's front and the back and corresponding logical groove of having seted up with the pin respectively.
As the utility model discloses preferred scheme, first fixed orifices is located down the left side of encapsulation frame and offers, the right side that the second fixed orifices is located down the encapsulation frame is offered.
As the preferred scheme of the utility model, the length of first backup pad and second backup pad is greater than the length of lower encapsulation frame.
As the utility model discloses preferred scheme, the plastic envelope body adopts the setting of plastic envelope resin material.
As the utility model discloses preferred scheme, the bottom of pin is on same water flat line with the bottom of first backup pad, second backup pad respectively.
Compared with the prior art, the beneficial effects of the utility model are that:
the utility model discloses in, through the heat-conducting plate that sets up on power semiconductor's packaging structure, radiating fin, radiating basal plate and louvre, conduct on the radiating fin through the heat-conducting plate with the heat that semiconductor chip produced, on giving radiating basal plate through radiating fin conduction, through the radiating fin multiplicable radiating area, and can support lower packaging frame through the first backup pad and the second backup pad that set up, thereby can make packaging frame's bottom not be connected with the mounting panel down, thereby make things convenient for the heat dissipation more, the radiating effect is better, thereby make the use that semiconductor chip can be fine, and through the first fixed orifices and the second fixed orifices of seting up, when installing semiconductor chip, the first fixed orifices of accessible and second fixed orifices carry on wholly spacingly, thereby it is more stable when welding the pin, the integrated device simple structure and practicality are higher.
Drawings
FIG. 1 is a front view of the present invention;
FIG. 2 is a left side view of the whole body of the present invention;
fig. 3 is a bottom structure view of the lower package frame of the present invention.
In the figure: 1. an upper package frame; 2. a lower package frame; 3. a placement groove; 4. a heat-dissipating substrate; 5. heat dissipation holes; 6. a heat dissipating fin; 7. a heat conducting plate; 8. a semiconductor chip; 9. a pin; 10. molding the body; 11. a first support plate; 12. a second support plate; 13. a first fixing hole; 14. and a second fixing hole.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, rather than all embodiments, and all other embodiments obtained by a person of ordinary skill in the art without creative work belong to the scope of the present invention based on the embodiments of the present invention.
In order to facilitate understanding of the invention, the invention will be described more fully hereinafter with reference to the accompanying drawings, in which several embodiments of the invention are shown, but which can be embodied in many different forms and are not limited to the embodiments described herein, but rather are provided for the purpose of making the disclosure more thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present, that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present, and that the terms "vertical", "horizontal", "left", "right" and the like are used herein for descriptive purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, and the use of the terms herein in the specification of the present invention are for the purpose of describing particular embodiments only and are not intended to limit the present invention, and the use of the term "and/or" herein includes any and all combinations of one or more of the associated listed items.
In an embodiment, please refer to fig. 1-3, the present invention provides a technical solution:
the utility model provides a power semiconductor device's packaging structure, including last encapsulation frame 1, the downside of going up encapsulation frame 1 is provided with down encapsulation frame 2, standing groove 3 has been seted up to the bottom of lower encapsulation frame 2, the inside of standing groove 3 is provided with radiating basal plate 4, louvre 5 has evenly been seted up to radiating basal plate 4's left surface and right flank, radiating basal plate 4's upside is provided with radiating fin 6, radiating fin 6's upside is provided with heat-conducting plate 7, heat-conducting plate 7's upside is provided with semiconductor chip 8, semiconductor chip 8's front and back are symmetrical to be provided with pin 9, the inside of going up encapsulation frame 1 and lower encapsulation frame 2 is provided with plastic-sealed body 10, the front side of lower encapsulation frame 2 bottom is provided with first backup pad 11, the rear side of lower encapsulation frame 2 bottom is provided with second backup pad 12, first fixed orifices 13 has evenly been seted up in the left side of first backup pad 11 and second backup pad 12 base planes, second fixed orifices 14 has evenly been seted up on the right side of first backup pad 11 and second backup pad 12 base planes.
Wherein, the front and back of the upper package frame 1 and the lower package frame 2 are respectively provided with a through groove corresponding to the pin 9, the outer end of the pin can pass through the upper package frame 1 and the lower package frame 2, the first fixing hole 13 is positioned at the left side of the lower package frame 2, the second fixing hole 14 is positioned at the right side of the lower package frame 2, the length of the first support plate 11 and the second support plate 12 is larger than that of the lower package frame 2, the first fixing hole 13 and the second fixing hole 14 can be positioned at the left and right sides of the lower package frame 2, thereby more conveniently limiting the pin, the plastic package body 10 is made of plastic package resin, the bottom of the pin 9 is respectively positioned at the same horizontal line with the bottom of the heat dissipation holes of the first support plate 11 and the second support plate 12, the pin 9 can contact with the mounting plate during welding, thereby more conveniently welding, by arranging the heat conduction plate 7, the heat dissipation fins 6, the heat dissipation substrate 4 and the heat dissipation 5 on the package structure of the power semiconductor device, the heat generated by the semiconductor chip 8 is conducted to the heat dissipation fins 6 through the heat conduction plate 7 and is conducted to the heat dissipation base plate 4 through the heat dissipation fins 6, the heat dissipation area can be increased through the heat dissipation holes 5, the lower packaging frame 2 can be supported through the arranged first support plate 11 and the second support plate 12, so that the bottom of the lower packaging frame 2 is not connected with the mounting plate, the heat dissipation is more convenient, the heat dissipation effect is better, the semiconductor chip 8 can be well used, when the semiconductor chip 8 is mounted, the whole body can be limited through the first fixing hole 13 and the second fixing hole 14, when the position is limited, the corresponding hole on the mounting plate is selected, and then the first fixing hole 13 and the second fixing hole 14 are connected with the corresponding hole, thereby can carry on spacingly to first backup pad 11 and second backup pad 12, more stable when welding the pin, the integrated device simple structure and practicality are higher.
The utility model discloses work flow: through set up heat-conducting plate 7 on power semiconductor's packaging structure, radiating fin 6, radiating basal plate 4 and louvre 5, conduct on radiating fin 6 through heat-conducting plate 7 with the heat that semiconductor chip 8 produced, conduct for radiating basal plate 4 through radiating fin 6, through louvre 5 multiplicable radiating area, and can support lower encapsulation frame 2 through first backup pad 11 and the second backup pad 12 that sets up, thereby can make the bottom of lower encapsulation frame 2 not be connected with the mounting panel, thereby more conveniently dispel the heat, the radiating effect is better, thereby make the use that semiconductor chip 8 can be fine, and through the first fixed orifices 13 and the second fixed orifices 14 of seting up, when installing semiconductor chip 8, accessible first fixed orifices 13 and second fixed orifices 14 are spacing whole, thereby it is more stable when welding the pin, the integrated device simple structure and practicality are higher.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (6)
1. A packaging structure of a power semiconductor device comprises an upper packaging frame (1), and is characterized in that: the packaging structure is characterized in that a lower packaging frame (2) is arranged on the lower side of the upper packaging frame (1), a placing groove (3) is formed in the bottom of the lower packaging frame (2), a heat dissipation substrate (4) is arranged inside the placing groove (3), heat dissipation holes (5) are uniformly formed in the left side face and the right side face of the heat dissipation substrate (4), heat dissipation fins (6) are arranged on the upper side of the heat dissipation substrate (4), a heat conduction plate (7) is arranged on the upper side of the heat dissipation fins (6), a semiconductor chip (8) is arranged on the upper side of the heat conduction plate (7), pins (9) are symmetrically arranged on the front face and the back face of the semiconductor chip (8), a plastic package body (10) is arranged inside the upper packaging frame (1) and the lower packaging frame (2), a first fixing hole (13) is uniformly formed in the left sides of the first supporting plate (11) and the second supporting plate (12), and a second fixing hole (14) is uniformly formed in the right sides of the first supporting plate (11) and the second supporting plate (12).
2. The package structure of a power semiconductor device according to claim 1, wherein: the front and back of the upper packaging frame (1) and the lower packaging frame (2) are respectively provided with a through groove corresponding to the pins (9).
3. The package structure of a power semiconductor device according to claim 1, wherein: the first fixing hole (13) is formed in the left side of the lower packaging frame (2), and the second fixing hole (14) is formed in the right side of the lower packaging frame (2).
4. The package structure of a power semiconductor device according to claim 1, wherein: the lengths of the first supporting plate (11) and the second supporting plate (12) are larger than that of the lower packaging frame (2).
5. The package structure of a power semiconductor device according to claim 1, wherein: the plastic package body (10) is made of plastic package resin materials.
6. The package structure of a power semiconductor device according to claim 1, wherein: the bottoms of the pins (9) are respectively on the same horizontal line with the bottoms of the first supporting plate (11) and the second supporting plate (12).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222119583.2U CN218333767U (en) | 2022-08-12 | 2022-08-12 | Packaging structure of power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222119583.2U CN218333767U (en) | 2022-08-12 | 2022-08-12 | Packaging structure of power semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218333767U true CN218333767U (en) | 2023-01-17 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222119583.2U Active CN218333767U (en) | 2022-08-12 | 2022-08-12 | Packaging structure of power semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218333767U (en) |
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2022
- 2022-08-12 CN CN202222119583.2U patent/CN218333767U/en active Active
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