CN218100218U - Universal VPX high-speed processing board - Google Patents

Universal VPX high-speed processing board Download PDF

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Publication number
CN218100218U
CN218100218U CN202221789405.4U CN202221789405U CN218100218U CN 218100218 U CN218100218 U CN 218100218U CN 202221789405 U CN202221789405 U CN 202221789405U CN 218100218 U CN218100218 U CN 218100218U
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interface
chip
vpx
module
voltage
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郭云霞
范思聪
王焱
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Henan Chuheng Electronic Technology Co ltd
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Henan Chuheng Electronic Technology Co ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The utility model provides a general VPX high-speed processing board, which is provided with a processing module, an interface module and a storage module, wherein the processing module is respectively connected with the interface module and the storage module; the processing module comprises an FPGA chip, the storage module comprises two DDR4 SODIMM memory banks, and the interface module comprises a QSFP28 interface, a tera SFP + interface, a gigabit RJ45 interface, a FMC interface and a 6U VPX interface. The utility model discloses a general type VPX high speed processing board, the FPGA who integrates high operational resource, board year high speed large capacity cache to have a plurality of high speed transmission interfaces and a plurality of extension FMC interfaces outward, solve the current problem that handling plate card throughput is low, throughput is little, the commonality is low of handling; and the heat dissipation performance is good.

Description

Universal VPX high-speed processing board
Technical Field
The utility model relates to a signal communication technology field especially relates to a general type VPX high speed processing board.
Background
A plurality of processing modules of the conventional VPX platform are produced in a customized mode according to requirements, the onboard real-time storage capacity is low, the data throughput is low, real-time processing and forwarding cannot be realized during high-speed operation, a plurality of processing modules are needed when the operation amount is large, the generated heat is large, the compatibility with the platform is poor, and the difficulty of later development is large.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned defects, an object of the present invention is to provide a general purpose VPX high-speed processing board, which integrates a high-computation resource FPGA, carries a high-speed high-capacity cache, and has a plurality of high-speed transmission interfaces and a plurality of extended FMC interfaces, thereby solving the problems of low throughput, small processing capacity, and low versatility of the existing processing board; and the heat dissipation performance is good.
In order to achieve the above object, the present invention provides a general purpose VPX high-speed processing board, which is provided with a processing module, an interface module and a storage module, wherein the processing module is respectively connected to the interface module and the storage module; the processing module comprises an FPGA chip, the storage module comprises two DDR4 SODIMM memory banks, and the interface module comprises a QSFP28 interface, a tera SFP + interface, a gigabit RJ45 interface, a FMC interface and a 6U VPX interface;
two DDR4 SODIMM memory banks are connected with the FPGA chip; the QSFP28 interface is connected with the chip FPGA; the ten-thousand-million SFP + interface and the kilomega RJ45 interface are respectively connected with the FPGA chip; the FMC interface is connected with the FPGA chip; the 6U VPX interface is connected with the FPGA chip.
Preferably, two QSFP28 interfaces are arranged, and the two QSFP28 interfaces are connected with a GTY serial transceiver on the chip FPGA.
Further, the QSFP28 interface is connected with the FPGA chip through a 4-way GTY serial transceiver.
Furthermore, the number of the FMC interfaces is two, and each FMC interface is connected with the FPGA chip through 28 paths of LVDS interfaces and 8 paths of GTY serial transceivers.
Furthermore, two DDR4 SODIMM memory banks are connected with the FPGA chip through 64-bit data bits;
the ten-thousand-megabyte SFP + interface is connected with the FPGA chip through a 1-path GTY serial transceiver; the kilomega RJ45 interface is connected with the FPGA chip through an RGMII interface;
the 6U VPX interface is connected with the FPGA chip through a 16-path SRIO serial high-speed bus.
Furthermore, the FPGA chip is also connected with a NOR FLASH FLASH memory chip for loading the system start configuration file in the BPI mode.
Furthermore, a UART serial port is also arranged on the FPGA chip.
Furthermore, a clock module and a power module are also arranged on the general VPX high-speed processing board;
the clock module comprises a 100MHz system clock, a 100MHz storage clock and a 156.25MHz GTY clock;
the system clock is used for providing differential clock input for the FPGA chip;
the memory clock is used for providing differential clock input for DDR4 SODIMM memory banks;
the GTY clock is used for providing differential clock input for the high-speed serial port;
the clock module further comprises a tunable clock, the tunable clock reference can use an on-board reference or an external reference;
the tunable clock is used to provide a differential clock input to the acquisition module.
Further, the power module adopts a single power supply +12V for power supply;
the +12V single power supply is converted by the chip LTM4650 to obtain 0.85V voltage to be supplied to the FPGA chip;
the single power supply +12V is converted into 1.2V and 0.9V voltage through a chip LTM4620 and is supplied to the FPGA chip;
the +12V single power supply is converted by another chip LTM4620 to obtain 1.2V and 1.8V voltages which are supplied to the FPGA chip;
the +12V single power supply is converted by a chip TPS54622 to obtain 3.3V voltage and output the voltage to the clock module and the external interface module;
the 3.3V voltage is obtained by conversion of the chip TPS54622, and the 1V voltage is obtained by conversion of the chip RT8015 and is output to a gigabit network interface chip;
the +12V single power supply is converted by a chip TPS54525 to obtain 5V voltage, and the voltage is output to an RS232 interface;
the 5V voltage converted by the chip TPS54525 is also converted by the chip TLV62130 to obtain a 2.5V voltage which is output to the DDR4 memory module.
The voltage of the DDR4 SODIMM memory bank is the voltage converted and output by the chip TPS51200 through 1.2V and 3.3V voltages.
Furthermore, the general VPX high-speed processing board adopts air cooling or cold conduction heat dissipation.
The utility model provides a general VPX high-speed processing board, which integrates the FPGA with high operation resources, carries a high-speed and large-capacity onboard cache, and is externally provided with a plurality of high-speed transmission interfaces and a plurality of extended FMC interfaces, thus solving the problems of low throughput, small processing capacity and low universality of the existing processing board card; and the heat dissipation performance is good.
Drawings
FIG. 1 is a block diagram of a general VPX high-speed processing board according to the present invention;
FIG. 2 is a distribution diagram of a clock module;
fig. 3 is an allocation diagram of a power supply module.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, the utility model provides a high-speed processing board of general type VPX, be provided with processing module, interface module and storage module on the high-speed processing board of general type VPX. The processing module is respectively connected with the interface module and the storage module.
The processing module comprises an FPGA chip, the FPGA chip adopts XILINX Ultrascale + series chips, and Virtex Ultrascale + series FPGAs provide the highest performance and the integration function on 14nm/16nm FinFET nodes. The FPGA integrated GTY transceiver has the advantages of abundant register resources, higher wiring efficiency, a strong mixed mode clock management module, a high-performance parallel SelectIO technology, multiple high-level DSP48E1 slices, SPI and parallel Flash interfaces, flexible configuration of the FPGA, integration of the FPGA with the GTY transceiver and a rate of 32.75 Gbit/s. Specifically, the FPGA XCVU9P-FLGA2104 of the UltraScale + series of Xilinx company is selected as the main processing chip of the FPGA chip.
The FPGA chip is also connected with a NOR FLASH FLASH memory chip and is used for loading the system starting configuration file in the BPI mode.
The FPGA chip is also provided with a UART serial port which can set the state of an output system.
The memory module comprises two DDR4 SODIMM memory banks, the maximum memory capacity supports 16GB, the speed supports 2666Mb/s, higher efficiency and low time delay are provided, and real-time cache can be provided for data processing.
The two DDR4 SODIMM memory banks are connected with the FPGA chip through 64bit data bits;
the interface module comprises a QSFP28 interface, a gigabit SFP + interface, a gigabit RJ45 interface, a FMC interface and a 6U VPX interface.
Two QSFP28 interfaces are arranged, the two QSFP28 interfaces are directly connected with a GTY serial transceiver on the chip FPGA, and the throughput of the QSFP28 interfaces can reach 200Gbps. Specifically, the QSFP28 interface is connected to the FPGA chip via a 4-way GTY serial transceiver.
The number of the ten-thousand SFP + interfaces and the number of the kilomega RJ45 interfaces are respectively 1. The ten-thousand-megabyte SFP + interface is connected with the FPGA chip through a 1-path GTY serial transceiver; the kilomega RJ45 interface is connected with the FPGA chip through an RGMII interface;
two FMC interfaces are arranged, each FMC interface is connected with the FPGA chip through 28 paths of LVDS interfaces and 8 paths of GTY serial transceivers, and the electrical level of each LVDS interface is 1.8V when the LVDS interfaces are used as single-ended signals; the specific signals of the FMC interface are defined according to the FMC standard.
The I2C bus of the FMC interface is connected to the VPX interface.
And an I2C bus for monitoring the temperature of the FPGA chip is connected to the VPX interface.
One 6U VPX interface is arranged, and the 6U VPX interface is connected with the FPGA chip through a 16-channel SRIO serial high-speed bus.
The general VPX high-speed processing board is also provided with a clock module and a power module,
referring to fig. 2, the clock module includes a 100MHz system clock, a 100MHz memory clock, and a 156.25MHz GTY clock.
The system clock is used for providing differential clock input for the FPGA chip.
The memory clock is used to provide a differential clock input to the DDR4 sodmm memory banks.
The GTY clock is used for providing differential clock input for the high-speed serial port.
The clock module also includes a tunable clock, which may use an on-board reference or an external reference.
The adjustable clock is used for providing differential clock input for the acquisition module.
The design of the clock module is flexible, a 100MHz differential clock is provided as a system clock, the GTY has high quality requirement on a clock source, a clock multiplexing chip SI53302 is adopted to provide 156.25MHz differential clock input during design, and two DDR4 SODIMM memory banks adopt a same-source 100M clock.
Referring to fig. 3, the power module is powered by a single power supply + 12V.
The large power consumption device in the general VPX high-speed processing board mainly comprises: FPGA chips and DDR4 sodim memory banks. The general VPX high-speed processing board adopts 12V power supply input, can supply power through a VPX interface or an external socket, and the FMC daughter card supplies power through 12V and 1.8V through an FMC plug-in. And each voltage in the universal VPX high-speed processing board is obtained by conversion of a power supply module. The power module supply scheme is shown in fig. 3.
The single power supply +12V is converted by the chip LTM4650 to obtain 0.85V voltage to be supplied to the FPGA chip;
the single power supply +12V is converted into 1.2V and 0.9V voltage through a chip LTM4620 and is supplied to the FPGA chip;
the single power supply +12V is converted by another chip LTM4620 to obtain 1.2V and 1.8V voltage to be supplied to the FPGA chip;
the +12V single power supply is converted by the chip TPS54622 to obtain 3.3V voltage and output the voltage to the clock module and the external interface module;
the 3.3V voltage is obtained by conversion of the chip TPS54622, and the 1V voltage is obtained by conversion of the chip RT8015 and is output to a gigabit network interface chip;
the +12V single power supply is converted by a chip TPS54525 to obtain 5V voltage, and the voltage is output to an RS232 interface;
the 5V voltage obtained through conversion of the chip TPS54525 is further converted into a 2.5V voltage through conversion of the chip TLV62130 and is output to the DDR4 memory module.
The voltage of the DDR4 SODIMM memory bank is the voltage converted and output by the chip TPS51200 through 1.2V and 3.3V voltages.
The general VPX high-speed processing plate can use air cooling or cold conduction for heat dissipation.
In the VPX platform, the general VPX high-speed processing board plays a role in high-speed processing transmission and expansion. The multiple high-speed interfaces enable the system to be compatible with various external devices, and the standard VPX interface connection enables the universal VPX high-speed processing board to be suitable for the VPX system under multiple environments.
The working flow of the general VPX high-speed processing plate is described as follows: the main processing chip adopts Xilinx Ultrascale + series FPGA. The FPGA chip has rich pin resources and strong operation processing capability, provides a large number of assembly lines and extended functions, and can improve the speed and efficiency of a plurality of applications. The FPGA chip is connected with all interfaces and storage devices on the general VPX high-speed processing board. The FPGA chip is provided with two DDR4 SODIMM memory strips, and the storage IP can easily construct a reliable interface to the latest high-performance memory. The two standard FMC-HPC interfaces are connected with the FPGA chip, the FMC interfaces are connected with the FPGA chip through 28 LVDS interfaces and 8 GTY interfaces, the FMC interfaces can be used as external expansion interfaces to be connected with an acquisition module or other processing modules, each GTY serial transceiver integrates functions of a transmitter and a receiver, and the high-speed connectors enable data to be sent to the FPGA chip in real time to be processed in a real-time operation mode. The FPGA chip adopts a Master BPI synchronous configuration mode, and the configuration chip is completed by selecting 1Gbit capacity. Two QSFP28 interfaces are led out from a GTX serial transceiver of the FPGA chip, the speed reaches 100Gb/s, and high-speed forwarding of data is realized.
The utility model provides a general VPX high-speed processing board, which integrates the FPGA with high operation resources, carries a high-speed and large-capacity onboard cache, and is externally provided with a plurality of high-speed transmission interfaces and a plurality of extended FMC interfaces, thus solving the problems of low throughput, small processing capacity and low universality of the existing processing board card; and the heat dissipation performance is good.
Naturally, the present invention can be embodied in many other forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be made by one skilled in the art without departing from the spirit or essential attributes thereof, and it is intended that all such changes and modifications be considered as within the scope of the appended claims.

Claims (10)

1. A general VPX high-speed processing board is characterized in that a processing module, an interface module and a storage module are arranged on the general VPX high-speed processing board, and the processing module is respectively connected with the interface module and the storage module; the processing module comprises an FPGA chip, the storage module comprises two DDR4 SODIMM memory banks, and the interface module comprises a QSFP28 interface, a tera SFP + interface, a gigabit RJ45 interface, a FMC interface and a 6U VPX interface;
two DDR4 SODIMM memory banks are connected with the FPGA chip; the QSFP28 interface is connected with the chip FPGA; the ten-thousand-million SFP + interface and the kilomega RJ45 interface are respectively connected with the FPGA chip; the FMC interface is connected with the FPGA chip; the 6U VPX interface is connected with the FPGA chip.
2. The universal VPX high-speed processing board according to claim 1, wherein two QSFP28 interfaces are provided, and both QSFP28 interfaces are connected with a GTY serial transceiver on a chip FPGA.
3. The universal VPX high-speed processing board according to claim 1, wherein the QSFP28 interface is connected to the FPGA chip through a 4-way GTY serial transceiver.
4. The universal VPX high-speed processing board according to claim 1, wherein there are two FMC interfaces, and each FMC interface is connected to the FPGA chip through a 28-way LVDS interface and an 8-way GTY serial transceiver.
5. The universal VPX high-speed processing board according to claim 1, wherein two DDR4 SODIMM memory banks are connected with the FPGA chip through 64-bit data bits;
the ten-thousand-megabyte SFP + interface is connected with the FPGA chip through a 1-path GTY serial transceiver; the kilomega RJ45 interface is connected with the FPGA chip through an RGMII interface;
the 6U VPX interface is connected with the FPGA chip through a 16-path SRIO serial high-speed bus.
6. The universal VPX high-speed processing board according to any one of claims 2 to 5, wherein the FPGA chip is further connected with a NOR FLASH FLASH memory chip for loading the system boot configuration file in the BPI mode.
7. A universal VPX high-speed processing board according to any one of claims 2 to 5, wherein a UART serial port is further provided on the FPGA chip.
8. The universal VPX high-speed processing board according to claim 1, wherein a clock module and a power module are further disposed on the universal VPX high-speed processing board;
the clock module comprises a 100MHz system clock, a 100MHz storage clock and a 156.25MHz GTY clock;
the system clock is used for providing differential clock input for the FPGA chip;
the memory clock is used for providing differential clock input for DDR4 SODIMM memory bars;
the GTY clock is used for providing differential clock input for the high-speed serial port;
the clock module also includes an adjustable clock.
9. The universal VPX high speed processing board according to claim 8, wherein the power supply module is powered by a single power supply + 12V;
the single power supply +12V is converted by the chip LTM4650 to obtain 0.85V voltage to be supplied to the FPGA chip;
the single power supply +12V is converted into 1.2V and 0.9V voltage through a chip LTM4620 and is supplied to the FPGA chip;
the single power supply +12V is converted by another chip LTM4620 to obtain 1.2V and 1.8V voltage to be supplied to the FPGA chip;
the +12V single power supply is converted by a chip TPS54622 to obtain 3.3V voltage and output the voltage to the clock module and the external interface module;
the 3.3V voltage obtained by conversion of the chip TPS54622 is also converted by the chip RT8015 to obtain 1V voltage which is output to a gigabit network interface chip;
the +12V single power supply is converted by a chip TPS54525 to obtain 5V voltage, and the voltage is output to an RS232 interface;
the 5V voltage is obtained through conversion of a chip TPS54525, and the 2.5V voltage is obtained through conversion of a chip TLV62130 and is output to the DDR4 SODIMM memory bank;
the voltage of the DDR4 SODIMM memory bank is the voltage converted and output by the chip TPS51200 through 1.2V and 3.3V voltages.
10. The universal VPX high speed processing board according to claim 1, wherein the universal VPX high speed processing board is air cooled or heat guided.
CN202221789405.4U 2022-07-12 2022-07-12 Universal VPX high-speed processing board Active CN218100218U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202221789405.4U CN218100218U (en) 2022-07-12 2022-07-12 Universal VPX high-speed processing board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202221789405.4U CN218100218U (en) 2022-07-12 2022-07-12 Universal VPX high-speed processing board

Publications (1)

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CN218100218U true CN218100218U (en) 2022-12-20

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