CN217606275U

CN217606275U - Electric erasing storage circuit based on DSP chip and frequency conversion controller

Info

Publication number: CN217606275U
Application number: CN202221871526.3U
Authority: CN
Inventors: 刘�东; 欧子阳; 田召广; 于洋; 王云波; 田淑杭
Original assignee: Ceristar Electric Co ltd; MCC Capital Engineering and Research Incorporation Ltd
Current assignee: Ceristar Electric Co ltd; MCC Capital Engineering and Research Incorporation Ltd
Priority date: 2022-07-13
Filing date: 2022-07-13
Publication date: 2022-10-18
Anticipated expiration: 2032-07-13

Abstract

The utility model discloses an electricity erases storage circuit and variable frequency controller based on DSP chip, wherein, this electricity erases storage circuit includes: the DSP chip and the I2C bus electrically erase memory; the I2C bus electric erasing memory is connected with the DSP chip and used for storing parameter data inside the DSP chip. The utility model discloses can realize that the internal parameter is preserved, preserve inside only serial number, system's signal correction parameter, the trigger pulse level key data constantly of trouble.

Description

Electric erasing storage circuit based on DSP chip and frequency conversion controller

Technical Field

The utility model relates to an electronic circuit field especially relates to an electricity erases storage circuit and frequency conversion controller based on DSP chip.

Background

This section is intended to provide a background or context to the embodiments of the invention that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.

The DSP chip is used as a main control chip of the frequency converter, can realize various complex algorithms by utilizing an integrated program package, and has the advantage of short development period. In the prior art, a data memory needs to be read and written by using an SPI bus or a LocalBus bus built in a DSP chip and a special storage bus. However, this method needs to consume a large amount of data and address signal lines, occupies valuable external pins of the DSP chip, and meanwhile, needs to perform detailed processing on the length and arrangement position of the signal lines during the wiring process of the circuit board, which is prone to signal interference, resulting in errors in storing data.

Thus, there is a need for a memory read and write scheme that overcomes the above-mentioned problems.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides an in embodiment provides an electricity based on DSP chip erases memory circuit for realize that the internal parameter is preserved, preserved inside only serial number, system signal correction parameter, the trigger pulse level key data constantly of trouble, this electricity based on DSP chip erases memory circuit includes: the DSP chip and the I2C bus electrically erase memory; the I2C bus electric erasing memory is connected with the DSP chip and used for storing parameter data inside the DSP chip.

Further, the internal parameter data includes: the DSP chip has one or any combination of unique serial numbers, system signal correction parameters and fault moment trigger pulse level data.

Furthermore, the I2C bus electric erasing memory is an AT24C64CN-SH-T chip; the DSP chip is a TMS320F28232 chip.

Further, the TMS320F28232 chip comprises: SDAA data signal pin and SCLA clock signal pin; the AT24C64CN-SH-T chip comprises: SDAA data signal pin and SCLA clock signal pin;

the SDAA data signal pin of the TMS320F28232 chip is connected with the SDAA data signal pin of the AT24C64CN-SH-T chip; the SCLA clock signal pin of the TMS320F28232 chip is connected with the SCLA clock signal pin of the AT24C64CN-SH-T chip.

The embodiment of the utility model provides an in still provide a frequency conversion controller for realize that the internal parameter is preserved, preserved inside only serial number, system signal correction parameter, the critical data of trigger pulse level constantly of trouble, this frequency conversion controller includes: the electric erasing memory circuit based on the DSP chip is described.

Further, the variable frequency controller further comprises: and the FPGA chip is connected with the DSP chip and is used for transmitting the control signal output by the DSP chip to a plurality of external frequency conversion devices in parallel.

Further, the variable frequency controller further comprises: and the external expansion board is connected with the FPGA chip and is used for expanding a field bus or an Ethernet bus.

Further, the variable frequency controller further comprises: and the interrupt signal transmission interface is connected with the FPGA chip and is used for transmitting an interrupt signal.

Further, the FPGA chip is used to extend any one of the following interfaces: the device comprises a CAN bus interface, an RS485 bus interface, an RS232 bus interface, an SSI encoder signal interface, an incremental encoder signal interface, a digital quantity input signal interface, a digital quantity output signal interface, an analog quantity input signal interface, an analog quantity output signal interface and a power supply interface.

Further, the variable frequency controller further comprises: a USB interface for communicating with an external USB device; and the USB-to-TTL module is connected with the DSP chip and is used for converting the USB data into the TTL data.

Further, the variable frequency controller further comprises: and the RTC clock chip is connected with the DSP chip and used for providing a clock signal.

Further, the variable frequency controller further comprises: and the DDR memory is connected with the DSP chip and is used for storing memory data.

Further, the variable frequency controller further comprises: and the CF card interface is connected with the DSP chip and used for storing data into an external CF card or reading data in the external CF card.

Further, the variable frequency controller further comprises: a nixie tube driving chip and a nixie tube; the nixie tube driving chip is connected with the DSP chip and used for driving the nixie tube to be turned on or turned off; the nixie tube is used for displaying the state information of the variable frequency controller.

The embodiment of the utility model provides an in provide an electricity based on DSP chip erases memory circuit and frequency conversion controller, through I2C bus electricity erase memory and DSP chip be connected with storage DSP chip internal parameter data to realize that internal parameter preserves, preserved inside only serial number, system signal correction parameter, the trigger pulse level key data constantly of trouble.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts. In the drawings:

FIG. 1 is a schematic diagram of an electrical erasing memory circuit based on DSP chip according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a TMS320F28232 chip signal pin according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a signal pin of an AT24C64CN-SH-T chip according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a frequency conversion controller according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention are described in further detail below with reference to the accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention.

The embodiment of the utility model provides an in provide an electricity based on DSP chip erases memory circuit, figure 1 is the embodiment of the utility model provides an in embodiment an electricity based on DSP chip erases memory circuit schematic diagram, as shown in figure 1, this electricity erases memory circuit and includes: a DSP chip 10 and an I2C bus electric erasing memory 11;

the I2C bus electrical erasing memory 11 is connected to the DSP chip 10, and is configured to store parameter data inside the DSP chip 10.

In one embodiment, in the electrically erasing memory circuit provided in the embodiment of the present invention, the I2C bus electrically erasing memory 11 employs an AT24C64CN-SH-T chip; the DSP chip 10 adopts a TMS320F28232 chip. The TMS320F28232 chip is a high-end DSP chip and can run a real-time operating system. The AT24C64CN-SH-T chip is an I2C bus electric erasing memory and can store internal parameter data of the DSP chip.

In one embodiment, the present invention provides an electrical erasing memory circuit, wherein the internal parameter data includes: the DSP chip has one or any combination of unique serial numbers, system signal correction parameters and fault moment trigger pulse level data.

Fig. 2 shows signal pins of a DSP chip provided in an embodiment of the present invention, and a definition of a part of the signal pins of the TMS320F28232 chip is shown in table 1. Fig. 3 illustrates a signal pin of an AT24C64CN-SH-T chip provided in an embodiment of the present invention, and a part of the signal pins of the AT24C64CN-SH-T chip is defined as shown in table 2.

TABLE 1

Serial number	Pin number	Name (R)	Means of
				1	74	SDAA	Data signal
2	75	SCLA	Clock signal

TABLE 2

Serial number	Pin number	Name (R)	Means of
				1	1	A0	I2C Address 0
2	2	A1	I2C Address 1
				3	3	A2	I2C Address	2
4	4	VSS	Power ground
				5	5	SDAA	Data signal
6	6	SCLA	Clock signal
				7	7	WP	Write protection signal
8	8	VCC	Power supply positive

In this embodiment, the TMS320F28232 chip includes: SDAA data signal pin and SCLA clock signal pin; the AT24C64CN-SH-T chip comprises: SDAA data signal pin and SCLA clock signal pin; the SDAA data signal pin of the TMS320F28232 chip is connected with the SDAA data signal pin of the AT24C64CN-SH-T chip; the SCLA clock signal pin of the TMS320F28232 chip is connected with the SCLA clock signal pin of the AT24C64CN-SH-T chip.

In this embodiment, the electrical erasing memory circuit based on DSP chip further includes: the AT24C64CN-SH-T chip further comprises a capacitor, a first resistor and a second resistor: WP write protect signal pin; the capacitor is connected between a WP write protection signal pin of the AT24C64CN-SH-T chip and external 3.3V power supply, the first resistor is connected between an SCLA clock signal pin of the AT24C64CN-SH-T chip and the external 3.3V power supply, and the second resistor is connected between an SDAA data signal pin of the AT24C64CN-SH-T chip and the external 3.3V power supply.

In this embodiment, in the electrical erasing memory circuit based on the DSP chip, the AT24C64CN-SH-T chip further includes: the VCC power supply positive pin, VSS power supply ground pin, I2C address 0 pin, I2C address 1 pin, I2C address 2 pin are connected to ground, the VCC power supply positive pin is connected outside 3.3V power supply.

Fig. 4 is the embodiment of the utility model provides an in the embodiment of a frequency conversion controller sketch map, as shown in fig. 4, the embodiment of the utility model provides a frequency conversion controller still is provided, include: any of the above DSP chip based electrically erasable memory circuits.

In one embodiment, the present invention provides a frequency conversion controller, further comprising: and the FPGA chip 20 is connected with the DSP chip 10 and is used for transmitting the control signals output by the DSP chip 10 to a plurality of external frequency conversion devices in parallel.

In one embodiment, the present invention provides a frequency conversion controller, further comprising: a USB interface 101 for communicating with an external USB device; and the USB-TTL102 is connected with the DSP chip 10 and is used for converting USB data into TTL data.

In one embodiment, the present invention provides a frequency conversion controller, further comprising: and the RTC clock chip 103 is connected with the DSP chip 10 and used for providing a clock signal.

In one embodiment, the present invention provides a variable frequency controller, further comprising: and the DDR memory 104 is connected with the DSP chip 10 and is used for storing memory data.

The embodiment of the utility model provides a frequency conversion controller can adopt 24V DC power supply, is connected with external power source through the power source 211 of bottom. Alternatively, the power interface 211 may be a power terminal.

In one embodiment, the present invention provides a frequency conversion controller, further comprising: and a CF card interface 105 connected to the DSP chip 10, for storing data in an external CF card or reading data in the external CF card. By expanding the DSP chip to the CF card storage function, system data or user data is stored in the CF card, and system and program upgrading can be conveniently carried out through the CF card.

In one embodiment, the present invention provides a frequency conversion controller, further comprising: a nixie tube driving chip 106 and a nixie tube 107; the nixie tube driving chip 106 is connected with the DSP chip 10 and is used for driving the nixie tube 107 to be turned on or turned off; the nixie tube 107 is used for displaying the state information of the variable frequency controller. Optionally, the nixie tube 107 is an 8-bit LED nixie tube for displaying the current controller state, so that the user can conveniently determine the current condition of the software inside the controller. Alternatively, the nixie driver chip 106 may be a 74HC595D serial-to-parallel chip, which converts the serial signal of the DSP chip into a parallel signal for driving the LED nixie tube.

In one embodiment, the present invention provides a frequency conversion controller, further comprising: and the external expansion board 201 is connected with the FPGA chip 20 and is used for expanding various field buses or Ethernet buses. The FPGA chip expands the external expansion board through the internal bus, can realize the support of various field buses and real-time Ethernet buses, and enhances the expansibility of the system.

In one embodiment, the present invention provides a frequency conversion controller, further comprising: and an interrupt signal transmission interface 212 connected to the FPGA chip 20 for transmitting an interrupt signal.

In an embodiment, in the variable frequency controller provided in the embodiment of the present invention, the FPGA chip 20 may be further configured to extend any one of the following interfaces, i.e., a CAN bus interface 202, an RS485 bus interface 203, an RS232 bus interface 204, an SSI encoder signal interface 205, an incremental encoder signal interface 206, a digital input signal interface 208, a digital output signal interface 207, an analog input signal interface 210, an analog output signal interface 209, and a power interface 211. By expanding the data transmission interfaces of various communication protocols, the coordinated and unified operation of multiple communication protocols is realized. The FPGA chip expands an interrupt signal transmission interface for receiving or sending a quick interrupt signal in a plastic optical fiber or glass optical fiber mode, and data synchronization and signal synchronization among a plurality of controllers are achieved. The DSP chip also supports interrupt triggering functions to enable emergency processing of fast signals.

To sum up, the embodiment of the utility model provides an in the electricity based on DSP chip erase storage circuit and frequency conversion controller, through I2C bus electricity erase memory and DSP chip be connected with storage DSP chip internal parameter data to only realized that internal parameter preserves through 2 way signal lines, preserved inside only serial number, system signal correction parameter, the trigger pulse level key data of trouble moment.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above-mentioned embodiments, which further illustrate the objects, technical solutions and advantages of the present invention in detail, it should be understood that the above-mentioned embodiments are only examples of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. An electrically erasable memory circuit based on a DSP chip, comprising: a DSP chip (10) and an I2C bus electric erasing memory (11);

the I2C bus electric erasing memory (11) is connected with the DSP chip (10) and used for storing parameter data inside the DSP chip (10).

2. The DSP chip based electrically erasable memory circuit of claim 1 wherein said internal parameter data comprises: the DSP chip has one or any combination of unique serial numbers, system signal correction parameters and fault moment trigger pulse level data.

3. The DSP chip based electrically erasable memory circuit of claim 1 wherein said I2C bus electrically erasable memory (11) is an AT24C64CN-SH-T chip; the DSP chip (10) is a TMS320F28232 chip.

4. The DSP chip-based electrically erasable memory circuit of claim 3, wherein the TMS320F28232 chip comprises: SDAA data signal pin and SCLA clock signal pin; the AT24C64CN-SH-T chip comprises: SDAA data signal pin and SCLA clock signal pin;

5. A variable frequency controller, comprising: an electrically erasable memory circuit according to any one of claims 1 to 4 based on a DSP chip.

6. The variable frequency controller of claim 5, further comprising:

and the FPGA chip (20) is connected with the DSP chip (10) and is used for transmitting the control signals output by the DSP chip (10) to a plurality of external frequency conversion devices in parallel.

7. The variable frequency controller of claim 6, further comprising:

and the external expansion board (201) is connected with the FPGA chip (20) and is used for expanding a field bus or an Ethernet bus.

8. The variable frequency controller of claim 6, further comprising:

and the interrupt signal transmission interface (212) is connected with the FPGA chip (20) and is used for transmitting an interrupt signal.

9. The variable frequency controller according to claim 6, wherein the FPGA chip (20) is configured to extend any one of the following interfaces: the device comprises a CAN bus interface (202), an RS485 bus interface (203), an RS232 bus interface (204), an SSI encoder signal interface (205), an incremental encoder signal interface (206), a digital quantity input signal interface (208), a digital quantity output signal interface (207), an analog quantity input signal interface (210), an analog quantity output signal interface (209) and a power interface (211).

10. The variable frequency controller of claim 5, further comprising:

a USB interface (101) for communicating with an external USB device;

and the USB-TTL (102) is connected with the DSP chip (10) and is used for converting the USB data into TTL data.

11. The variable frequency controller of claim 5, further comprising:

and the RTC clock chip (103) is connected with the DSP chip (10) and is used for providing a clock signal.

12. The variable frequency controller of claim 5, further comprising:

and the DDR memory (104) is connected with the DSP chip (10) and is used for storing memory data.

13. The variable frequency controller of claim 5, further comprising:

and the CF card interface (105) is connected with the DSP chip (10) and is used for storing data into an external CF card or reading the data in the external CF card.

14. The variable frequency controller of claim 5, further comprising:

a nixie tube driving chip (106) and a nixie tube (107);

the nixie tube driving chip (106) is connected with the DSP chip (10) and is used for driving the nixie tube (107) to be turned on or turned off; the nixie tube (107) is used for displaying state information of the variable frequency controller.