CN217606273U - Real-time clock information reading circuit based on DSP chip and variable frequency controller - Google Patents
Real-time clock information reading circuit based on DSP chip and variable frequency controller Download PDFInfo
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- CN217606273U CN217606273U CN202221813825.1U CN202221813825U CN217606273U CN 217606273 U CN217606273 U CN 217606273U CN 202221813825 U CN202221813825 U CN 202221813825U CN 217606273 U CN217606273 U CN 217606273U
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Abstract
The utility model discloses a real-time clock information reads circuit and frequency conversion controller based on DSP chip, wherein, this real-time clock information reads the circuit and includes: a DSP chip and an I2C bus real-time clock chip; the I2C bus real-time clock chip is connected with the DSP chip and used for providing real-time clock information for the DSP chip. The utility model discloses can realize reading of real-time clock information in CPU starts the initialization process.
Description
Technical Field
The utility model relates to an electronic circuit field especially relates to a real-time clock information reads circuit and frequency conversion controller based on DSP chip.
Background
This section is intended to provide a background or context to the embodiments of the invention that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.
The DSP chip is used as a main control chip of the frequency converter, can realize various complex algorithms by utilizing an integrated program package, and has the advantage of short development period. In the prior art, when clock information is read, the clock information needs to be acquired by using an SPI bus or a LocalBus bus built in a DSP chip and a dedicated storage bus. However, this method needs to consume a large amount of data and address signal lines, occupies valuable external pins of the DSP chip, and meanwhile, needs to perform detailed processing on the length and arrangement position of the signal lines during the wiring process of the circuit board, which is prone to signal interference and causes errors in reading information.
Therefore, a real-time clock information reading scheme capable of overcoming the above problems is desired.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides an in provide a real-time clock information reading circuit based on DSP chip for realize reading of real-time clock information in CPU starts the initialization process, this real-time clock information reading circuit based on DSP chip includes: a DSP chip and an I2C bus real-time clock chip; the I2C bus real-time clock chip is connected with the DSP chip and used for providing real-time clock information for the DSP chip.
Furthermore, the I2C bus real-time clock chip is a PCF8563TS \5 chip; the DSP chip is a TMS320F28232 chip.
Further, the TMS320F28232 chip includes: SDAA data signal pin and SCLA clock signal pin; the PCF8563TS \5 chip comprises: SDA data signal pin and SCL clock signal pin; the SDAA data signal pin of the TMS320F28232 chip is connected with the SDA data signal pin of the PCF8563TS \ 5 chip; and the SCLA clock signal pin of the TMS320F28232 chip is connected with the SCL clock signal pin of the PCF8563TS \5 chip.
Further, the real-time clock information reading circuit based on the DSP chip further includes: and the quartz crystal resonator is connected with the PCF8563TS \5 chip and is used for providing time, date and clock correction information.
Further, the real-time clock information reading circuit based on the DSP chip further includes: and the button battery is connected with the PCF8563TS \5 chip and is used for supplying power to the PCF8563TS \5 chip when external power supply is interrupted.
The embodiment of the utility model provides an in still provide a frequency conversion controller for CPU starts reading of realizing real-time clock information in the initialization process, this frequency conversion controller includes: the real-time clock information reading circuit based on the DSP chip.
Further, the variable frequency controller further comprises: and the FPGA chip is connected with the DSP chip and is used for transmitting the control signals output by the DSP chip to a plurality of external frequency conversion devices in parallel.
Further, the variable frequency controller further comprises: and the external expansion board is connected with the FPGA chip and is used for expanding various field buses or Ethernet buses.
Further, the variable frequency controller further comprises: and the interrupt signal transmission interface is connected with the FPGA chip and is used for transmitting interrupt signals.
Further, the FPGA chip is used to extend any one of the following interfaces: RS485 bus interface, CAN bus interface, RS232 bus interface, SSI encoder signal interface, incremental encoder signal interface, digital input signal interface, digital output signal interface, analog input signal interface and analog output signal interface.
Further, the variable frequency controller further comprises: the USB interface is connected with the DSP chip and is used for communicating with external USB equipment; and the USB-TTL is connected with the DSP chip and is used for converting the USB data into TTL data.
Further, the variable frequency controller further comprises: and the CF card interface is connected with the DSP chip and used for storing data into an external CF card or reading data in the external CF card.
Further, the variable frequency controller further comprises: a nixie tube driving chip and a nixie tube; the digital tube driving chip is connected with the DSP chip and is used for driving the digital tube to be lightened or extinguished; the nixie tube is used for displaying the state information of the variable frequency controller.
Further, the variable frequency controller further comprises: and the RTC clock chip is connected with the DSP chip and used for providing a clock signal.
Further, the variable frequency controller further comprises: DDR memory and MMC memory; the DDR memory is connected with the DSP chip and used for storing memory data; and the MMC memory is connected with the DSP chip and used for storing data.
The embodiment of the utility model provides an in provide real-time clock information reading circuit and frequency conversion controller based on the DSP chip is connected thereby to provide real-time clock information to the DSP chip through I2C bus real-time clock chip and DSP chip to realize reading of real-time clock information in CPU starts the initialization process, come to calibrate the CPU clock.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts. In the drawings:
fig. 1 is a schematic diagram of a real-time clock information reading circuit based on a DSP chip according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a TMS320F28232 chip signal pin according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a PCF8563TS \5 chip signal pin according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a frequency conversion controller according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention are described in further detail below with reference to the accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention.
The embodiment of the utility model provides an in provide a real-time clock information reading circuit based on DSP chip, figure 1 is the embodiment of the utility model provides an in embodiment a real-time clock information reading circuit schematic diagram based on DSP chip, as shown in figure 1, this real-time clock information reading circuit includes: a DSP chip 10 and an I2C bus real-time clock chip 11;
the I2C bus real-time clock chip 11 is connected to the DSP chip 10, and is configured to provide real-time clock information to the DSP chip 10.
In an embodiment, in the real-time clock information reading circuit provided in the embodiment of the present invention, the I2C bus real-time clock chip 11 adopts a PCF8563TS \5 chip; the DSP chip 10 adopts a TMS320F28232 chip. The TMS320F28232 chip is a high-end DSP chip and can run a real-time operating system. The PCF8563TS \5 chip is an I2C bus real-time clock chip and can transmit real-time clock information to the DSP chip.
Fig. 2 shows a signal pin of a DSP chip provided in an embodiment of the present invention, and a definition of a part of the signal pin of the TMS320F28232 chip is shown in table 1. Fig. 3 shows a signal pin of a PCF8563TS \5 chip provided in an embodiment of the present invention, and a part of the signal pin of the PCF8563TS \5 chip is defined as shown in table 2.
TABLE 1
| Serial number | Pin number | Name (R) | Means of | |
| 1 | 74 | | Data signal | |
| 2 | 75 | SCLA | Clock signal |
TABLE 2
| Serial number | Pin number | Name (R) | Means of | |
| 1 | 1 | OSCI | Passive |
|
| 2 | 2 | OSCO | Passive |
|
| 3 | 3 | INT# | |
|
| 4 | 4 | | Power ground | |
| 5 | 5 | | Clock signal | |
| 6 | 6 | | Data signal | |
| 7 | 7 | CLKOUT | |
|
| 8 | 8 | VDD | Power supply positive |
In this embodiment, the TMS320F28232 chip includes: SDAA data signal pin and SCLA clock signal pin; the PCF8563TS \5 chip comprises: an SDA data signal pin and an SCL clock signal pin; the SDAA data signal pin of the TMS320F28232 chip is connected with the SDA data signal pin of the PCF8563TS \ 5 chip; the SCLA clock signal pin of the TMS320F28232 chip is connected with the SCL clock signal pin of the PCF8563TS \5 chip.
In this embodiment, the real-time clock information reading circuit based on the DSP chip further includes: and the quartz crystal resonator 12 is connected with the PCF8563TS \5 chip and is used for providing time, date and clock correction information.
In specific implementation, two ends of the quartz crystal resonator 12 are respectively connected with an OSCI passive crystal oscillator input pin and an OSCO passive crystal oscillator output pin of the PCF8563TS \5 chip. The quartz crystal resonator adopts 32.768kHz and provides accurate time date clock correction information for the PCF8563TS \5 chip, thereby reducing the clock jitter of the chip, reducing the clock drift and ensuring more accurate timing.
In this embodiment, the real-time clock information reading circuit based on the DSP chip further includes: and the two capacitors are respectively connected with an OSCI passive crystal oscillator input pin and an OSCO passive crystal oscillator output pin of the PCF8563TS \5 chip, and the capacitors can be 15pF capacitors and are used for filtering voltage fluctuation at two ends of the quartz crystal resonator.
In this embodiment, the real-time clock information reading circuit based on the DSP chip further includes: and the button battery 13 is connected with the PCF8563TS \5 chip and is used for supplying power to the PCF8563TS \5 chip when external power supply is interrupted.
When the PCF8563TS \5 chip is implemented concretely, the VDD pin of the PCF8563TS \5 chip is powered by the button cell and external power (3.3V) at the same time, and when the external 3.3V power supply is normal, the external 3.3V supplies power for the PCF8563TS \5 chip. When the external power supply is interrupted, the PCF8563TS \5 chip is powered by the button battery.
In this embodiment, the real-time clock information reading circuit based on the DSP chip further includes: the button cell comprises a first diode, a second diode and a resistor, wherein the first diode is connected between the VDD pin of the PCF8563TS \5 chip and the external 3.3V power supply, and the second diode is connected between the VDD pin of the PCF8563TS \ 5 chip and the button cell after being connected with the resistor. The resistor (which can be 1k omega) is used for limiting the output current of the button cell, and simultaneously, the voltage output by the button cell at a VDD pin is slightly lower than the power supply voltage of a 3.3V line, so that the function of preferentially supplying power by external 3.3V is realized. The working purpose of the diode is to prevent the button cell from being supplied with power by external 3.3V and also prevent the button cell from supplying power by external 3.3V, thereby realizing power supply isolation among 2 power supply circuits.
In this embodiment, the real-time clock information reading circuit based on the DSP chip further includes: the first capacitor and the second capacitor are respectively connected with a VDD pin of the PCF8563TS \5 chip. The capacitors are respectively 10uF and 0.1uF, so that a VDD power supply is more stable, the voltage fluctuation caused by sudden disappearance of 3.3V external power supply is reduced, the output current of the button battery is more stable, and the service life of the button battery is prolonged.
Fig. 4 is the embodiment of the utility model provides an in the embodiment of a frequency conversion controller sketch map, as shown in fig. 4, the embodiment of the utility model provides a frequency conversion controller still is provided, include: any one of the above real-time clock information reading circuits based on DSP chip.
In one embodiment, the present invention provides a frequency conversion controller, further comprising: and the FPGA chip 20 is connected with the DSP chip 10 and is used for transmitting the control signals output by the DSP chip 10 to a plurality of external frequency conversion devices in parallel.
In one embodiment, the present invention provides a variable frequency controller, further comprising: a USB interface 101 for communicating with an external USB device; and the USB-TTL102 is connected with the DSP chip 10 and is used for converting USB data into TTL data.
In one embodiment, the present invention provides a variable frequency controller, further comprising: DDR memory 104 and MMC memory 103; the DDR memory 104 is connected with the DSP chip 10 and used for storing memory data; and the MMC memory 103 is connected with the DSP chip 10 and used for storing data. Alternatively, the MMC memory may be an MMC card, through which onboard data storage is implemented, and both system check and encrypted data need to be stored in the MMC card. Because the read-write speed of the MMC card is higher than that of the CF card, the data which is held emergently can be stored in the MMC card. The embodiment of the utility model provides an among the frequency conversion controller, the DSP chip passes through DDR's mode extension RAM, has realized the storage and the operation of big batch memory data, supports current various mainstream DDR buses.
The embodiment of the utility model provides a frequency conversion controller can adopt 24V DC power supply, is connected with external power source through the power source 211 of bottom. Alternatively, the power interface 211 may be a power terminal.
In one embodiment, the present invention provides a frequency conversion controller, further comprising: and a CF card interface 105 connected to the DSP chip 10, for storing data in an external CF card or reading data in the external CF card. By expanding the DSP chip to the CF card storage function, system data or user data is stored in the CF card, and system and program upgrading can be conveniently carried out through the CF card.
In one embodiment, the present invention provides a variable frequency controller, further comprising: a nixie tube driving chip 106 and a nixie tube 107; the nixie tube driving chip 106 is connected with the DSP chip 10 and is used for driving the nixie tube 107 to be turned on or turned off; the nixie tube 107 is used for displaying the state information of the variable frequency controller. Optionally, the nixie tube 107 is an 8-bit LED nixie tube for displaying the current controller status, so that the user can conveniently determine the current software condition inside the controller. Alternatively, the nixie driver chip 106 may be a 74HC595D serial-to-parallel chip, which converts the serial signal of the DSP chip into a parallel signal for driving the LED nixie tube.
In one embodiment, the present invention provides a frequency conversion controller, further comprising: and the external expansion board 201 is connected with the FPGA chip 20 and is used for expanding various field buses or Ethernet buses. The FPGA chip expands the external expansion board through the internal bus, can realize the support of various field buses and a real-time Ethernet bus, and enhances the expansibility of the system.
In one embodiment, the present invention provides a frequency conversion controller, further comprising: and the interrupt signal transmission interface 212 is connected with the FPGA chip 20 and is used for transmitting interrupt signals.
In an embodiment, in the variable frequency controller provided in the embodiment of the present invention, the FPGA chip 20 may be further configured to extend any one of the following interfaces, i.e., a CAN bus interface 202, an RS485 bus interface 203, an RS232 bus interface 204, an SSI encoder signal interface 205, an incremental encoder signal interface 206, a digital input signal interface 208, a digital output signal interface 207, an analog input signal interface 210, an analog output signal interface 209, and a power interface 211. By expanding the data transmission interfaces of various communication protocols, the coordinated and unified operation of multiple communication protocols is realized. The FPGA chip expands an interrupt signal transmission interface for receiving or sending a quick interrupt signal in a plastic optical fiber or glass optical fiber mode, and data synchronization and signal synchronization among a plurality of controllers are achieved. The DSP chip also supports interrupt triggering functions to enable emergency processing of fast signals.
To sum up, the embodiment of the utility model provides a real-time clock information based on DSP chip reads circuit and frequency conversion controller is connected thereby through I2C bus real-time clock chip and DSP chip and provides real-time clock information to DSP chip to realize reading of real-time clock information in CPU starts the initialization process, come to calibrate the CPU clock. The embodiment of the utility model provides a only through 2 way signal lines, realized reading real-time clock information in the initialization process that CPU starts, come to calibrate the CPU clock. And after the circuit board stops supplying power, the button battery is adopted to supply power to the real-time clock chip, and the current time and date are stored. Meanwhile, the standby power is low, and the power supply time and the service life of the button battery are prolonged.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above-mentioned embodiments, which further illustrate the objects, technical solutions and advantages of the present invention in detail, it should be understood that the above-mentioned embodiments are only examples of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (14)
1. A real-time clock information reading circuit based on a DSP chip is characterized by comprising: a DSP chip (10) and an I2C bus real-time clock chip (11);
the I2C bus real-time clock chip (11) is connected with the DSP chip (10) and used for providing real-time clock information for the DSP chip (10).
2. The real-time clock information reading circuit based on DSP chip as set forth in claim 1, wherein the I2C bus real-time clock chip (11) is PCF8563TS \5 chip; the DSP chip (10) is a TMS320F28232 chip.
3. The DSP chip-based real-time clock information read circuit of claim 2, wherein the TMS320F28232 chip includes: SDAA data signal pin and SCLA clock signal pin; the PCF8563TS \5 chip comprises: SDA data signal pin and SCL clock signal pin;
the SDAA data signal pin of the TMS320F28232 chip is connected with the SDA data signal pin of the PCF8563TS \5 chip; and the SCLA clock signal pin of the TMS320F28232 chip is connected with the SCL clock signal pin of the PCF8563TS \5 chip.
4. The DSP chip based real-time clock information reading circuit of claim 2 further comprising:
and the quartz crystal resonator (12) is connected with the PCF8563TS \5 chip and is used for providing time, date and clock correction information.
5. The DSP chip based real-time clock information reading circuit of claim 2 further comprising:
and the button battery (13) is connected with the PCF8563TS \5 chip and is used for supplying power to the PCF8563TS \5 chip when the external power supply is interrupted.
6. A variable frequency controller, comprising: the DSP chip based real time clock information reading circuit of any one of claims 1 to 5.
7. The variable frequency controller of claim 6, further comprising:
and the FPGA chip (20) is connected with the DSP chip (10) and is used for transmitting the control signals output by the DSP chip (10) to a plurality of external frequency conversion devices in parallel.
8. The variable frequency controller of claim 7, further comprising:
and the external expansion board (201) is connected with the FPGA chip (20) and is used for expanding a field bus or an Ethernet bus.
9. The variable frequency controller of claim 7, further comprising:
and the interrupt signal transmission interface (212) is connected with the FPGA chip (20) and is used for transmitting an interrupt signal.
10. The variable frequency controller according to claim 7, wherein the FPGA chip (20) is configured to extend any one of the following interfaces: the device comprises a CAN bus interface (202), an RS485 bus interface (203), an RS232 bus interface (204), an SSI encoder signal interface (205), an incremental encoder signal interface (206), a digital quantity input signal interface (207), a digital quantity output signal interface (208), an analog quantity input signal interface (209), an analog quantity output signal interface (210) and a power supply interface (211).
11. The variable frequency controller of claim 6, further comprising:
a USB interface (101) for communicating with an external USB device;
and the USB-to-TTL module (102) is connected with the DSP chip (10) and is used for converting USB data into TTL data.
12. The variable frequency controller of claim 6, further comprising:
a DDR memory (104) and an MMC memory (103);
the DDR memory (104) is connected with the DSP chip (10) and used for storing memory data; the MMC memory (103) is connected with the DSP chip (10) and used for storing data.
13. The variable frequency controller of claim 6, further comprising:
and the CF card interface (105) is connected with the DSP chip (10) and is used for storing data into an external CF card or reading the data in the external CF card.
14. The variable frequency controller of claim 6, further comprising:
a nixie tube driving chip (106) and a nixie tube (107);
the nixie tube driving chip (106) is connected with the DSP chip (10) and is used for driving the nixie tube (107) to be turned on or turned off; the nixie tube (107) is used for displaying state information of the variable frequency controller.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202221813825.1U CN217606273U (en) | 2022-07-13 | 2022-07-13 | Real-time clock information reading circuit based on DSP chip and variable frequency controller |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202221813825.1U CN217606273U (en) | 2022-07-13 | 2022-07-13 | Real-time clock information reading circuit based on DSP chip and variable frequency controller |
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