CN217544611U - Integrated power semiconductor module packaging unit - Google Patents

Integrated power semiconductor module packaging unit Download PDF

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Publication number
CN217544611U
CN217544611U CN202220841894.7U CN202220841894U CN217544611U CN 217544611 U CN217544611 U CN 217544611U CN 202220841894 U CN202220841894 U CN 202220841894U CN 217544611 U CN217544611 U CN 217544611U
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China
Prior art keywords
terminal
power semiconductor
phase
semiconductor chips
group
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CN202220841894.7U
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Chinese (zh)
Inventor
朱楠
徐贺
史经奎
邓永辉
梅营
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Zhizhan Technology Shanghai Co ltd
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Zhizhan Technology Shanghai Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires

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  • Inverter Devices (AREA)

Abstract

The utility model provides an integrated power semiconductor module encapsulation unit belongs to the encapsulation technology field of semiconductor. The package unit includes: an insulating substrate; the direct-current power terminal, the first three-phase direct-current power terminal, the second three-phase direct-current power terminal, the third three-phase direct-current power terminal, the first three-phase alternating-current power terminal, the second three-phase alternating-current power terminal, the third three-phase alternating-current power terminal and the signal terminal are arranged on the front surface of the insulating substrate and extend out of the insulating substrate; the drain electrodes of the power semiconductor chips of one group are connected with the direct current power terminals, the source electrodes of the power semiconductor chips of one group are respectively connected with the drain electrodes of the power semiconductor chips of the other group in a one-to-one correspondence mode, and the source electrodes of the power semiconductor chips of the other group are respectively connected with the first three-phase direct current power terminals, the second three-phase direct current power terminals and the third three-phase direct current power terminals in a one-to-one correspondence mode. The packaging unit can reduce the parasitic inductance of the circuit.

Description

Integrated power semiconductor module packaging unit
Technical Field
The utility model relates to a packaging technology field of semiconductor specifically relates to an integrated power semiconductor module encapsulation unit.
Background
The existing low-power electronic converter generally adopts a power semiconductor device packaged by a patch or a direct-insert single tube. External electric connection is through printed circuit board or copper bar, and external heat dissipation needs to use insulating piece and radiator to realize electrical isolation, needs to use two-layer thermal interface material between insulating piece and the power device and between insulating piece and the radiator, and such structure has caused two technical defect: firstly, the heat dissipation thermal resistance of the chip is improved, and secondly, the paster or the direct-insertion single tube formed by the structure needs to be converged through a printed circuit board or a copper bar when being assembled, so that the parasitic inductance of the current conversion loop is not favorably reduced.
SUMMERY OF THE UTILITY MODEL
An object of the embodiments of the present invention is to provide an integrated power semiconductor module package unit, which can reduce the parasitic inductance of the circuit.
In order to achieve the above object, an embodiment of the present invention provides an integrated power semiconductor module packaging unit, including:
an insulating substrate;
the direct-current power terminal, the first three-phase direct-current power terminal, the second three-phase direct-current power terminal, the third three-phase direct-current power terminal, the first three-phase alternating-current power terminal, the second three-phase alternating-current power terminal, the third three-phase alternating-current power terminal and the signal terminal are arranged on the front surface of the insulating substrate and extend out of the insulating substrate;
the drain electrodes of the power semiconductor chips of one group are connected with the direct current power terminals, the source electrodes of the power semiconductor chips of one group are respectively connected with the drain electrodes of the power semiconductor chips of the other group in a one-to-one correspondence manner, the source electrodes of the power semiconductor chips of the other group are respectively connected with the first three-phase direct current power terminals, the second three-phase direct current power terminals and the third three-phase direct current power terminals in a one-to-one correspondence manner, the first three-phase alternating current power terminals, the second three-phase alternating current power terminals and the third three-phase alternating current power terminals are respectively connected with the drain electrodes of the power semiconductor chips of the other group in a one-to-one correspondence manner, and the grid electrodes and the source electrodes of the power semiconductor chips are connected with the signal terminals.
Optionally, the package unit includes a first copper sheet, which is disposed on the bottom of the power semiconductor chips of one group and connected to the drains of the power semiconductors of one group and the dc power terminals.
Optionally, the package unit further includes a plurality of second copper sheets, each of the second copper sheets is disposed at a bottom of one of the power semiconductor chips of another group, connected to a drain of the corresponding one of the power semiconductor chips of another group, and connected to the first three-phase ac power terminal, the second three-phase ac power terminal, the third three-phase ac power terminal, and the source of the power semiconductor chip of one group in a one-to-one correspondence manner.
Optionally, the sources of the power semiconductor chips of the other group are connected with the signal terminals through bonding wires;
the source electrodes of the other group of power semiconductor chips are connected with the first three-phase direct current terminal, the second three-phase direct current terminal and the third three-phase direct current terminal through bonding wires;
and the drain electrode of the other group of power semiconductor chips is connected with the first three-phase alternating current terminal, the second three-phase alternating current terminal and the third three-phase alternating current terminal through bonding wires.
Optionally, the first three-phase dc terminal, the second three-phase dc terminal and the third three-phase dc terminal set become dc output terminals.
Optionally, the first, second and third three-phase ac terminals are integrated as ac output terminals.
Optionally, the back surface of the insulating substrate is covered with a heat dissipation copper sheet.
Optionally, the package unit further includes a thermistor and a thermistor signal terminal, the thermistor is disposed on the insulating substrate, one end of the thermistor signal terminal extends out of the insulating substrate, and the other end of the thermistor signal terminal is connected to two ends of the thermistor.
Optionally, a thermoplastic sealant is disposed on the periphery of the insulating substrate.
Through the technical scheme, the utility model provides a pair of integrated power semiconductor module encapsulation unit is through setting up a plurality of power semiconductor chips on insulating substrate to through establishing ties a plurality of power semiconductor chips in order to obtain the power semiconductor chip group that integrates, compare in prior art, this encapsulation unit can reduce or avoid the use of copper bar, printed circuit board etc. that converges when circuit design, has reduced the parasitic inductance of circuit, and the insulating substrate that sets up simultaneously has also improved the radiating efficiency of circuit.
Other features and advantages of embodiments of the present invention will be described in detail in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention, but do not constitute a limitation of the embodiments of the invention. In the drawings:
fig. 1 is a top view of an integrated power semiconductor module packaging unit according to an embodiment of the present invention;
fig. 2 is a circuit diagram of an integrated power semiconductor module packaging unit according to an embodiment of the present invention;
fig. 3 is a top view of an integrated power semiconductor module packaging unit according to an embodiment of the present invention;
fig. 4 is a circuit diagram of an integrated power semiconductor module packaging unit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an integrated power semiconductor module package unit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an integrated power semiconductor module packaging unit according to an embodiment of the present invention.
Detailed Description
The following describes in detail embodiments of the present invention with reference to the accompanying drawings. It is to be understood that the description herein is only intended to illustrate and explain embodiments of the present invention, and is not intended to limit embodiments of the present invention.
In the embodiments of the present invention, unless otherwise specified, the use of directional terms such as "upper, lower, top, and bottom" is generally used with respect to the orientation shown in the drawings or the positional relationship between the components in the vertical, or gravitational direction.
In addition, if there is a description in the embodiments of the present invention referring to "first", "second", etc., the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments can be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or can not be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.
Fig. 1 is a top view of an integrated power semiconductor module package unit according to an embodiment of the present invention. Fig. 2 is a circuit diagram of an integrated power semiconductor module package unit according to an embodiment of the present invention. In fig. 1, the package unit may include an insulating substrate 01, a direct current power terminal DC +, a first three-phase direct current power terminal DC-U, a second three-phase direct current power terminal DC-V, a third three-phase direct current power terminal DC-W, a first three-phase alternating current power terminal U, a second three-phase alternating current power terminal V, a third three-phase alternating current power terminal W, signal terminals (S1, G1, S2, G2, S3, G3, S4, G4, S5, G5, S6, G6), at least two groups of power semiconductor chips (Q1, Q2, Q3, Q4, Q5, Q6). (the packaging units shown in FIGS. 1 and 2 are examples in which the number of power semiconductor chips per group is three)
Specifically, in fig. 1 and 2, the DC power terminal DC +, the first three-phase DC power terminal DC-U, the second three-phase DC power terminal DC-V, the third three-phase DC power terminal DC-W, the first three-phase ac power terminal U, the second three-phase ac power terminal V, the third three-phase ac power terminal W, and the signal terminals (S1, G1, S2, G2, S3, G3, S4, G4, S5, G5, S6, G6) may be disposed on the front surface of the insulating substrate 01 and extend out of the insulating substrate 01. The drains of the power semiconductor chips (Q1, Q3, Q5) of one group may be connected to DC +. The sources of the power semiconductor chips (Q1, Q3, Q5) of the one group may be connected to the drains of the power semiconductor chips (Q2, Q4, Q6) of the other group in a one-to-one correspondence, respectively. The source of each power semiconductor chip (Q2, Q4, Q6) of the other group may be connected to the first three-phase direct current power terminal DC-U, the second three-phase direct current power terminal DC-V, and the third three-phase direct current power terminal DC-W, respectively, in a one-to-one correspondence. The first three-phase ac power terminal U, the second three-phase ac power terminal V, and the third three-phase ac power terminal W are connected to drains of another group of power semiconductor chips (Q2, Q4, Q6) in a one-to-one correspondence. The gate and source of each power semiconductor chip (Q1, Q2, Q3, Q4, Q5, Q6) may be connected to a signal terminal (S1, G1, S2, G2, S3, G3, S4, G4, S5, G5, S6, G6).
Specifically, in fig. 1 and 2, the gate of the power semiconductor chip Q1 may be connected to the signal terminal G1. The drain of the power semiconductor chip Q1 may be connected to the direct current power terminal DC +. The drain of the power semiconductor chip Q1 may be connected to the first three-phase ac power terminal U and the signal terminal S1. The drain of the power semiconductor chip Q2 may be connected to the source of the power semiconductor chip Q1. The gate of the power semiconductor chip Q2 may be connected to the signal terminal G2. The source of the power semiconductor chip Q2 may be connected to the signal terminal S2 and the first three-phase direct current power terminal DC-U. The gate of the power semiconductor chip Q3 may be connected to the signal terminal G3. The drain of the power semiconductor chip Q3 may be connected to the direct current power terminal DC +. The source of the power semiconductor chip Q3 may be connected to the signal terminal S3 and the second three-phase ac power terminal V. The drain of the power semiconductor chip Q4 may be connected to the source of the power semiconductor chip Q3. The gate of the power semiconductor chip Q4 may be connected to the signal terminal G4. The source of the power semiconductor chip Q4 may be connected to the signal terminal S4 and the second three-phase direct-current power terminal DC-V. The drain of the power semiconductor chip Q5 may be connected to the direct current power terminal DC +. The gate of the power semiconductor chip Q5 may be connected to the signal terminal G5. The source of the power semiconductor chip Q5 may be connected to the signal terminal S5 and the third three-phase ac power terminal W. The drain of the power semiconductor chip Q6 may be connected to the source of the power semiconductor chip Q5. The gate of the power semiconductor chip Q6 may be connected to the signal terminal G6. The source of the power semiconductor chip Q6 may be connected to the signal terminal S6 and the third three-phase direct-current power terminal DC-W.
In one embodiment of the present invention, in order to facilitate the connection of the power semiconductor chip on the insulating substrate 01, the packaging unit may further include a first copper sheet 02. As shown in fig. 1, the first copper sheet 02 may be disposed at the bottom of the power semiconductor chips Q1, Q3, Q5, and connected to the drains of the power semiconductor chips Q1, Q3, Q5 and the DC power terminal DC +.
Similarly, the packaging unit may further include a plurality of second copper sheets 03. As shown in fig. 1, the second copper sheet 03 may be disposed on the bottom of the power semiconductor chips Q2, Q4, Q5, and connected to the drain of one of the corresponding power semiconductor chips Q2, Q4, Q5, and connected to the first three-phase ac power terminal U, the second three-phase ac power terminal V, the third three-phase ac power terminal W, and the sources of one group of power semiconductor chips Q1, Q3, Q5 in a one-to-one correspondence manner.
In an embodiment of the present invention, in order to avoid the increase of the thickness of the product caused by stacking the first copper sheet 02 and the second copper sheet 03, the connection between the power semiconductor chip and each terminal is ensured, and the source electrodes of the other group of power semiconductor chips Q2, Q4 and Q5 can be connected to the signal terminals S2, S4 and S6 through bonding wires. The sources of the other group of power semiconductor chips Q2, Q4, Q5 may also be connected with the first three-phase direct current terminal DC-U, the second three-phase direct current terminal DC-V, and the third three-phase direct current terminal DC-W, respectively, by bonding wires. Drains of the power semiconductor chips Q2, Q4, and Q5 of the other group may be connected to the first three-phase ac terminal U, the second three-phase ac terminal V, and the third three-phase ac terminal W, respectively, via bonding wires.
In order to accommodate the need for current or voltage conversion, in one embodiment of the present invention, the first three-phase DC terminal DC-U, the second three-phase DC terminal DC-V and the third three-phase DC terminal DC-W are integrated into a DC output terminal. The first three-phase ac terminal U, the second three-phase ac terminal V, and the third three-phase ac terminal W are integrated as ac output terminals. The packaged unit after integration may be as shown in fig. 3 and 4.
Since the material of the insulating substrate 01 is generally Al 2 O 3 DBC、AlN DBC、Si 3 N 4 AMB, and the like. These materials are easily deformed by heat during actual operation, and then in an embodiment of the present invention, the back surface of the insulating substrate 01 may be covered with a heat dissipation copper sheet (not shown in the figure). The radiating copper sheet can fix the insulating substrate 01 on one hand, and can increase the radiating efficiency on the other hand. In the practical implementation process, the heat dissipation installation of the packaging unit can be realized only by coating the heat dissipation silicone grease on the heat dissipation copper sheet. In addition, in order to maintain the stability and durability of the power semiconductor chip, the periphery of the insulating substrate 01 may also be provided with a thermoplastic molding compound. A three-dimensional view of the encapsulation unit may be as shown in fig. 5 and 6.
Since the conventional single power semiconductor chip has limited heat generation, the temperature of the single power semiconductor chip does not need to be monitored in an actual circuit. However, in this embodiment, since the plurality of power semiconductor chips are integrated so that the amount of heat generated from the package unit is greatly increased, the package unit further includes a thermistor R and thermosensitive signal terminals NTC1, NTC2 in order to facilitate monitoring of the temperature of the package unit. The thermistor is disposed on an insulating substrate 01. One end of each of the thermosensitive signal terminals NTC1 and NTC2 extends out of the insulating substrate 01, and the other end can be connected with two ends of the thermistor R.
Through the technical scheme, the utility model provides a pair of integrated power semiconductor module encapsulation unit is through setting up a plurality of power semiconductor chip on the insulating substrate to through establishing ties a plurality of power semiconductor chip and organize in order to obtain the power semiconductor chip that integrates, compare in prior art, this encapsulation unit can reduce or avoid the use of copper bar, printed circuit board etc. that converges when circuit design, has reduced the parasitic inductance of circuit, and the insulating substrate that sets up simultaneously has also improved the radiating efficiency of circuit.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims (9)

1. An integrated power semiconductor module package unit, characterized in that the package unit comprises:
an insulating substrate;
the direct-current power terminal, the first three-phase direct-current power terminal, the second three-phase direct-current power terminal, the third three-phase direct-current power terminal, the first three-phase alternating-current power terminal, the second three-phase alternating-current power terminal, the third three-phase alternating-current power terminal and the signal terminal are arranged on the front surface of the insulating substrate and extend out of the insulating substrate;
the drain electrodes of the power semiconductor chips of one group are connected with the direct current power terminals, the source electrodes of the power semiconductor chips of one group are respectively connected with the drain electrodes of the power semiconductor chips of the other group in a one-to-one correspondence manner, the source electrodes of the power semiconductor chips of the other group are respectively connected with the first three-phase direct current power terminals, the second three-phase direct current power terminals and the third three-phase direct current power terminals in a one-to-one correspondence manner, the first three-phase alternating current power terminals, the second three-phase alternating current power terminals and the third three-phase alternating current power terminals are respectively connected with the drain electrodes of the power semiconductor chips of the other group in a one-to-one correspondence manner, and the grid electrodes and the source electrodes of the power semiconductor chips are connected with the signal terminals.
2. The package unit according to claim 1, wherein the package unit comprises a first copper sheet, the bottom of the power semiconductor chips of one group is arranged, and the first copper sheet is connected with the drain electrodes of the power semiconductors of one group and the direct current power terminals.
3. The package unit according to claim 1, wherein the package unit further comprises a plurality of second copper sheets, each of the second copper sheets being disposed at a bottom of one of the power semiconductor chips of another group, connected to a drain of the corresponding one of the power semiconductor chips of another group, and connected to the first, second, and third three-phase ac power terminals, and sources of the power semiconductor chips of one group in a one-to-one correspondence.
4. The packaging unit according to claim 3, wherein the sources of the power semiconductor chips of the other group are connected to the signal terminals by bonding wires;
the source electrodes of the other group of power semiconductor chips are connected with the first three-phase direct current terminal, the second three-phase direct current terminal and the third three-phase direct current terminal through bonding wires;
and the drain electrode of the other group of power semiconductor chips is connected with the first three-phase alternating current terminal, the second three-phase alternating current terminal and the third three-phase alternating current terminal through bonding wires.
5. The packaging unit according to claim 1, wherein the first, second and third three-phase direct current terminals are configured as direct current output terminals.
6. The packaging unit according to claim 3, wherein the first three-phase alternating-current terminal, the second three-phase alternating-current terminal, and the third three-phase alternating-current terminal are integrated as alternating-current output terminals.
7. The packaging unit of claim 1, wherein the back side of the insulating substrate is covered with a heat sink copper sheet.
8. The package unit according to claim 1, further comprising a thermistor and a thermosensitive signal terminal, wherein the thermistor is disposed on the insulating substrate, one end of the thermosensitive signal terminal extends out of the insulating substrate, and the other end of the thermosensitive signal terminal is connected to both ends of the thermistor.
9. The packaging unit according to claim 1, wherein the periphery of the insulating substrate is provided with a thermoplastic seal.
CN202220841894.7U 2022-04-08 2022-04-08 Integrated power semiconductor module packaging unit Active CN217544611U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202220841894.7U CN217544611U (en) 2022-04-08 2022-04-08 Integrated power semiconductor module packaging unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202220841894.7U CN217544611U (en) 2022-04-08 2022-04-08 Integrated power semiconductor module packaging unit

Publications (1)

Publication Number Publication Date
CN217544611U true CN217544611U (en) 2022-10-04

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Country Status (1)

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