CN215578508U

CN215578508U - Semiconductor circuit having a plurality of transistors

Info

Publication number: CN215578508U
Application number: CN202121214259.8U
Authority: CN
Inventors: 左安超; 谢荣才; 王敏
Original assignee: Guangdong Huixin Semiconductor Co Ltd
Current assignee: Guangdong Huixin Semiconductor Co Ltd
Priority date: 2021-06-01
Filing date: 2021-06-01
Publication date: 2022-01-18
Anticipated expiration: 2031-06-01

Abstract

The utility model relates to a semiconductor circuit, comprising a heat dissipation substrate, a circuit wiring layer, a plurality of electronic elements, a plurality of pins and a sealing layer, wherein the sealing layer at least has two areas with different thicknesses, and the electronic elements with the surfaces higher than the height of the circuit wiring layer in the plurality of electronic elements are positioned in the area with the larger thickness in the sealing layer. The distance between the surface of the electronic element with larger thickness and the surface of the thicker area of the sealing layer is approximately the same as the distance between the surface of the electronic element with smaller thickness and the surface of the thinner area of the sealing layer due to larger power consumption, so that the consumption of the material of the sealing layer, such as resin, is saved under the requirement of ensuring the sealing strength of the sealing layer, and the cost is saved due to the fact that the consumption of the resin adopted by the area with relatively smaller thickness is less.

Description

Semiconductor circuit having a plurality of transistors

Technical Field

The utility model relates to a semiconductor circuit, and belongs to the technical field of semiconductor circuit application.

Background

A semiconductor circuit is a power-driven type product that combines power electronics and integrated circuit technology. The outer surface of a semiconductor circuit is generally encapsulated with a resin material formed by injection molding to form a sealing layer, and the circuit board and the electronic components inside are sealed, and the leads protrude from one side or both sides of the sealing layer. Most of the semiconductor circuits on the market are manufactured by an epoxy resin molding material and a packaging process. The heat conductivity of the plastic packaging material is lower than that of the plastic packaging material, the heat conductivity is generally about 1.5-2W/m-K, when a semiconductor circuit is designed, in order to simplify a plastic packaging process and beautify a product, designers generally design the outline of a sealing layer of a module into a square and smooth surface structure, the thickness of the sealing layer is consistent, but the height of an electronic element inside the module is not consistent with the surface height of the sealing layer, the height of the electronic element is longer than that of the sealing layer, and the height of the electronic element is longer than that of the sealing layer, so that the sealing layer is relatively thick, and the waste of materials for manufacturing the sealing layer is brought.

SUMMERY OF THE UTILITY MODEL

The technical problem to be solved by the utility model is to solve the problem of waste of materials for manufacturing the sealing layer caused by consistent thickness of the sealing layer in the using process of the existing semiconductor circuit.

Specifically, the present invention discloses a semiconductor circuit comprising:

the heat dissipation substrate comprises a mounting surface and a heat dissipation surface;

a circuit wiring layer provided on the mounting surface of the heat dissipation substrate, the circuit wiring layer being provided with a plurality of connection pads;

the electronic elements are arranged on the bonding pads of the circuit wiring layer, the electronic elements comprise power devices and driving chips, and the heights of the surfaces of the electronic elements relative to the circuit wiring layer are inconsistent;

the pins are arranged on at least one side of the heat dissipation substrate;

the sealing layer wraps one surface of the heat dissipation substrate provided with the electronic element, and one end of each pin is exposed out of the sealing layer;

wherein the sealing layer has at least two regions having different thicknesses, and the electronic element having a surface with a height higher than that of the circuit wiring layer among the plurality of electronic elements is located in the region having the larger thickness in the sealing layer.

Optionally, the semiconductor circuit further comprises an auxiliary heat spreader disposed between the circuit wiring layer and the at least one power device, the auxiliary heat spreader being located in a thicker region of the encapsulation layer.

Alternatively, the plurality of electronic components form the inverter circuit and the PFC circuit in a circuit wiring layer, and the power device mounted on the auxiliary heat sink is located in the PFC circuit.

Optionally, the power device includes a plurality of switching tubes and a plurality of freewheeling diodes, and the plurality of auxiliary radiators are respectively connected to the switching tubes and the freewheeling diodes of the PFC circuit.

Alternatively, the inverter circuit is located in a thinner region in the auxiliary heat sink, and the power device in the inverter circuit is not mounted with the auxiliary heat sink.

Optionally, the distances from the surface of the power device in the thinner and thicker regions of the sealing layer to the surface of the sealing layer are the same, both 1 mm to 7 mm.

Optionally, the semiconductor circuit further comprises a plurality of bonding wires connected between the plurality of electronic components, the circuit wiring layer, and the plurality of pins.

Optionally, the surface of the circuit wiring layer is further provided with a green oil layer for protection.

Alternatively, the insulating layer is made of a resin material, and the inside of the resin material is filled with a filler of alumina and aluminum carbide.

Optionally, the filler is angular, spherical, or a mixture of angular and spherical.

The semiconductor circuit of the present invention includes a heat dissipating substrate, a circuit wiring layer, a plurality of electronic components, a plurality of leads, and a sealing layer, wherein the sealing layer has at least two regions having different thicknesses, and the electronic component having a surface whose height from the circuit wiring layer is high among the plurality of electronic components is located in the region having a large thickness in the sealing layer. The distance between the surface of the electronic element with larger thickness and the surface of the thicker area of the sealing layer is approximately the same as the distance between the surface of the electronic element with smaller thickness and the surface of the thinner area of the sealing layer due to larger power consumption, so that the consumption of the material of the sealing layer, such as resin, is saved under the requirement of ensuring the sealing strength of the sealing layer, and the cost is saved due to the fact that the consumption of the resin adopted by the area with relatively smaller thickness is less.

Drawings

FIG. 1 is a cross-sectional view of a semiconductor circuit according to an embodiment of the present invention;

FIG. 2 is a schematic structural view of a heat dissipating substrate of a semiconductor circuit for mounting an electronic component according to an embodiment of the present invention;

FIG. 3 is a schematic view of a semiconductor circuit showing the internal circuit wiring layers and electronic components with portions of the encapsulating layer removed according to an embodiment of the present invention;

FIG. 4 is a simplified diagram of an internal circuit of a semiconductor circuit according to an embodiment of the present invention.

Reference numerals:

the driving circuit includes an auxiliary heat sink 001, a sealing layer 002, a first surface 0021, a second surface 0022, a circuit wiring layer 005, a connection pad 0051, a bonding wire 006, a heat dissipation substrate 008, a first IGBT009, a first freewheeling diode 010, a pin 100, a driving chip 104, a second IGBT208, and a second freewheeling diode 209.

Detailed Description

It is to be noted that the embodiments and features of the embodiments may be combined with each other without conflict in structure or function. The present invention will be described in detail below with reference to examples.

The semiconductor circuit provided by the utility model is a circuit module which integrates a power switch device, a high-voltage driving circuit and the like together and is sealed and packaged on the outer surface, and is widely applied to the field of power electronics, such as the fields of frequency converters of driving motors, various inversion voltages, variable frequency speed regulation, metallurgical machinery, electric traction, variable frequency household appliances and the like. The semiconductor circuit herein may be referred to by various other names, such as Modular Intelligent Power System (MIPS), Intelligent Power Module (IPM), or hybrid integrated circuit, Power semiconductor Module, Power Module, etc. In the following embodiments of the present invention, collectively referred to as a Modular Intelligent Power System (MIPS).

As shown in fig. 1 to 4, the MIPS provided by the present invention includes a heat dissipation substrate 008, a circuit wiring layer 005, a plurality of electronic elements, a plurality of pins 100, and a sealing layer 002.

The heat dissipating substrate 008 is made of a metal material, and includes an upper mounting surface and a lower heat dissipating surface, which may be a rectangular plate made of aluminum such as 1100, 5052, and the like.

An insulating layer (not shown) is provided on the heat dissipating substrate 008 to provide the circuit wiring layer 005 on the insulating layer, and electrical isolation between the circuit wiring layer 005 and the heat dissipating substrate 008 is achieved. The insulating layer is formed to cover at least one surface of the heat dissipating substrate 008, is made of a resin material such as epoxy resin, and is filled with a filler such as alumina and aluminum carbide to improve thermal conductivity. In order to increase the thermal conductivity, the shape of these fillers may be angular, and in order to avoid the risk of the fillers damaging the contact surfaces of the electronic components arranged on the surface thereof, the fillers may be spherical, angular, or a mixture of angular and spherical. The circuit wiring layer 005 may be formed by etching a copper foil or by printing a paste-like conductive medium, which may be a conductive material such as graphene, solder paste, or silver paste. A wiring of a circuit is formed on the circuit wiring layer 005, and a plurality of connection pads 0051 for connecting the wiring are provided for mounting an electronic element and the pin 100. The pins 100 are fixedly and electrically connected to a connection pad 0051 near the edge of the heat dissipation substrate 008, and have a function of inputting and outputting signals to and from an external circuit connected to the MIPS, in this embodiment, as shown in fig. 2 and 3, the plurality of pins 100 are led out from one side of the heat dissipation substrate 008, and may also be led out from two opposite sides of the heat dissipation substrate 008 in other implementations. The lead 100 is generally made of a metal such as copper, a nickel-tin alloy layer is formed on the surface of the copper by chemical plating and electroplating, the thickness of the alloy layer is generally 5 μm, and the copper can be protected from corrosion and oxidation by the plating layer and the solderability can be improved.

Further, a thin layer of green oil (not shown) may be disposed on the surface of the circuit wiring layer 005 to prevent damage caused by short circuit between the traces of the circuit wiring layer 005 and to prevent oxidation and contamination of the surface of the circuit wiring layer 005, thereby protecting the circuit wiring layer 005.

Electronic components are disposed on the connection pads 0051 of the circuit wiring layer 005, and the electronic components include a power device and a driving chip 104, wherein the power device includes a switching device such as an IGBT (Insulated Gate Bipolar Transistor) or a MOS (metal oxide semiconductor) and a freewheeling diode, and the power consumed by the operation of the power device is large and the amount of heat generated is large, so that the temperature during the operation of the MIPS is high relative to the room temperature. The electronic components also include passive devices such as resistors, capacitors, and the like. Different electronic components have different sizes due to their different power consumptions, for example, the first IGBT009, the first freewheeling diode 010, the second IGBT208 and the second freewheeling diode 209 as power devices, wherein the first IGBT009 and the first freewheeling diode 010 consume power more than the second IGBT208 and the second freewheeling diode 209, and thus the first IGBT009 and the first freewheeling diode 010 have larger sizes and thicknesses, and the second IGBT208 and the second freewheeling diode 209 have relatively smaller sizes and thicknesses, so that the surfaces of the first IGBT009 and the first freewheeling diode 010 are higher than those of the circuit wiring layer 005, and the surfaces of the second IGBT208 and the second freewheeling diode 209 are lower than those of the first IGBT009 and the first freewheeling diode 010.

The sealing layer 002 may be formed of a resin, and may be molded using a thermosetting resin by a transfer molding method, or may be molded using a thermoplastic resin by an injection molding method. The sealing layer 002 has two packaging structures, one is that the sealing layer 002 coats the upper surface and the lower surface of the heat dissipation substrate 008 and coats the electronic element arranged on the heat dissipation substrate 008, and also coats the pin 100 arranged at one end of the heat dissipation substrate 008, which is a full coating mode of the sealing layer 002; in another packaging method, the sealing layer 002 covers the upper surface of the heat dissipating substrate 008, i.e., covers the heat dissipating substrate 008, the electronic element, and the leads 100 disposed at one end of the heat dissipating substrate 008, and the lower surface of the heat dissipating substrate 008, i.e., the heat dissipating surface, is exposed out of the sealing layer 002, thereby forming a half-covered method of the sealing layer 002. Fig. 1 shows a full coating method of the sealing layer 002.

Compared with the solution in which the surface of the sealing layer 002 is flat, that is, the thickness of the sealing layer 002 is uniform, the sealing layer 002 of the MIPS of the embodiment of the present invention has at least two regions with different thicknesses on the surface, where an electronic element with a height higher than the circuit wiring layer 005 is located in a region with a larger thickness in the sealing layer 002. As shown in fig. 1, in the electronic component, the first IGBT009 and the first freewheeling diode 010 with a larger thickness are located in the region with a larger thickness, and the surface of the sealing layer 002 is the second surface 022, while the second IGBT208, the second freewheeling diode 209 and the resistor-capacitor element with a smaller thickness are located in the region with a smaller thickness, and the surface of the sealing layer 002 is the first surface 0021, so that the distance between the surface of the first IGBT009 and the first freewheeling diode 010 with a larger thickness and the second surface 02 of the sealing layer 002 is approximately equal to the distance between the surface of the second IGBT208 and the second freewheeling diode 209 with a smaller thickness and the first surface 0021 of the sealing layer 002, that is, although the thickness of the sealing layer 002 is different, the different surface is approximately equal to the thickness of the sealing of the surface of the electronic component, thereby saving the amount of the material of the sealing layer 002 such as resin while ensuring the sealing strength of the sealing layer 002, because the area with relatively thin thickness uses less resin, thus saving cost. Moreover, the distance between the surface of the IGBT with the larger thickness and the surface of the sealing layer 002 is approximately equal to the distance between the surface of the IGBT with the smaller thickness and the surface of the sealing layer 002 due to the different thicknesses of the sealing layer 002, and the electronic elements such as the IGBTs in the sealing layer 002 with the smaller thickness are more beneficial to heat dissipation of the electronic elements compared with the scheme that the thicknesses of the sealing layer 002 are consistent in the prior art, so that the temperature fluctuation of the electronic elements in the working process is not too large, and the working reliability and stability of the whole MIPS are improved.

In some embodiments of the present invention, as shown in fig. 1, the MIPS further includes a plurality of bonding wires 006, and the bonding wires 006 are connected between the plurality of electronic components, the circuit wiring layer 005, and the plurality of pins 100. For example, the bonding wire 006 may connect an electronic component and an electronic component, may also connect the electronic component and the circuit wiring layer 005, may also connect the electronic component and the lead 100, and may also connect the circuit wiring layer 005 and the lead 100. The electronic components are the first IGBT009 and the first freewheeling diode 010, the second IGBT208 and the second freewheeling diode 209, the driver chip, and others such as resistors, capacitors, and the like, mentioned in the above embodiments. The bonding wires 006 are typically gold wires, copper wires, hybrid gold and copper wires, 38um or thin aluminum wires below 38um, or thick aluminum wires above 100 um. As shown in fig. 1 in particular, the bonding wires 006 are connected between the electronic components, such as between the power devices, or between the power devices and the resistors or capacitors, in the space of the sealing layer from the surface of the electronic components to the surface of the sealing layer.

In some embodiments of the present invention, as shown in fig. 1 and 2, the MIPS further includes an auxiliary heat spreader 001, the auxiliary heat spreader 001 being disposed between the circuit wiring layer 005 and the at least one power device, the auxiliary heat spreader 001 being located at a thicker region in the sealing layer 002. Since some power devices such as the first IGBT009 and the first freewheeling diode 010 have large overcurrent, large power consumption and thus large heat generation amount, in order to facilitate heat dissipation thereof, an auxiliary heat sink 001 is further installed between the first IGBT009 and the first freewheeling diode 010 and the circuit wiring layer 005, as shown in fig. 1 and 2, and the auxiliary heat sink 001 is generally made of a metal material such as a copper alloy. The size that auxiliary heat sink 001 corresponds is unanimous with the size that the power device chip corresponds, and auxiliary heat sink 001's setting is equivalent to the height that has heightened power device for the distance greatly increased of power device's surface to circuit wiring layer 005, consequently the sealing layer 002 thickness that the region that is provided with auxiliary heat sink 001 corresponds needs to be increased, with the surface of guaranteeing these power device to highly satisfy certain demand on the surface of sealing layer 002, thereby guarantee the intensity requirement of sealing layer 002.

Further, in some embodiments of the present invention, as shown in fig. 1 to 4, a plurality of electronic components form an inverter circuit and a PFC (power factor correction) circuit in the circuit wiring layer 005, and power devices such as the first IGBT009 and the first freewheeling diode 010 mounted on the auxiliary heat sink 001 are located in the PFC circuit. The MIPS of this embodiment includes a PFC circuit in addition to a conventional inverter circuit, so that the application range of the MIPS can be expanded, and a power switch part related to the PFC circuit does not need to be provided in application. Since the switching tube of the PFC circuit is generally a single tube, the overcurrent thereof is much larger than each switching tube of the inverter circuit composed of 6 switching tubes, and thus the power consumption of the switching tube of the PFC circuit such as the first IGBT009 and the first freewheeling diode 010 is large, and thus the chip volume of the power device thereof is large, and for better heat dissipation, an auxiliary heat sink 001 is provided under the first IGBT009 and the first freewheeling diode 010 of the PFC circuit, so that the height of these electronic components with respect to the circuit wiring layer 005 is increased when these electronic components are mounted, and thus a region where the thickness of the sealing layer 002 is large is provided in the FPC circuit portion, while the power device of the inverter circuit such as the second IGBT208 and the second freewheeling diode 209 has a lower power consumption than the power device of the PFC circuit, and is small in size, and does not require the installation of the auxiliary heat sink 001, and thus the power device of the inverter circuit is directly mounted on the circuit wiring layer 005, and the height of the surface of the power device of the inverter circuit to the circuit wiring layer 005 is lower than the PFC circuit portion, therefore, a region where the sealing layer 002 is thin is provided in the inverter circuit portion.

In some embodiments of the present invention, the distance from the surface of the power device in the thinner and thicker regions of the sealing layer 002 to the surface of the sealing layer 002 is the same, both 1 mm to 7 mm. As shown in fig. 1, the first IGBT009 and the first freewheeling diode 010 of the PFC circuit are located in a thicker region of the sealing layer 002, with a surface thereof at a distance of 1 mm to 7 mm, such as typically 2.3 mm, from the second surface 0022 of the sealing layer 002. The second IGBT and the free wheel diode of the inverter are located in the thin region of the sealing layer 002, and the surface thereof is also located at a distance of 1 mm to 7 mm, such as 2.4 mm in general, from the first surface 0021 of the sealing layer 002, so that the electronic components in the two thick and thin regions of the sealing layer 002 are located at substantially the same distance from the surface of the sealing layer 002. In addition to meeting the sealing strength requirement of the sealing layer 002, the proper distance is selected to meet the installation requirement of the key and wire 006, because the key and wire are installed in the space of the distance, the key and wire are arranged in a curved arc when connecting different electronic elements, the height of the arc is required to meet the safety requirement, and therefore, the area for installing the bonding wire 006 needs a certain height. That is, the thickness uniformity of the region for mounting the bonding wire 006 is realized through the different regions of the sealing layer 002, which are thinner and thicker, so that the requirement of the sealing strength of the sealing layer 002 is met, and meanwhile, the requirement of mounting the bonding wire 006 is also met.

In some embodiments of the present invention, as shown in fig. 3 and 4, a circuit formed by the circuit wiring layer 005 and the electronic component disposed on the circuit wiring layer 005 includes a driving circuit and an inverter circuit, wherein the inverter circuit includes 6 switching tubes of upper and lower bridge arms, the driving circuit includes a driving chip 104, and the driving chip 104 is provided with at least one of an over-temperature protection switching circuit, an under-voltage protection circuit, an over-current protection circuit, and an over-voltage protection circuit. As shown in fig. 3, the 6 first IGBTs 009 and the first freewheeling diode 010 constitute an inverter circuit, and the driver chip 104 and the surrounding rc elements constitute a driver circuit. The inverter circuit mainly comprises 3 sets of inverter units of an upper bridge arm and a lower bridge arm, each inverter unit comprises two three-level transistors which are IGBTs (insulated gate bipolar transistors) or MOS (metal oxide semiconductor) transistors in a group in FIG. 4, a triode transistor 202 and a triode transistor 205 are in a group, a triode transistor 203 and a triode transistor 206 are in a group, a triode transistor 204 and a triode transistor 207 are in a group, each group of two triode transistors is divided into an upper bridge arm and a lower bridge arm, wherein the triode transistor 202 is an upper bridge arm, the triode transistor 205 is a lower bridge arm, the triode transistor 203 is an upper bridge arm, the triode transistor 206 is a lower bridge arm, the triode transistor 204 is an upper bridge arm, the triode transistor 207 is a lower bridge arm, a collector of the triode transistor 202 of the upper bridge arm is connected with a high-voltage input terminal VCC (17) of the module, an emitter of the triode transistor 202 of the upper bridge arm is connected with a collector of the triode transistor 205 of the lower bridge arm, an emitter of the triode transistor 205 of the lower bridge arm is connected with an outer pin U- (23) end of the module, the gates of the two triode transistors are connected with the driving chip 104, the emitter of the triode transistor 203 of the upper bridge arm is connected with the collector of the triode transistor 205 of the lower bridge arm, the emitter of the triode transistor 206 of the lower bridge arm is connected with the end of the pin V- (22) outside the module, the gates of the two triode transistors are connected with the driving chip 104, the emitter of the triode transistor 204 of the upper bridge arm is connected with the collector of the triode transistor 207 of the lower bridge arm, the emitter of the triode transistor 207 of the lower bridge arm is connected with the end of the pin W- (21) outside the module, and the gates of the two triode transistors are connected with the driving chip 104.

Further, the circuit further includes a PFC circuit, as shown in fig. 3, a second IGBT208 and a second freewheeling diode 209 are disposed on the left side of the circuit wiring layer 005, so as to form a full-bridge PFC circuit, so that the PFC circuit is integrated in the IPM module, thereby expanding the application of the IPM module.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the utility model and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the utility model.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims

1. A semiconductor circuit, comprising:

a plurality of electronic elements disposed on the pads of the circuit wiring layer, the plurality of electronic elements including power devices and driver chips, surfaces of the plurality of electronic elements having different heights with respect to the circuit wiring layer;

a plurality of pins disposed on at least one side of the heat-dissipating substrate;

wherein the sealing layer has at least two regions different in thickness, and among the plurality of electronic elements, electronic elements whose surfaces are high with respect to the circuit wiring layer are located in a region having a large thickness in the sealing layer.

2. The semiconductor circuit of claim 1, further comprising an auxiliary heat spreader disposed between the circuit wiring layer and at least one of the power devices, the auxiliary heat spreader being located in a thicker region of the encapsulation layer.

3. The semiconductor circuit according to claim 2, wherein the plurality of electronic components form an inverter circuit and a PFC circuit in the circuit wiring layer, and a power device mounted on the auxiliary heat sink is located in the PFC circuit.

4. The semiconductor circuit according to claim 3, wherein the power device includes a plurality of switching tubes and a plurality of freewheeling diodes, and the plurality of auxiliary heat sinks are respectively connected to the switching tubes and the freewheeling diodes of the PFC circuit.

5. The semiconductor circuit according to claim 3, wherein the inverter circuit is located in a thinner region in the auxiliary heat sink, and a power device in the inverter circuit is not mounted with the auxiliary heat sink.

6. The semiconductor circuit of claim 1, wherein the distances from the surface of the power device in the thinner and thicker regions of the sealing layer to the surface of the sealing layer are in the same range, both 1 mm to 7 mm.

7. The semiconductor circuit of claim 1, further comprising a plurality of bond wires connected between the plurality of electronic components, the circuit wiring layer, and the plurality of pins.

8. The semiconductor circuit according to claim 1, wherein a surface of the circuit wiring layer is further provided with a green oil layer for protection.