CN217467651U

CN217467651U - Back plate link detection device

Info

Publication number: CN217467651U
Application number: CN202220807684.6U
Authority: CN
Inventors: 陈海燕
Original assignee: Shenzhen Tong Tai Yi Information Technology Co ltd
Current assignee: Shenzhen Tong Tai Yi Information Technology Co ltd
Priority date: 2022-04-08
Filing date: 2022-04-08
Publication date: 2022-09-20
Anticipated expiration: 2032-04-08

Abstract

The utility model relates to a backboard link detection device, wherein, the high-speed signal link comprises a programmable logic chip, a signal interface group, a cable, a backboard to be tested, an interface loop board, a backboard to be tested, a cable, a signal interface group and a programmable logic chip in sequence to form a loop; the programmable logic chip forms a low-speed sideband signal link with the backboard to be tested by simulating SGPIO and I2C interface codes to observe the state of the LED indicator lamp of the backboard to be tested, and the low-speed sideband signal link sequentially comprises the programmable logic chip, a signal interface group, a cable, the backboard to be tested, the CPLD of the backboard to be tested and the LED indicator lamp of the backboard to be tested. The test board, the backboard to be tested, the interface loop board and the interconnection cable form a complete self-sending and self-receiving loop, the flexibility of CPLD logic design is utilized, the CPLD with low cost is adopted to design a transceiver test signal source, the test environment construction is simplified, the data to be analyzed or coded and decoded is processed by the CPLD, and the link loop test and the automatic feedback of the result are completed.

Description

Back plate link detection device

Technical Field

The utility model relates to a backplate technical field especially relates to a backplate link detection device.

Background

With the increasing development of new technologies such as cloud storage and big data, the demand for data storage is increased sharply, and the development and application of the back plate with multiple hard disk access interfaces are promoted. After the production and processing of the backplane are completed, in order to ensure the quality of the backplane, the backplane link needs to be detected.

At present, each manufacturer mainly adopts the complete machine environment for testing, which requires using the motherboard, matching with the CPU, the memory, the hard disk, the power supply, the display, the keyboard, etc., and running the corresponding test program. On one hand, the existing testing method needs to be matched with a series of accessories, so that the construction cost of the testing environment is increased; on the other hand, the time and the labor are consumed when the environment of the whole machine is matched, and the cost of the test time is increased due to multiple manual interventions of test program operation and result judgment; moreover, after the test is started, the test result of each interface needs to be defined artificially, which results in the reduction of the test accuracy.

SUMMERY OF THE UTILITY MODEL

In view of the above situation, it is necessary to provide a backplane link detection apparatus capable of reducing the test environment setup.

In order to solve the technical problem, the utility model discloses a technical scheme be: a backplane link detection apparatus, comprising:

a power interface;

the signal interface group is provided with at least one group, each group of signal interface group comprises at least two signal interfaces, an interface loop board is arranged on the backboard to be tested, and the signal interface group is connected with the backboard to be tested through an interconnection cable and the interface loop board;

the programmable logic chip is respectively connected with the power interface and the signal interface group, and a high-speed signal link and a low-speed sideband signal link are formed among the signal interface group, the programmable logic chip and the backboard to be tested;

the high-speed signal link sequentially comprises a programmable logic chip, a signal interface group, a cable, a backboard to be tested, an interface loop board, a backboard to be tested, a cable, a signal interface group and a programmable logic chip to form a loop;

the programmable logic chip forms the low-speed sideband signal link with the backboard to be tested by simulating the SGPIO and I2C interface codes to observe the state of the LED indicator lamp of the backboard to be tested, the low-speed sideband signal link sequentially comprises the programmable logic chip, a signal interface group, a cable, the backboard to be tested, the CPLD of the backboard to be tested and the LED indicator lamp of the backboard to be tested, and one signal interface in the signal interface group transmits an SGPIO signal and the other signal interface transmits an I2C signal.

Further, the signal interface group comprises at least one group of SFF-8643 interfaces and SFF-8654 interfaces.

Further, the signal interface is a hot plug interface.

Further, the high-speed signal link further comprises a signal conditioning circuit.

Further, the signal conditioning circuit comprises a first-order RC high-pass filter consisting of coupling capacitors.

Furthermore, the programmable logic chip comprises a signal source generating module, a signal sending module, a signal receiving module and a test result feedback module.

Further, the test result feedback module comprises a pass status light and a fault status light.

Further, the power supply interface is consistent with the power supply interface of the backboard to be tested.

The beneficial effects of the utility model reside in that: the test board, the backboard to be tested, the interface loop board and the interconnection cable form a complete self-sending and self-receiving loop, the flexibility of CPLD logic design is utilized, the CPLD with low cost is adopted to design a transceiver test signal source, the test environment construction is simplified, the data to be analyzed or coded and decoded is processed by the CPLD, and the link loop test and the automatic feedback of the result are completed.

Drawings

Fig. 1 is a schematic structural diagram of a backplane link detection apparatus according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a programmable logic chip of a backplane link detection apparatus according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a signal conditioning circuit of a backplane link detection apparatus according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a high-speed signal link of a backplane link detection device according to an embodiment of the present invention

Fig. 5 is a schematic structural diagram of a low-speed sideband signal link of a backplane link detection apparatus according to an embodiment of the present invention.

Description of reference numerals:

100. a power interface; 200. a signal interface group; 210. SFF-8643 interface;

220. an SFF-8654 interface; 300. a programmable logic chip; 310. a signal source generating module;

320. a signal transmitting module; 330. a signal receiving module; 340. a test result feedback module;

341. a pass status light; 342. a fault status light; 400. a signal conditioning circuit;

500. a backboard to be tested; 510. an interface loop plate; 520. a power supply interface; 530. an LED indicator light;

540. a backplane interface group.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the following description, taken in conjunction with the accompanying drawings and embodiments, will explain the present invention in further detail. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.

Referring to fig. 1 to 5, a backplane link detection apparatus includes:

a power supply interface 100;

the signal interface group 200, the signal interface group 200 is provided with at least one group, each group of signal interface group 200 includes at least two signal interfaces, the backplane 500 to be tested is provided with an interface loop board 510, and the signal interface group 200 is connected with the backplane 500 to be tested through the interface loop board 510 and the interconnection cable;

the programmable logic chip 300 is respectively connected with the power interface 100 and the signal interface group 200, and a high-speed signal link and a low-speed sideband signal link are formed among the signal interface group 200, the programmable logic chip 300 and the backboard 500 to be tested;

the high-speed signal link sequentially comprises a programmable logic chip 300, a signal interface group 200, a cable, a backboard 500 to be tested, an interface loop board 510 (through TX-RX loop), the backboard 500 to be tested, the cable, the signal interface group 200 and the programmable logic chip 300 to form a loop;

the programmable logic chip 300 forms a low-speed sideband signal link with the backboard 500 to be tested through simulating an SGPIO and I2C interface code to observe the state of an LED indicator light of the backboard 500 to be tested, the low-speed sideband signal link sequentially comprises the programmable logic chip 300, a signal interface group 200, a cable, the backboard 500 to be tested, a CPLD of the backboard 500 to be tested and the LED indicator light of the backboard 500 to be tested, and one signal interface in the signal interface group 200 transmits an SGPIO signal and the other signal interface transmits an I2C signal.

The test board, the backboard 500 to be tested, the interface loop board 510 and the interconnection cable form a complete self-sending and self-receiving loop, the flexibility of the logic design of the CPLD (Complex programmable logic device) is utilized, the transceiver test signal source is designed by adopting the CPLD with low cost, the test environment is simplified to be built, the data to be analyzed or to be coded and decoded is processed by the CPLD, and the link loop test and the automatic result feedback are completed. And the self-loop transceiver carries out data transmission in a communication mode, thereby simplifying the testing steps and shortening the testing time cost. The signal interface set 200 is at least one set, so that when a plurality of signal interface sets 200 are arranged, a plurality of backplates 500 to be tested can be tested conveniently and simultaneously.

The signal interface high-speed signal of the backplane 500 to be tested is a PCIe signal (usually from a slimas interface SFF-8654) and a SAS/SATA signal (usually from a minisas interface SFF-8643), the I2C and the SGPIO signal are low-speed sideband signals of the two interfaces (SFF-8654 interface and SFF-8643 interface), respectively, and the programmable logic chip analog transceiver processes the signal in the high-speed signal link (PCIe, SAS, SATA signal link) on one hand and processes the signal in the low-speed signal link (I2C, SGPIO signal link) on the other hand.

Referring to fig. 1, the signal interface set 200 includes at least one set of SFF-8643 interfaces 210 and SFF-8654 interfaces 220. The SFF-8643 interface 210 and the SFF-8654 interface 220 are mainstream interfaces in the market, and have mature technology and stable performance. It is understood that the backplane interface set 540 of the backplane 500 to be tested corresponds to the signal interface set 200, that is, when the signal interface set 200 has a set of SFF-8643 interfaces 210 and SFF-8654 interfaces 220, the backplane interface set 540 also has a set of corresponding SFF-8643 interfaces and SFF-8654 interfaces. Preferably, the signal interface 200 is a hot plug interface. The hot plug interface is convenient for replacing the interface type, and even if the number of the test board signal interfaces 200 cannot completely cover the backboard, the test can be quickly completed by replacing the interface interconnection cable through the hot plug.

Referring to fig. 1, the high-speed signal link includes a signal conditioning circuit 400. The signal conditioning circuit 400 is introduced to solve the problem of waveform distortion in the link test with the coupling capacitor, and is also suitable for the link test without the coupling capacitor. The signal conditioning circuit between the TX-RX loop link of the high-speed interface can be set according to the existence or non-existence of the serial coupling capacitor on the back plate, and no serial coupling capacitor is arranged between PCIe signals of the SFF-8654 interface of the back plate to be tested, so that only SAS/SATA signals of SFF-8643 are subjected to signal conditioning; through the RC parameter setting of the signal conditioning circuit, the analog transceiver can carry out the on-off test of the high-speed link without high frequency.

Referring to fig. 1 and 3, the signal conditioning circuit 400 includes a first-order RC high-pass filter formed by coupling capacitors. The CPLD is adopted to simplify and design the transceiver, and the transceiving signals of the transceiver are distorted due to the series connection of the coupling capacitors through the differential link of the backboard 500 to be tested, so that a first-order RC high-pass filter is formed by utilizing the coupling capacitor body. And setting a cut-off frequency according to the CPLD clock frequency so as to obtain a proper RC filtering parameter. If the target frequency is 31.85kHz, the cut-off frequency is set to be 3.185kHz, and the value of R is 10k by setting the series capacitance to be 5nf, the low-frequency component is filtered at the moment, and the acquisition of the target signal is not influenced. Note that, according to the distortion-free transmission condition, if the CPLD clock frequency is f0, the target frequency is equal to or less than f 0/2.

Referring to fig. 2, the programmable logic chip 300 includes a signal source generating module 310, a signal transmitting module 320, a signal receiving module 330, and a test result feedback module 340.

Referring to fig. 1 and 2, the test result feedback module 340 includes a pass status light 341 and a fail status light 342. The feedback test result of the passing state is reliable and quick.

In particular, the power interface 100 is identical to the power interface 520 of the backplane 500 to be tested. The test board power interface 100 is consistent with the power interface 520 of the backplane 500 to be tested, so that the backplane 500 to be tested can be used for adapting the power supply without introducing a new adapting power supply.

To sum up, the utility model provides a pair of backplate link detection device surveys test panel, the backplate that awaits measuring, interface return ring board and interconnection cable constitute complete spontaneous self-receiving return circuit, utilizes the flexibility of CPLD logic design, adopts low-cost CPLD design transceiver test signal source, simplifies test environment and builds, handles the data that needs analysis or need compile, decode through CPLD, accomplishes link return ring test and result automatic feedback. And the self-loop transceiver carries out data transmission in a communication mode, thereby simplifying the testing steps and shortening the testing time cost.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and although the present invention has been disclosed with reference to the preferred embodiment, it is not intended to limit the present invention, and any person skilled in the art can make modifications or changes to equivalent embodiments with equivalent changes when using the technical contents disclosed above without departing from the technical scope of the present invention, and any simple modifications, equivalent changes and modifications made to the above embodiments by the technical matters of the present invention are all within the scope of the technical solution of the present invention.

Claims

1. A backplane link detection apparatus, comprising:

a power interface;

2. The backplane link detection apparatus of claim 1, wherein the set of signal interfaces comprises at least one of a set of SFF-8643 interfaces and a set of SFF-8654 interfaces.

3. The backplane link detection apparatus of claim 2, wherein the high-speed signal link further comprises signal conditioning circuitry.

4. The backplane link detection apparatus of claim 3, wherein the signal conditioning circuit comprises a first-order RC high-pass filter comprising coupling capacitors.

5. The apparatus of claim 1, wherein the signal interface is a hot plug interface.

6. The backplane link detection device according to claim 1, wherein the programmable logic chip comprises a signal source generation module, a signal transmission module, a signal reception module, and a test result feedback module.

7. The backplane link detection apparatus of claim 6, wherein the test result feedback module comprises a pass status light and a fail status light.

8. The backplane link detection apparatus of claim 1, wherein the power interface is consistent with a power interface of the backplane to be tested.