CN217034696U - FPGA reset circuit and frequency conversion equipment - Google Patents

Abstract

The utility model discloses an FPGA reset circuit and frequency conversion equipment. The FPGA circuit is used for outputting a control signal to the self-reset circuit after the upgrade program is completely burned, and the self-reset circuit is used for outputting a reset signal to the FPGA circuit according to the control signal so as to control the FPGA circuit to reset. According to the utility model, the reset signal is output from the reset circuit to the reset configuration end of the FPGA circuit to trigger the FPGA circuit to automatically reset, so that the power-off-free upgrading program is completed. The problem of unable power on-off resets when the product is upgraded is solved.

Description

FPGA reset circuit and frequency conversion equipment

technical field

The utility model relates to a frequency converter, in particular to an FPGA reset circuit and a frequency conversion device.

Background technique

As the application scenarios of inverter products continue to upgrade and change, customers have more and more requirements for the functions and performance of inverter products. In order to meet customer needs, software upgrades to frequency converters are inevitable. In the normal software upgrade process of the inverter, we need to power on and off the inverter at least once after the software is upgraded to make our newly upgraded software take effect. This process is similar to patching our personal PC software or upgrade.

In some applications with higher requirements, in order to ensure safety or continuous production, we do not support or allow us to re-power on and off the inverter and other equipment. In the existing solution, an MCU chip with an internal self-reset function can be selected, but this situation limits the selection of the MCU and brings many limitations to the product design.

Utility model content

The main purpose of the utility model is to provide an FPGA reset circuit and a frequency conversion device, which are intended to realize uninterrupted power reset.

In order to achieve the above purpose, the utility model proposes a FPGA reset circuit, the FPGA reset circuit includes:

Burning interface, used to connect with the host computer;

The FPGA circuit has a communication terminal, a control terminal and a reset configuration terminal, and the communication terminal of the FPGA circuit is electrically connected to the programming interface;

A self-reset circuit has a controlled end and an output end, the controlled end of the self-reset circuit is connected to the control end of the FPGA circuit, and the output end of the self-reset circuit is connected to the reset configuration end of the FPGA circuit;

The FPGA circuit is used to output a control signal to the self-reset circuit after the upgrade program is burned, and the self-reset circuit is used to output a reset signal to the FPGA circuit according to the control signal to control the FPGA circuit reset.

In one embodiment, the FPGA circuit includes an FPGA chip and a communication circuit;

The FPGA chip has a first communication end, a control end and a reset configuration end, the communication circuit has a first communication end and a second communication end, and the first communication end of the communication circuit is the communication end of the FPGA circuit, The second communication end of the communication circuit is connected to the first communication end of the FPGA chip;

The control terminal of the FPGA chip is the control terminal of the FPGA circuit, and the reset configuration terminal of the FPGA chip is the reset configuration terminal of the FPGA circuit.

In one embodiment, the FPGA circuit further includes a memory;

The FPGA chip further has a second communication end, and the second communication end of the FPGA chip is electrically connected to the memory, and the memory is used for storing the upgrade program.

In one embodiment, the self-reset circuit includes a reset chip and a logic circuit;

The reset chip has a first voltage input terminal, a controlled terminal and a first output terminal, the logic circuit has a first input terminal, a second input terminal and an output terminal, and the first input terminal of the logic circuit is connected to the The control terminal of the FPGA circuit is connected, and the second input terminal of the logic circuit is used to access the first power supply voltage;

The first voltage input terminal of the reset chip is used to connect to the first power supply voltage, the controlled terminal of the reset chip is connected to the output terminal of the logic circuit, and the first output terminal of the reset chip is connected to the FPGA The reset configuration terminal of the circuit is connected;

The logic circuit is used for outputting a first voltage signal under the control of the control signal, and the reset chip is used for outputting a reset signal according to the first voltage signal; the reset chip is also used for the first voltage input terminal A reset signal is output when the first power supply voltage is not connected.

In one embodiment, the self-reset circuit further includes a first voltage divider circuit;

The first voltage divider circuit has a first input end, a second input end and an output end, the first input end of the first voltage divider circuit is used to connect to the first supply voltage, and the first voltage divider circuit has a The second input terminal is connected to the control terminal of the FPGA chip, and the output terminal of the first voltage divider circuit is connected to the first input terminal of the logic circuit;

The first voltage divider circuit is used to keep the voltage output from the control terminal of the FPGA circuit stable when the FPGA reset circuit is powered on or powered off.

In one embodiment, the reset chip further has a second voltage input terminal and a second output terminal;

The second voltage input end of the reset chip is used for connecting to a second power supply voltage, and the second output end of the reset chip is used for connecting with the second input end of the logic circuit;

The reset chip is further used for outputting a second voltage signal to the second input terminal of the logic circuit when the second voltage input terminal is not connected to the second power supply voltage, and the logic circuit is further used for according to the second voltage The signal outputs a first voltage signal.

In one embodiment, the self-reset circuit further includes a second voltage divider circuit;

The second voltage divider circuit has a first input end, a second input end and an output end, the first input end of the second voltage divider circuit is used to connect to the first supply voltage, and the second voltage divider circuit has a The second input terminal is connected to the second output terminal of the reset chip, and the output terminal of the second voltage divider circuit is connected to the second input terminal of the logic circuit;

The second voltage divider circuit is used to keep the voltage output by the second output terminal of the reset chip stable when the FPGA reset circuit is powered on or powered off.

The present invention also provides a frequency conversion device, the frequency conversion device includes the above-mentioned FPGA reset circuit.

The utility model also proposes a FPGA reset method, which is applied to the above-mentioned frequency conversion equipment, and the FPGA reset method includes:

After the upgrade program is burned, the control terminal of the FPGA circuit outputs a control signal to the controlled terminal of the self-reset circuit;

After receiving the control signal, the self-reset circuit outputs the reset signal to the reset configuration terminal of the FPGA circuit through the output terminal;

The FPGA circuit resets after receiving the reset signal.

In one embodiment, after receiving the control signal, the self-reset circuit outputs a reset signal to the reset configuration terminal of the FPGA circuit through the output terminal, specifically:

The logic circuit outputs a first voltage signal after receiving the control signal;

The reset chip outputs a reset signal according to the first voltage signal.

The utility model uses the FPGA circuit to output the control signal to the self-reset circuit after the upgrade program is burned, and triggers the automatic reset of the FPGA circuit through the self-reset circuit outputting the reset signal to the reset configuration terminal of the FPGA circuit to complete the upgrade program without power failure. It is not necessary to control the power-on and power-off of the FPGA reset circuit to trigger the reset of the FPGA circuit, which solves the problem that power-on and power-off cannot be performed to reset the product when the product is upgraded.

Description of drawings

In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are just some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can also be obtained based on the structures shown in these drawings without any creative effort.

Fig. 1 is the structural representation of the utility model FPGA reset circuit;

Fig. 2 is the structural representation of the utility model FPGA reset circuit;

Fig. 3 is the logic state table of the utility model FPGA reset circuit;

4 is a schematic flowchart of the FPGA reset method of the present invention;

FIG. 5 is a schematic flowchart of an embodiment of an FPGA reset method of the present invention.

The realization, functional characteristics and advantages of the purpose of the present utility model will be further described with reference to the accompanying drawings in conjunction with the embodiments.

Detailed ways

The technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, not all of them. Example. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the difference between the various components under a certain posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly.

In addition, the descriptions involving "first", "second", etc. in the present invention are only for description purposes, and should not be understood as indicating or implying their relative importance or implicitly indicating the number of indicated technical features. Thus, a feature delimited with "first", "second" may expressly or implicitly include at least one of that feature. In addition, the technical solutions between the various embodiments can be combined with each other, but must be based on the realization by those of ordinary skill in the art. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that the combination of such technical solutions does not exist. , is not within the scope of protection required by the present utility model.

Referring to FIG. 1 , the present invention proposes an FPGA reset circuit. The FPGA reset circuit includes a programming interface 10 , an FPGA circuit 20 and a self-reset circuit 30 .

The programming interface 10 is used to connect with the upper computer.

The FPGA circuit 20 has a communication terminal, a control terminal and a reset configuration terminal, and the communication terminal of the FPGA circuit 20 is electrically connected to the programming interface 10 .

The self-reset circuit 30 has a controlled terminal and an output terminal. The controlled terminal of the self-reset circuit 30 is connected to the control terminal of the FPGA circuit 20 . The output terminal of the self-reset circuit 30 is connected to the reset terminal of the FPGA circuit 20 . Configuration side connection.

The FPGA circuit 20 is used to output a control signal to the self-reset circuit 30 after the upgrade program is burned, and the self-reset circuit 30 is used to output a reset signal to the FPGA circuit 20 according to the control signal to control The FPGA circuit 20 is reset.

In the normal operation state of the FPGA reset circuit, the control terminal of the FPGA circuit 20 outputs a high level to the controlled terminal of the self-reset circuit 30 , and the output terminal of the self-reset circuit 30 outputs a high level to the reset configuration terminal of the FPGA circuit 20 at this time. , the FPGA circuit 20 does not start self-resetting. When the FPGA circuit 20 needs to be upgraded, the host computer writes the upgrade program to the FPGA circuit 20 through the programming interface 10. After the upgrade program is programmed, the FPGA circuit 20 outputs a low level through the control terminal to the controlled terminal of the self-reset circuit 30, At this time, the self-reset circuit 30 outputs a low level to the reset configuration terminal of the FPGA circuit 20 through the output terminal, triggering the reset of the FPGA circuit 20, the reloading program starts to run, and the upgrade procedure without power failure is completed.

The utility model uses the FPGA circuit to output the control signal to the self-reset circuit after the upgrade program is burned, and triggers the automatic reset of the FPGA circuit through the self-reset circuit outputting the reset signal to the reset configuration terminal of the FPGA circuit to complete the upgrade program without power failure. It is not necessary to control the power-on and power-off of the FPGA reset circuit to trigger the reset of the FPGA circuit, which solves the problem that power-on and power-off cannot be performed to reset the product when the product is upgraded.

In one embodiment, the FPGA circuit 20 includes an FPGA chip U1 and a communication circuit 21 .

The FPGA chip U1 has a first communication end, a control end and a reset configuration end, the communication circuit 21 has a first communication end and a second communication end, and the first communication end of the communication circuit 21 is the FPGA circuit 20 The second communication end of the communication circuit 21 is connected to the first communication end of the FPGA chip U1.

The control terminal of the FPGA chip U1 is the control terminal of the FPGA circuit 20 , and the reset configuration terminal of the FPGA chip U1 is the reset configuration terminal of the FPGA circuit 20 .

In this embodiment, the communication circuit 21 is used to perform signal conversion, so that the FPGA chip U1 and the host computer can communicate normally, and the upgrade program programming is completed.

In one embodiment, the FPGA circuit 20 further includes a memory U3.

The FPGA chip U1 further has a second communication terminal, and the second communication terminal of the FPGA chip U1 is electrically connected to the memory U3, and the memory U3 is used for storing the upgrade program.

In this embodiment, the upgrade program of the FPGA chip U1 is stored by the memory U3, and the FPGA chip U1 obtains the upgrade program from the memory U3 to perform the upgrade. It is more stable to store the upgrade program in the storage U3, and avoid loss or damage of the upgrade program caused by other data overwriting or modification.

Referring to FIG. 2 and FIG. 3 , in one embodiment, the self-reset circuit 30 includes a reset chip U2 and a logic circuit 31 .

The reset chip U2 has a first voltage input end, a controlled end and a first output end, the logic circuit 31 has a first input end, a second input end and an output end, the first input end of the logic circuit 31 It is connected to the control terminal of the FPGA circuit 20, and the second input terminal of the logic circuit 31 is used to access the first power supply voltage.

The first voltage input terminal of the reset chip U2 is used to connect to the first power supply voltage, the controlled terminal of the reset chip U2 is connected to the output terminal of the logic circuit 31, and the first output terminal of the reset chip U2 It is connected to the reset configuration terminal of the FPGA circuit 20 .

The logic circuit 31 is used to output a first voltage signal under the control of the control signal, and the reset chip U2 is used to output a reset signal according to the first voltage signal; the reset chip U2 is also used to The reset signal is output when the voltage input terminal is not connected to the first power supply voltage.

In the above embodiment, the reset chip U2 may be an ADM708ARZ chip, or other ARM or DSP chips. The logic circuit 31 can select the OR gate U4. The self-reset circuit 30 further includes a fifth resistor R5. The input end of the fifth resistor R5 is connected to the first output end of the reset chip U2 , and the output end of the fifth resistor R5 is connected to the reset configuration end of the FPGA circuit 20 .

In the normal operation state of the FPGA reset circuit, the control terminal of the FPGA circuit 20 outputs a high level to the first input terminal of the logic circuit 31. At this time, the first input terminal and the second input terminal of the logic circuit 31 are both high level. The logic circuit 31 outputs a high level to the controlled terminal of the reset chip U2, the first output terminal of the reset chip U2 outputs a high level to the FPGA circuit 20, and the FPGA circuit 20 does not start self-resetting. When the FPGA circuit 20 needs to be upgraded, the host computer writes the upgrade program to the FPGA circuit 20 through the programming interface 10 . After the upgrade program is programmed, the FPGA circuit 20 outputs a low level to the first input terminal of the logic circuit 31 through the control terminal, and at this time, the logic circuit 31 outputs a low level to the controlled terminal of the reset chip U2. When the low level output by the FPGA circuit 20 is greater than 150ns, the first output terminal of the reset chip U2 is triggered to output a low level of 200ms, and the FPGA circuit 20 is reset to a low level through the current limiting resistor R5, thereby triggering the FPGA circuit 20 reset. When the low level output by the first output terminal of the reset chip U2 changes to a high level, the reset of the FPGA circuit 20 is completed, the reloading program starts to run, and the upgrade program without power failure is completed.

The self-reset circuit 30 also has the function of monitoring the abnormal reset of the power supply. When the first voltage input terminal of the reset chip U2 is not connected to the first power supply voltage, the reset chip U2 outputs a low level to the reset configuration terminal of the FPGA circuit 20 to trigger the reset of the FPGA circuit 20 .

In this embodiment, the FPGA circuit 20 outputs a low level to trigger the reset chip U2 to output a low level of a preset duration, thereby triggering the FPGA circuit 20 to reset, and the upgrade procedure without power failure is completed. Solved the problem that the product could not be reset by powering on and off when the product was upgraded.

In one embodiment, the self-reset circuit 30 further includes a first voltage divider circuit.

The first voltage divider circuit has a first input end, a second input end and an output end, the first input end of the first voltage divider circuit is used to connect to the first supply voltage, and the first voltage divider circuit has a The second input terminal is connected to the control terminal of the FPGA circuit 20 , and the output terminal of the first voltage divider circuit is connected to the first input terminal of the logic circuit 31 .

The first voltage divider circuit is used to keep the voltage output from the control terminal of the FPGA circuit 20 stable when the FPGA reset circuit is powered on or powered off.

When the FPGA reset circuit is powered on or powered off, the voltage of the control terminal of the FPGA circuit 20 is unstable, which may mistakenly trigger the logic circuit 31 to output a low level, thereby mistakenly triggering the FPGA circuit 20 to reset. In this embodiment, the first power supply voltage is divided by the first voltage dividing circuit, so that the voltage of the second input terminal of the first voltage dividing circuit, that is, the control terminal of the FPGA circuit 20 is a preset voltage value. Prevents self-reset from being triggered by mistake when the FPGA reset circuit is powered on or powered off.

In one embodiment, the first voltage dividing circuit includes a first resistor R1 and a second resistor R2.

The input end of the first resistor R1 is the first input end of the first voltage divider circuit, the output end of the first resistor R1 is connected to the input end of the second resistor R2, and the second resistor R2 The output end of the first voltage divider circuit is the output end of the first voltage divider circuit, and the output end of the first resistor R1 and the input end of the second resistor R2 are connected to form the second input end of the first voltage divider circuit.

In this embodiment, the first power supply voltage is divided by the first resistor R1 and the second resistor R2. The user can select the appropriate resistance values of the first resistor R1 and the second resistor R2 according to the requirements, and set different preset voltage values. This ensures that the voltage of the control terminal of the FPGA circuit 20 is stable, and prevents false triggering of self-reset.

In an embodiment, the reset chip U2 further has a second voltage input terminal and a second output terminal.

The second voltage input terminal of the reset chip U2 is used for connecting to a second power supply voltage, and the second output terminal of the reset chip U2 is used for connecting with the second input terminal of the logic circuit 31 .

The reset chip U2 is further configured to output a second voltage signal to the second input end of the logic circuit 31 when the second voltage input end is not connected to the second power supply voltage, and the logic circuit 31 is further configured to The second voltage signal outputs the first voltage signal.

The number of the second voltage input terminals may be multiple. Multiple different power supply voltages are usually used in the circuit, and the reset chip U2 can also monitor multiple power supply voltages. When the second voltage input terminal is not connected to the second power supply voltage, the second output terminal is controlled to output a low level, and the logic circuit 31 is triggered to output a low level, thereby triggering the FPGA circuit 20 to reset.

In this embodiment, the monitoring of the second power supply voltage is implemented by setting the second voltage input terminal to monitor multiple power sources. There is no need to add additional power monitoring circuits, saving costs, reducing circuit redundancy and occupying space.

In one embodiment, the self-reset circuit 30 further includes a second voltage divider circuit.

The second voltage divider circuit has a first input end, a second input end and an output end, the first input end of the second voltage divider circuit is used to connect to the first supply voltage, and the second voltage divider circuit has a The second input terminal is connected to the second output terminal of the reset chip U2 , and the output terminal of the second voltage divider circuit is connected to the second input terminal of the logic circuit 31 .

The second voltage divider circuit is used to keep the voltage output from the second output terminal of the reset chip U2 stable when the FPGA reset circuit is powered on or powered off.

When the FPGA reset circuit is powered on or powered off, the voltage of the second output terminal of the reset chip U2 is unstable, which may falsely trigger the logic circuit 31 to output a low level, thereby falsely triggering the FPGA circuit 20 to reset. In this embodiment, the first power supply voltage is divided by the second voltage dividing circuit, so that the voltage of the second input terminal of the second voltage dividing circuit, that is, the second output terminal of the reset chip U2 is a preset voltage value. Prevents self-reset from being triggered by mistake when the FPGA reset circuit is powered on or powered off.

In one embodiment, the second voltage dividing circuit includes a third resistor R3 and a fourth resistor R4.

The input end of the third resistor R3 is the input end of the second voltage divider circuit, the output end of the third resistor R3 is connected to the input end of the fourth resistor R4, and the output end of the third resistor R3 The terminal is the output terminal of the second voltage dividing circuit, and the output terminal of the third resistor R3 and the input terminal of the fourth resistor R4 are connected to form the second input terminal of the second voltage dividing circuit.

In this embodiment, the first power supply voltage is divided by the third resistor R3 and the fourth resistor R4. The user can select the appropriate resistance values of the third resistor R3 and the fourth resistor R4 according to the requirements, and set different preset voltage values. It is ensured that the voltage of the second output terminal of the reset chip U2 is stable, and the self-reset is prevented from being triggered by mistake.

The present invention also provides a frequency conversion device, and the frequency conversion device includes the above-mentioned FPGA reset circuit.

It can be understood that since the above-mentioned FPGA reset circuit is used in the above-mentioned frequency conversion device, the embodiment of the frequency conversion device includes all the technical solutions of all the above-mentioned FPGA reset circuit embodiments, and the technical effects achieved are also the same. This will not be repeated here.

Referring to FIG. 4 , the present invention also provides an FPGA reset method, which is applied to the above-mentioned frequency conversion equipment, and the FPGA reset method includes:

S100: After the upgrade program is burned, the control terminal of the FPGA circuit 20 outputs a control signal to the controlled terminal of the self-reset circuit;

S200: After receiving the control signal, the self-reset circuit 30 outputs the reset signal to the reset configuration terminal of the FPGA circuit 20 through the output terminal;

S300: The FPGA circuit 20 resets after receiving the reset signal.

In the normal operation state of the FPGA reset circuit, the control terminal of the FPGA circuit 20 outputs a high level to the controlled terminal of the self-reset circuit 30 , and the output terminal of the self-reset circuit 30 outputs a high level to the reset configuration terminal of the FPGA circuit 20 at this time. , the FPGA circuit 20 does not start self-resetting. When the FPGA circuit 20 needs to be upgraded, the host computer writes the upgrade program to the FPGA circuit 20 through the programming interface 10. After the upgrade program is programmed, the FPGA circuit 20 outputs a low level through the control terminal to the controlled terminal of the self-reset circuit 30, At this time, the self-reset circuit 30 outputs a low level to the reset configuration terminal of the FPGA circuit 20 through the output terminal, triggering the reset of the FPGA circuit 20, the reloading program starts to run, and the upgrade procedure without power failure is completed.

The utility model uses the FPGA circuit to output the control signal to the self-reset circuit after the upgrade program is burned, and triggers the automatic reset of the FPGA circuit through the self-reset circuit outputting the reset signal to the reset configuration terminal of the FPGA circuit to complete the upgrade program without power failure. It is not necessary to control the power-on and power-off of the FPGA reset circuit to trigger the reset of the FPGA circuit, which solves the problem that power-on and power-off cannot be performed to reset the product when the product is upgraded.

In one embodiment, the self-reset circuit 30 outputs a reset signal to the reset configuration terminal of the FPGA circuit 20 through the output terminal after receiving the control signal, specifically:

S210: the logic circuit 31 outputs a first voltage signal after receiving the control signal;

S220: The reset chip U2 outputs a reset signal according to the first voltage signal.

In the normal operation state of the FPGA reset circuit, the control terminal of the FPGA circuit 20 outputs a high level to the first input terminal of the logic circuit 31. At this time, the first input terminal and the second input terminal of the logic circuit 31 are both high level. The logic circuit 31 outputs a high level to the controlled terminal of the reset chip U2, the first output terminal of the reset chip U2 outputs a high level to the FPGA circuit 20, and the FPGA circuit 20 does not start self-resetting. When the FPGA circuit 20 needs to be upgraded, the host computer writes the upgrade program to the FPGA circuit 20 through the programming interface 10 . After the upgrade program is programmed, the FPGA circuit 20 outputs a low level to the first input terminal of the logic circuit 31 through the control terminal, and at this time, the logic circuit 31 outputs a low level to the controlled terminal of the reset chip U2. When the low level output by the FPGA circuit 20 is greater than 150ns, the first output terminal of the reset chip U2 is triggered to output a low level of 200ms, and the FPGA circuit 20 is reset to a low level through the current limiting resistor R5, thereby triggering the FPGA circuit 20 reset. When the low level output by the first output terminal of the reset chip U2 changes to a high level, the reset of the FPGA circuit 20 is completed, the reloading program starts to run, and the upgrade program without power failure is completed.

The self-reset circuit 30 also has the function of monitoring the abnormal reset of the power supply. When the first voltage input terminal of the reset chip U2 is not connected to the first power supply voltage, the reset chip U2 outputs a low level to the reset configuration terminal of the FPGA circuit 20 to trigger the reset of the FPGA circuit 20 .

In this embodiment, the FPGA circuit 20 outputs a low level to trigger the reset chip U2 to output a low level of a preset duration, thereby triggering the FPGA circuit 20 to reset, and the upgrade procedure without power failure is completed. Solved the problem that the product could not be reset by powering on and off when the product was upgraded.

The above are only optional embodiments of the present utility model, and are not intended to limit the scope of the present utility model patent. Any equivalent structural transformation made by using the contents of the present utility model description and accompanying drawings under the inventive concept of the present utility model, or directly / Indirect applications in other related technical fields are included in the scope of patent protection of the present utility model.

Claims (8)

1. An FPGA reset circuit, comprising:

the burning interface is used for being connected with an upper computer;

the FPGA circuit is provided with a communication end, a control end and a reset configuration end, and the communication end of the FPGA circuit is electrically connected with the burning interface;

the self-reset circuit is provided with a controlled end and an output end, the controlled end of the self-reset circuit is connected with the control end of the FPGA circuit, and the output end of the self-reset circuit is connected with the reset configuration end of the FPGA circuit;

the FPGA circuit is used for outputting a control signal to the self-reset circuit after the upgrade program is completely burned, and the self-reset circuit is used for outputting a reset signal to the FPGA circuit according to the control signal so as to control the reset of the FPGA circuit.

2. The FPGA reset circuit of claim 1 wherein the FPGA circuit comprises an FPGA chip and a communication circuit;

the FPGA chip is provided with a first communication end, a control end and a reset configuration end, the communication circuit is provided with a first communication end and a second communication end, the first communication end of the communication circuit is the communication end of the FPGA circuit, and the second communication end of the communication circuit is connected with the first communication end of the FPGA chip;

the control end of the FPGA chip is the control end of the FPGA circuit, and the reset configuration end of the FPGA chip is the reset configuration end of the FPGA circuit.

3. The FPGA reset circuit of claim 2 wherein the FPGA circuit further comprises a memory;

the FPGA chip is also provided with a second communication end, the second communication end of the FPGA chip is electrically connected with the memory, and the memory is used for storing an upgrading program.

4. The FPGA reset circuit of claim 1 wherein the self reset circuit comprises a reset chip and a logic circuit;

the reset chip is provided with a first voltage input end, a controlled end and a first output end, the logic circuit is provided with a first input end, a second input end and an output end, the first input end of the logic circuit is connected with the control end of the FPGA circuit, and the second input end of the logic circuit is used for being connected with a first power supply voltage;

a first voltage input end of the reset chip is used for accessing a first power supply voltage, a controlled end of the reset chip is connected with an output end of the logic circuit, and a first output end of the reset chip is connected with a reset configuration end of the FPGA circuit;

the logic circuit is used for outputting a first voltage signal under the control of the control signal, and the reset chip is used for outputting a reset signal according to the first voltage signal; the reset chip is also used for outputting a reset signal when the first voltage input end is not connected with the first power supply voltage.

5. The FPGA reset circuit of claim 4 wherein the self reset circuit further comprises a first voltage divider circuit;

the first voltage division circuit is provided with a first input end, a second input end and an output end, the first input end of the first voltage division circuit is used for accessing a first power supply voltage, the second input end of the first voltage division circuit is connected with the control end of the FPGA chip, and the output end of the first voltage division circuit is connected with the first input end of the logic circuit;

the first voltage division circuit is used for keeping the voltage output by the control end of the FPGA circuit stable when the FPGA reset circuit is powered on or powered off.

6. The FPGA reset circuit of claim 4 wherein the reset chip further has a second voltage input and a second output;

a second voltage input end of the reset chip is used for accessing a second power supply voltage, and a second output end of the reset chip is used for being connected with a second input end of the logic circuit;

the reset chip is further configured to output a second voltage signal to a second input terminal of the logic circuit when a second voltage input terminal is not connected to a second power supply voltage, and the logic circuit is further configured to output a first voltage signal according to the second voltage signal.

7. The FPGA reset circuit of claim 6 wherein the self reset circuit further comprises a second voltage divider circuit;

the second voltage division circuit is provided with a first input end, a second input end and an output end, the first input end of the second voltage division circuit is used for accessing a first power supply voltage, the second input end of the second voltage division circuit is connected with the second output end of the reset chip, and the output end of the second voltage division circuit is connected with the second input end of the logic circuit;

and the second voltage division circuit is used for keeping the voltage output by the second output end of the reset chip stable when the FPGA reset circuit is powered on or powered off.

8. Frequency conversion equipment, characterized in that the frequency conversion equipment comprises an FPGA reset circuit according to any one of claims 1 to 7.

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