CN217034696U - FPGA reset circuit and frequency conversion equipment - Google Patents

Abstract

The utility model discloses an FPGA reset circuit and frequency conversion equipment. The FPGA circuit is used for outputting a control signal to the self-reset circuit after the upgrade program is completely burned, and the self-reset circuit is used for outputting a reset signal to the FPGA circuit according to the control signal so as to control the FPGA circuit to reset. According to the utility model, the reset signal is output from the reset circuit to the reset configuration end of the FPGA circuit to trigger the FPGA circuit to automatically reset, so that the power-off-free upgrading program is completed. The problem of unable power on-off resets when the product is upgraded is solved.

Description

FPGA reset circuit and frequency conversion equipment

Technical Field

The utility model relates to a frequency converter, in particular to an FPGA reset circuit and frequency conversion equipment.

Background

With the continuous upgrading and changing of the application scenes of the frequency converter products, the requirements of customers on the functions and the performance of the frequency converter products are more and more high. In order to meet customer requirements, software upgrades to the frequency converter are unavoidable. In the conventional software upgrading process of the frequency converter, the frequency converter needs to be powered on and powered off again at least once after software is upgraded, so that the newly upgraded software becomes effective, and the process is similar to patching or upgrading personal PC software.

In some applications with higher requirements, in order to ensure safe or continuous production, the operation of powering on or powering off the frequency converter and other devices is not supported or allowed. The existing scheme can select an MCU chip with an internal self-resetting function, but the selection of the MCU is limited under the condition, and a plurality of limitations are brought to product design.

SUMMERY OF THE UTILITY MODEL

The utility model mainly aims to provide an FPGA reset circuit and frequency conversion equipment, and aims to realize uninterrupted reset.

In order to achieve the above object, the present invention provides an FPGA reset circuit, which includes:

the burning interface is used for being connected with an upper computer;

the FPGA circuit is provided with a communication end, a control end and a reset configuration end, and the communication end of the FPGA circuit is electrically connected with the burning interface;

the self-reset circuit is provided with a controlled end and an output end, the controlled end of the self-reset circuit is connected with the control end of the FPGA circuit, and the output end of the self-reset circuit is connected with the reset configuration end of the FPGA circuit;

the FPGA circuit is used for outputting a control signal to the self-reset circuit after the upgrade program is completely burned, and the self-reset circuit is used for outputting a reset signal to the FPGA circuit according to the control signal so as to control the FPGA circuit to reset.

In one embodiment, the FPGA circuit includes an FPGA chip and a communication circuit;

the FPGA chip is provided with a first communication end, a control end and a reset configuration end, the communication circuit is provided with a first communication end and a second communication end, the first communication end of the communication circuit is the communication end of the FPGA circuit, and the second communication end of the communication circuit is connected with the first communication end of the FPGA chip;

the control end of the FPGA chip is the control end of the FPGA circuit, and the reset configuration end of the FPGA chip is the reset configuration end of the FPGA circuit.

In an embodiment, the FPGA circuit further comprises a memory;

the FPGA chip is also provided with a second communication end, the second communication end of the FPGA chip is electrically connected with the memory, and the memory is used for storing an upgrading program.

In one embodiment, the self-reset circuit comprises a reset chip and a logic circuit;

the reset chip is provided with a first voltage input end, a controlled end and a first output end, the logic circuit is provided with a first input end, a second input end and an output end, the first input end of the logic circuit is connected with the control end of the FPGA circuit, and the second input end of the logic circuit is used for being connected with a first power supply voltage;

the first voltage input end of the reset chip is used for accessing a first power supply voltage, the controlled end of the reset chip is connected with the output end of the logic circuit, and the first output end of the reset chip is connected with the reset configuration end of the FPGA circuit;

the logic circuit is used for outputting a first voltage signal under the control of the control signal, and the reset chip is used for outputting a reset signal according to the first voltage signal; the reset chip is also used for outputting a reset signal when the first voltage input end is not connected with the first power supply voltage.

In one embodiment, the self reset circuit further comprises a first voltage divider circuit;

the first voltage division circuit is provided with a first input end, a second input end and an output end, the first input end of the first voltage division circuit is used for accessing a first power supply voltage, the second input end of the first voltage division circuit is connected with the control end of the FPGA chip, and the output end of the first voltage division circuit is connected with the first input end of the logic circuit;

the first voltage division circuit is used for keeping the voltage output by the control end of the FPGA circuit stable when the FPGA reset circuit is powered on or powered off.

In one embodiment, the reset chip further has a second voltage input terminal and a second output terminal;

a second voltage input end of the reset chip is used for accessing a second power supply voltage, and a second output end of the reset chip is used for being connected with a second input end of the logic circuit;

the reset chip is further used for outputting a second voltage signal to a second input end of the logic circuit when a second voltage input end is not connected with a second power supply voltage, and the logic circuit is further used for outputting a first voltage signal according to the second voltage signal.

In one embodiment, the self reset circuit further comprises a second voltage divider circuit;

the second voltage division circuit is provided with a first input end, a second input end and an output end, the first input end of the second voltage division circuit is used for accessing a first power supply voltage, the second input end of the second voltage division circuit is connected with the second output end of the reset chip, and the output end of the second voltage division circuit is connected with the second input end of the logic circuit;

and the second voltage division circuit is used for keeping the voltage output by the second output end of the reset chip stable when the FPGA reset circuit is powered on or powered off.

The utility model also provides frequency conversion equipment which comprises the FPGA reset circuit.

The utility model also provides an FPGA resetting method which is applied to the frequency conversion equipment and comprises the following steps:

after the upgrading program is burnt, the control end of the FPGA circuit outputs a control signal to the controlled end of the self-reset circuit;

the self-reset circuit outputs a reset signal to a reset configuration end of the FPGA circuit through an output end after receiving the control signal;

and the FPGA circuit resets after receiving the reset signal.

In an embodiment, the outputting, by the self-reset circuit, the reset signal to the reset configuration end of the FPGA circuit through the output end after receiving the control signal specifically includes:

the logic circuit outputs a first voltage signal after receiving the control signal;

and the reset chip outputs a reset signal according to the first voltage signal.

According to the utility model, the FPGA circuit outputs a control signal to the self-reset circuit after the upgrading program is completely burned, and the self-reset circuit outputs a reset signal to the reset configuration end of the FPGA circuit to trigger the FPGA circuit to automatically reset, so that the upgrading program without power failure is completed. The FPGA reset circuit is triggered to reset without controlling the power on and power off of the FPGA reset circuit, so that the problem that the power on and power off cannot be reset when the product is upgraded is solved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.

FIG. 1 is a schematic diagram of the structure of the FPGA reset circuit of the present invention;

FIG. 2 is a schematic diagram of the structure of the FPGA reset circuit of the present invention;

FIG. 3 is a logic state table of the FPGA reset circuit of the present invention;

FIG. 4 is a schematic flow chart of the FPGA reset method of the present invention;

fig. 5 is a schematic flowchart of an embodiment of an FPGA reset method according to the present invention.

The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.

It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.

In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.

Referring to fig. 1, the present invention provides an FPGA reset circuit, which includes a programming interface 10, an FPGA circuit 20, and a self-reset circuit 30.

The burning interface 10 is used for connecting with an upper computer.

The FPGA circuit 20 is provided with a communication end, a control end and a reset configuration end, and the communication end of the FPGA circuit 20 is electrically connected with the burning interface 10.

The self-reset circuit 30 has a controlled terminal and an output terminal, the controlled terminal of the self-reset circuit 30 is connected with the control terminal of the FPGA circuit 20, and the output terminal of the self-reset circuit 30 is connected with the reset configuration terminal of the FPGA circuit 20.

The FPGA circuit 20 is configured to output a control signal to the self-reset circuit 30 after the upgrade program is completely burned, and the self-reset circuit 30 is configured to output a reset signal to the FPGA circuit 20 according to the control signal to control the FPGA circuit 20 to reset.

When the FPGA reset circuit is in a normal operation state, the control terminal of the FPGA circuit 20 outputs a high level to the controlled terminal of the self-reset circuit 30, and at this time, the output terminal of the self-reset circuit 30 outputs a high level to the reset configuration terminal of the FPGA circuit 20, so that the FPGA circuit 20 does not start self-reset. When the FPGA circuit 20 needs to be upgraded, the upper computer burns an upgrading program to the FPGA circuit 20 through the burning interface 10, after the upgrading program is burnt, the FPGA circuit 20 outputs a low level to the controlled end of the self-reset circuit 30 through the control end, at the moment, the self-reset circuit 30 outputs a low level to the reset configuration end of the FPGA circuit 20 through the output end, the FPGA circuit 20 is triggered to reset, the reloading program starts to run, and the upgrading program without power off is completed.

According to the utility model, the FPGA circuit outputs a control signal to the self-reset circuit after the upgrade program is completely burned, and the self-reset circuit outputs a reset signal to the reset configuration end of the FPGA circuit to trigger the FPGA circuit to automatically reset, so that the non-power-off upgrade program is completed. The FPGA reset circuit is triggered to reset without controlling the power on and power off of the FPGA reset circuit, so that the problem that the reset cannot be performed by powering on and off when a product is upgraded is solved.

In one embodiment, the FPGA circuit 20 includes an FPGA chip U1 and a communication circuit 21.

The FPGA chip U1 is provided with a first communication end, a control end and a reset configuration end, the communication circuit 21 is provided with a first communication end and a second communication end, the first communication end of the communication circuit 21 is the communication end of the FPGA circuit 20, and the second communication end of the communication circuit 21 is connected with the first communication end of the FPGA chip U1.

The control end of the FPGA chip U1 is the control end of the FPGA circuit 20, and the reset configuration end of the FPGA chip U1 is the reset configuration end of the FPGA circuit 20.

In this embodiment, signal conversion is performed through the communication circuit 21, so that normal communication can be performed between the FPGA chip U1 and the upper computer, and the programming of the upgrade program is completed.

In one embodiment, the FPGA circuit 20 further includes a memory U3.

The FPGA chip U1 is further provided with a second communication end, the second communication end of the FPGA chip U1 is electrically connected with the memory U3, and the memory U3 is used for storing an upgrading program.

In this embodiment, the memory U3 stores the upgrade program of the FPGA chip U1, and the FPGA chip U1 obtains the upgrade program from the memory U3 for upgrading. The upgrade program is more stable to be stored in the memory U3, and is prevented from being lost or damaged due to being overwritten or modified by other data.

Referring to fig. 2 and 3, in one embodiment, the self reset circuit 30 includes a reset chip U2 and a logic circuit 31.

The reset chip U2 has a first voltage input terminal, a controlled terminal and a first output terminal, the logic circuit 31 has a first input terminal, a second input terminal and an output terminal, the first input terminal of the logic circuit 31 is connected to the control terminal of the FPGA circuit 20, and the second input terminal of the logic circuit 31 is used for accessing a first power supply voltage.

The first voltage input end of the reset chip U2 is used for accessing a first power supply voltage, the controlled end of the reset chip U2 is connected to the output end of the logic circuit 31, and the first output end of the reset chip U2 is connected to the reset configuration end of the FPGA circuit 20.

The logic circuit 31 is used for outputting a first voltage signal under the control of the control signal, and the reset chip U2 is used for outputting a reset signal according to the first voltage signal; the reset chip U2 is further configured to output a reset signal when the first voltage input terminal is not connected to the first power supply voltage.

In the above embodiment, the reset chip U2 may be an ADM708ARZ chip, or other ARM type or DSP type chips. The logic circuit 31 may be an or gate U4. The self reset circuit 30 also includes a fifth resistor R5. The input end of the fifth resistor R5 is connected to the first output end of the reset chip U2, and the output end of the fifth resistor R5 is connected to the reset configuration end of the FPGA circuit 20.

Under the normal operation state of the FPGA reset circuit, the control end of the FPGA circuit 20 outputs a high level to the first input end of the logic circuit 31, at this time, both the first input end and the second input end of the logic circuit 31 are high levels, the logic circuit 31 outputs a high level to the controlled end of the reset chip U2, the first output end of the reset chip U2 outputs a high level to the FPGA circuit 20, and the FPGA circuit 20 is not started for self-reset. When the FPGA circuit 20 needs to be upgraded, the upper computer burns an upgrade program to the FPGA circuit 20 through the burning interface 10. After the upgrade program is completely burned, the FPGA circuit 20 outputs a low level to the first input terminal of the logic circuit 31 through the control terminal, and at this time, the logic circuit 31 outputs a low level to the controlled terminal of the reset chip U2. When the low level output by the FPGA circuit 20 is greater than 150ns, the first output terminal of the reset chip U2 is triggered to output a low level of 200ms, the reset configuration terminal of the FPGA circuit 20 is made to be a low level through the current limiting resistor R5, and the FPGA circuit 20 is triggered to reset. When the low level output by the first output end of the reset chip U2 changes to the high level, the FPGA circuit 20 is reset and ends, the reloading program starts to run, and the upgrading program without power off is completed.

The self reset circuit 30 also has a function of monitoring power supply abnormality reset. When the first voltage input end of the reset chip U2 is not connected to the first power supply voltage, the reset chip U2 outputs a low level to the reset configuration end of the FPGA circuit 20, and triggers the FPGA circuit 20 to reset.

In this embodiment, the low level output by the FPGA circuit 20 triggers the reset chip U2 to output a low level for a preset time, so as to trigger the FPGA circuit 20 to reset, thereby completing the power-off upgrade procedure. The problem of unable power on-off resets when the product is upgraded is solved.

In one embodiment, the self reset circuit 30 further includes a first voltage divider circuit.

The first voltage divider circuit has a first input terminal, a second input terminal, and an output terminal, the first input terminal of the first voltage divider circuit is used for accessing a first power supply voltage, the second input terminal of the first voltage divider circuit is connected to the control terminal of the FPGA circuit 20, and the output terminal of the first voltage divider circuit is connected to the first input terminal of the logic circuit 31.

The first voltage dividing circuit is configured to keep the voltage output by the control terminal of the FPGA circuit 20 stable when the FPGA reset circuit is powered on or powered off.

When the FPGA reset circuit is powered on or powered off, the voltage at the control terminal of the FPGA circuit 20 is unstable, and the logic circuit 31 may be triggered by mistake to output a low level, so as to trigger the FPGA circuit 20 by mistake to reset. In the present embodiment, the first voltage divider circuit divides the first power supply voltage, so that the voltage at the second input terminal of the first voltage divider circuit, i.e. the control terminal of the FPGA circuit 20, is a preset voltage value. The self-reset is prevented from being triggered by mistake when the FPGA reset circuit is powered on or powered off.

In one embodiment, the first voltage divider circuit includes a first resistor R1 and a second resistor R2.

The input end of the first resistor R1 is the first input end of the first voltage-dividing circuit, the output end of the first resistor R1 is connected with the input end of the second resistor R2, the output end of the second resistor R2 is the output end of the first voltage-dividing circuit, and the output end of the first resistor R1 and the input end of the second resistor R2 are connected to form the second input end of the first voltage-dividing circuit.

According to the embodiment, the first power supply voltage is divided through the first resistor R1 and the second resistor R2, a user can select the resistance values of the first resistor R1 and the second resistor R2 which are suitable according to requirements, different preset voltage values are set, the voltage stability of the control end of the FPGA circuit 20 is guaranteed, and false triggering and self resetting are prevented.

In one embodiment, the reset chip U2 further has a second voltage input terminal and a second output terminal.

A second voltage input terminal of the reset chip U2 is configured to receive a second supply voltage, and a second output terminal of the reset chip U2 is configured to be connected to a second input terminal of the logic circuit 31.

The reset chip U2 is further configured to output a second voltage signal to the second input terminal of the logic circuit 31 when the second voltage input terminal is not connected to the second power supply voltage, and the logic circuit 31 is further configured to output the first voltage signal according to the second voltage signal.

The number of the second voltage input terminals may be plural. Multiple different power supply voltages are generally required in the circuit, and the reset chip U2 can also monitor multiple power supply voltages. When the second voltage input terminal is not connected to the second power supply voltage, the second output terminal is controlled to output a low level, the trigger logic circuit 31 outputs the low level, and the FPGA circuit 20 is triggered to reset.

In the embodiment, the second power supply voltage is monitored by setting the second voltage input end, so that multi-power supply monitoring is realized. And a power supply monitoring circuit is not required to be additionally arranged, so that the cost is saved, and the redundancy and the occupied space of the circuit are reduced.

In one embodiment, the self reset circuit 30 further includes a second voltage divider circuit.

The second voltage divider circuit has a first input terminal, a second input terminal, and an output terminal, the first input terminal of the second voltage divider circuit is used for receiving a first power supply voltage, the second input terminal of the second voltage divider circuit is connected to the second output terminal of the reset chip U2, and the output terminal of the second voltage divider circuit is connected to the second input terminal of the logic circuit 31.

The second voltage division circuit is used for keeping the voltage output by the second output end of the reset chip U2 stable when the FPGA reset circuit is powered on or powered off.

When the FPGA reset circuit is powered on or powered off, the voltage at the second output terminal of the reset chip U2 is unstable, which may falsely trigger the logic circuit 31 to output a low level, thereby falsely triggering the FPGA circuit 20 to reset. In the present embodiment, the first power supply voltage is divided by the second voltage dividing circuit, so that the voltage at the second input terminal of the second voltage dividing circuit, i.e., the second output terminal of the reset chip U2, is a preset voltage value. The self-reset circuit can prevent the FPGA reset circuit from being triggered by mistake when the power is on or off.

In one embodiment, the second voltage divider circuit includes a third resistor R3 and a fourth resistor R4.

The input end of the third resistor R3 is the input end of the second voltage-dividing circuit, the output end of the third resistor R3 is connected with the input end of the fourth resistor R4, the output end of the third resistor R3 is the output end of the second voltage-dividing circuit, and the output end of the third resistor R3 and the input end of the fourth resistor R4 are connected to form the second input end of the second voltage-dividing circuit.

According to the embodiment, the first power supply voltage is divided by the third resistor R3 and the fourth resistor R4, a user can select the appropriate resistance values of the third resistor R3 and the fourth resistor R4 according to requirements, different preset voltage values are set, the voltage stability of the second output end of the reset chip U2 is guaranteed, and false triggering and self resetting are prevented.

The utility model also provides frequency conversion equipment which comprises the FPGA reset circuit.

It can be understood that, because the FPGA reset circuit is used in the frequency conversion device, the embodiment of the frequency conversion device includes all technical solutions of all embodiments of the FPGA reset circuit, and the achieved technical effects are also completely the same, and are not described herein again.

Referring to fig. 4, the present invention further provides an FPGA reset method, which is applied to the frequency conversion device described above, and the FPGA reset method includes:

s100: after the upgrade program is completely burned, the control end of the FPGA circuit 20 outputs a control signal to the controlled end of the self-reset circuit;

s200: the self-reset circuit 30 outputs a reset signal to the reset configuration end of the FPGA circuit 20 through the output end after receiving the control signal;

s300: the FPGA circuit 20 resets upon receiving a reset signal.

When the FPGA reset circuit is in a normal operation state, the control terminal of the FPGA circuit 20 outputs a high level to the controlled terminal of the self-reset circuit 30, and at this time, the output terminal of the self-reset circuit 30 outputs a high level to the reset configuration terminal of the FPGA circuit 20, so that the FPGA circuit 20 does not start self-reset. When the FPGA circuit 20 needs to be upgraded, the upper computer burns an upgrading program to the FPGA circuit 20 through the burning interface 10, after the upgrading program is burnt, the FPGA circuit 20 outputs a low level to a controlled end of the self-reset circuit 30 through a control end, at the moment, the self-reset circuit 30 outputs a low level to a reset configuration end of the FPGA circuit 20 through an output end, the FPGA circuit 20 is triggered to reset, the reloading program starts to run, and the upgrading program without power off is completed.

According to the utility model, the FPGA circuit outputs a control signal to the self-reset circuit after the upgrade program is completely burned, and the self-reset circuit outputs a reset signal to the reset configuration end of the FPGA circuit to trigger the FPGA circuit to automatically reset, so that the non-power-off upgrade program is completed. The FPGA reset circuit is triggered to reset without controlling the power on and power off of the FPGA reset circuit, so that the problem that the reset cannot be performed by powering on and off when a product is upgraded is solved.

In an embodiment, the outputting the reset signal from the reset circuit 30 to the reset configuration end of the FPGA circuit 20 through the output end after receiving the control signal specifically includes:

s210: the logic circuit 31 receives the control signal and then outputs a first voltage signal;

s220: the reset chip U2 outputs a reset signal according to the first voltage signal.

Under the normal operation state of the FPGA reset circuit, the control end of the FPGA circuit 20 outputs a high level to the first input end of the logic circuit 31, at this time, both the first input end and the second input end of the logic circuit 31 are high levels, the logic circuit 31 outputs a high level to the controlled end of the reset chip U2, the first output end of the reset chip U2 outputs a high level to the FPGA circuit 20, and the FPGA circuit 20 is not started for self-reset. When the FPGA circuit 20 needs to be upgraded, the upper computer burns an upgrade program to the FPGA circuit 20 through the burning interface 10. After the upgrade program is burned, the FPGA circuit 20 outputs a low level to the first input terminal of the logic circuit 31 through the control terminal, and at this time, the logic circuit 31 outputs a low level to the controlled terminal of the reset chip U2. When the low level output by the FPGA circuit 20 is greater than 150ns, the first output terminal of the reset chip U2 is triggered to output a low level of 200ms, the reset configuration terminal of the FPGA circuit 20 is made to be a low level through the current limiting resistor R5, and the FPGA circuit 20 is triggered to reset. When the low level output by the first output end of the reset chip U2 is converted into the high level, the reset of the FPGA circuit 20 is finished, the reloading program starts to run, and the power-off-free upgrade program is completed.

The self-reset circuit 30 also has a function of monitoring power supply abnormality reset. When the first voltage input end of the reset chip U2 is not connected to the first power supply voltage, the reset chip U2 outputs a low level to the reset configuration end of the FPGA circuit 20, and triggers the FPGA circuit 20 to reset.

In this embodiment, the FPGA circuit 20 outputs a low level to trigger the reset chip U2 to output a low level for a preset time, so as to trigger the FPGA circuit 20 to reset, thereby completing the power-off upgrade procedure. The problem of unable power on-off resets when the product is upgraded is solved.

The above description is only an alternative embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (8)

1. An FPGA reset circuit, comprising:

the burning interface is used for being connected with an upper computer;

the FPGA circuit is provided with a communication end, a control end and a reset configuration end, and the communication end of the FPGA circuit is electrically connected with the burning interface;

the self-reset circuit is provided with a controlled end and an output end, the controlled end of the self-reset circuit is connected with the control end of the FPGA circuit, and the output end of the self-reset circuit is connected with the reset configuration end of the FPGA circuit;

the FPGA circuit is used for outputting a control signal to the self-reset circuit after the upgrade program is completely burned, and the self-reset circuit is used for outputting a reset signal to the FPGA circuit according to the control signal so as to control the reset of the FPGA circuit.

2. The FPGA reset circuit of claim 1 wherein the FPGA circuit comprises an FPGA chip and a communication circuit;

the FPGA chip is provided with a first communication end, a control end and a reset configuration end, the communication circuit is provided with a first communication end and a second communication end, the first communication end of the communication circuit is the communication end of the FPGA circuit, and the second communication end of the communication circuit is connected with the first communication end of the FPGA chip;

the control end of the FPGA chip is the control end of the FPGA circuit, and the reset configuration end of the FPGA chip is the reset configuration end of the FPGA circuit.

3. The FPGA reset circuit of claim 2 wherein the FPGA circuit further comprises a memory;

the FPGA chip is also provided with a second communication end, the second communication end of the FPGA chip is electrically connected with the memory, and the memory is used for storing an upgrading program.

4. The FPGA reset circuit of claim 1 wherein the self reset circuit comprises a reset chip and a logic circuit;

the reset chip is provided with a first voltage input end, a controlled end and a first output end, the logic circuit is provided with a first input end, a second input end and an output end, the first input end of the logic circuit is connected with the control end of the FPGA circuit, and the second input end of the logic circuit is used for being connected with a first power supply voltage;

a first voltage input end of the reset chip is used for accessing a first power supply voltage, a controlled end of the reset chip is connected with an output end of the logic circuit, and a first output end of the reset chip is connected with a reset configuration end of the FPGA circuit;

the logic circuit is used for outputting a first voltage signal under the control of the control signal, and the reset chip is used for outputting a reset signal according to the first voltage signal; the reset chip is also used for outputting a reset signal when the first voltage input end is not connected with the first power supply voltage.

5. The FPGA reset circuit of claim 4 wherein the self reset circuit further comprises a first voltage divider circuit;

the first voltage division circuit is provided with a first input end, a second input end and an output end, the first input end of the first voltage division circuit is used for accessing a first power supply voltage, the second input end of the first voltage division circuit is connected with the control end of the FPGA chip, and the output end of the first voltage division circuit is connected with the first input end of the logic circuit;

the first voltage division circuit is used for keeping the voltage output by the control end of the FPGA circuit stable when the FPGA reset circuit is powered on or powered off.

6. The FPGA reset circuit of claim 4 wherein the reset chip further has a second voltage input and a second output;

a second voltage input end of the reset chip is used for accessing a second power supply voltage, and a second output end of the reset chip is used for being connected with a second input end of the logic circuit;

the reset chip is further configured to output a second voltage signal to a second input terminal of the logic circuit when a second voltage input terminal is not connected to a second power supply voltage, and the logic circuit is further configured to output a first voltage signal according to the second voltage signal.

7. The FPGA reset circuit of claim 6 wherein the self reset circuit further comprises a second voltage divider circuit;

the second voltage division circuit is provided with a first input end, a second input end and an output end, the first input end of the second voltage division circuit is used for accessing a first power supply voltage, the second input end of the second voltage division circuit is connected with the second output end of the reset chip, and the output end of the second voltage division circuit is connected with the second input end of the logic circuit;

and the second voltage division circuit is used for keeping the voltage output by the second output end of the reset chip stable when the FPGA reset circuit is powered on or powered off.

8. Frequency conversion equipment, characterized in that the frequency conversion equipment comprises an FPGA reset circuit according to any one of claims 1 to 7.

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