CN216719926U

CN216719926U - Dislocation packaging structure

Info

Publication number: CN216719926U
Application number: CN202123026611.8U
Authority: CN
Inventors: 不公告发明人
Original assignee: Shenzhen Panyi Microelectronics Technology Co ltd
Current assignee: Shenzhen Panyi Microelectronics Technology Co ltd
Priority date: 2021-12-02
Filing date: 2021-12-02
Publication date: 2022-06-10
Anticipated expiration: 2031-12-02

Abstract

The utility model discloses a dislocation packaging structure, which comprises a semiconductor element, a first pressing sheet and a second pressing sheet, wherein the first pressing sheet is provided with a first pressing groove; the chip comprises a first surface and a second surface, wherein the first surface and the second surface are arranged oppositely; a plurality of connecting ribs are arranged on the periphery of the first pressing piece and the second pressing piece, the first pressing piece is connected with the first surface, the second pressing piece is connected with the second surface, and any connecting rib on the first pressing piece is not positioned right above any connecting rib on the second pressing piece after connection. The positions of the connecting ribs on the first pressing sheet and the second pressing sheet used for packaging the element are adjusted, so that the connecting positions of the exposed parts of the pressing sheets after packaging are staggered, the linear distance between the connecting ribs on the first pressing sheet and the second pressing sheet is increased under the condition that the number of the connecting ribs on each pressing sheet is not changed, and the short circuit risk is reduced.

Description

Dislocation packaging structure

Technical Field

The utility model relates to the technical field of electronics, in particular to a staggered packaging structure.

Background

Electronic products have evolved throughout toward smaller size, lighter weight, faster speed, higher frequency, lower cost, and higher reliability.

Then, when the specification of the chip becomes smaller, the S pole and the D pole are very likely to be short-circuited at the step of soldering or the like because the specification of the package becomes smaller during the packaging process.

SUMMERY OF THE UTILITY MODEL

In order to solve the above problems, the present invention provides a staggered package structure, which is suitable for chips of different types and can reduce the probability of short circuit.

The technical scheme adopted by the utility model is as follows:

a dislocation packaging structure comprises a semiconductor element, a first pressing sheet and a second pressing sheet;

the semiconductor element comprises a first surface and a second surface, and the first surface and the second surface are arranged oppositely; the periphery of the first pressing piece and the periphery of the second pressing piece are provided with a plurality of connecting ribs, the first pressing piece is connected with the first surface, the second pressing piece is connected with the second surface, and after connection, any connecting rib on the first pressing piece is not positioned right above any connecting rib on the second pressing piece.

Preferably, the connecting ribs are uniformly arranged around the first pressing plate and the second pressing plate.

Preferably, the connecting ribs on the first pressing plate after being packaged are positioned right above the two connecting ribs on the second pressing plate.

Preferably, the vertical distance between the first and second preforms after encapsulation is less than 0.15 mm.

Preferably, the thickness of the connecting rib on the first pressing plate is the same as that of the first pressing plate.

Preferably, the thickness of the connecting rib on the second pressing plate is the same as that of the second pressing plate.

Preferably, the connecting ribs on the first pressing plate and the connecting ribs on the second pressing plate are the same in size.

Preferably, the width of the connecting rib on the first pressing plate and the width of the connecting rib on the second pressing plate are 0.2-0.4 mm.

Preferably, the area of the first pressing piece is larger than that of the first surface.

Preferably, the second pressing piece has an area larger than that of the second surface.

Compared with the prior art, the staggered packaging structure has the advantages that the positions of the connecting ribs on the first pressing plate and the second pressing plate for packaging elements are adjusted, so that the connecting positions of the exposed parts of the pressing plates after packaging are staggered, the linear distance between the connecting ribs on the first pressing plate and the second pressing plate is increased under the condition that the number of the connecting ribs on each pressing plate is not changed, and the short circuit risk is reduced.

Drawings

In order to more clearly explain the technical solution in the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be described below.

Fig. 1 is a schematic structural diagram of a package with a staggered package structure according to an embodiment of the present invention;

fig. 2 is an exploded view of a staggered package structure according to an embodiment of the present invention;

FIG. 3 is a front view of a package with a staggered package structure according to an embodiment of the present invention;

fig. 4 is a schematic top view of a heat dissipation structure according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a heat dissipation structure according to an embodiment of the present invention;

fig. 6 is a schematic front view of a heat dissipation structure according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the utility model and are not intended to limit the utility model.

The terms "first", "second", and the like in the embodiments of the present invention are only used for distinguishing related technical features, and do not indicate a sequential order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In this application, the terms "upper", "lower", "inner", "middle", "outer", "front", "rear", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings. These terms are used primarily to better describe the present application and its embodiments, and are not used to limit the indicated devices, elements or components to a particular orientation or to be constructed and operated in a particular orientation.

Moreover, some of the above terms may be used to indicate other meanings besides the orientation or positional relationship, for example, the term "on" may also be used to indicate some kind of attachment or connection relationship in some cases. The specific meaning of these terms in this application will be understood by those of ordinary skill in the art as appropriate.

Furthermore, the terms "disposed," "connected," and "secured" are to be construed broadly. For example, "connected" may be a fixed connection, a detachable connection, or a unitary construction; can be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements or components.

Example 1

The embodiment of the utility model provides a staggered packaging structure, which is mainly a chip applied to a power device packaging element, for example, a waterproof packaging structure applied to electronic elements such as a high-power transistor, a Thyristor, a bidirectional Thyristor GTO (Gate-Turn-Off Thyristor), a mosfet (metal Oxide Semiconductor Field Effect transistor), an igbt (insulated Gate bipolar transistor) and the like.

As shown in fig. 1-3, comprises a semiconductor element 110, a first pressing piece 200, a second pressing piece 300; the semiconductor element 110 includes a first surface and a second surface, the first surface and the second surface being disposed opposite to each other; a plurality of connecting ribs 400 are arranged on the periphery of the first pressing plate 200 and the second pressing plate 300, the first pressing plate 200 is connected with the first surface, the second pressing plate 300 is connected with the second surface, and any connecting rib 400 on the first pressing plate 200 is not positioned right above any connecting rib 400 on the second pressing plate 300 after connection.

The upper and lower pressing sheets for packaging mostly adopt the same pressing sheet, so that the connecting rib 400 of the upper pressing sheet is positioned right above the connecting rib 400 of the lower pressing sheet after packaging, when the specification of the semiconductor element 110 is reduced, the linear distance between the connecting ribs 400 on the upper and lower pressing sheets is also reduced, for example, when the specification is smaller than 0.15mm, in the subsequent application (such as PCB welding) process, the direct short circuit of the two pressing sheets is easily caused, the normal use of the semiconductor element 110 is influenced, and even the semiconductor element is damaged. Any connecting rib 400 on the first pressing plate 200 is not positioned right above any connecting rib 400 on the second pressing plate 300, so that the linear distance between the connecting ribs 400 on the upper and lower pressing plates is increased.

The connecting rib 400 is uniformly arranged around the first pressing plate 200 and the second pressing plate 300, and the connecting rib 400 is uniformly arranged so that the stress of each connecting rib 400 is uniform, thereby avoiding the occurrence of the damage caused by the overlarge stress of the single connecting rib 400.

The connecting ribs 400 of the first wafer 200 after encapsulation are positioned directly above the two connecting ribs 400 of the second wafer 300. In this way, the straight distance between the connection ribs 400 is increased as much as possible without changing the size and number of the connection ribs 400.

The vertical distance between the first pressing plate 200 and the second pressing plate 300 after being packaged is less than 0.15mm, so that if the upper and lower pressing plates adopt the same pressing plate, the connecting rib 400 of the upper pressing plate after being packaged is positioned right above the connecting rib 400 of the lower pressing plate, and the linear distance between the connecting ribs 400 on the upper and lower pressing plates is also less than 0.15mm, so that in the subsequent application (such as PCB welding), the two pressing plates are easily directly short-circuited to influence the normal use of the semiconductor element 110.

The thickness of the connecting rib 400 on the first pressing plate 200 is the same as that of the first pressing plate 200, and the thickness of the connecting rib 400 on the second pressing plate 300 is the same as that of the second pressing plate 300. In actual manufacturing activities, the thickness of the tie bar 400 is generally the same as the thickness of the preform, taking into account the ease of manufacturing the preform, and the strength of the tie bar 400.

The connecting ribs 400 on the first pressing plate 200 are the same size as the connecting ribs 400 on the second pressing plate 300.

The width of the connecting rib 400 on the first pressing plate 200 and the width of the connecting rib 400 on the second pressing plate 300 are 0.2-0.4 mm.

The area of the first segment 200 is greater than that of the first surface, and the area of the second segment 300 is greater than that of the second surface.

Example 2

The present embodiment provides a heat dissipation structure, which is mainly applied to a Semiconductor device in a power device package device, for example, a heat dissipation structure applied to an electronic device in a high power transistor, a Thyristor, a bidirectional Thyristor GTO (Gate-Turn-Off Thyristor), a mosfet (metal Oxide Semiconductor Field Effect transistor), an igbt (insulated Gate bipolar transistor), and the like.

As shown in fig. 4-6, the heat dissipation structure 100 of the present embodiment includes a semiconductor element 110, a first conductive sheet 140, a second conductive sheet 150, and a third conductive sheet 160; the semiconductor element 110 includes a first surface and a second surface, the first surface is provided with an S-level 120 and a G-level 130, the first conductive sheet 140 is disposed on the S-level 120, the second conductive sheet 150 is disposed on the G-level 130, and the third conductive sheet 160 is disposed on the second surface; the S-stage 120 and the G-stage 130 are disconnected and have a gap. The semiconductor element 110 may be simply understood as a "chip" or a crystalline silicon layer, and may be other elements capable of implementing the above two functions, such as a flat rectangular structure as shown in fig. 2, a flat circular structure, etc., and the specific shape and configuration may be determined according to actual needs and production variations. The first surface and the second surface are generally oppositely arranged as shown in the figure, but are not necessarily oppositely arranged, and can also be adjacently arranged on the premise of not influencing the function.

The first conductive sheet 140, the second conductive sheet 150, and the third conductive sheet 160 are made of silver, which is a material that can be used for chip manufacturing at present, and the silver is selected as the conductive sheet material, so that the heat dissipation capability of the chip is improved, and the conductive sheet can be used for circuit conduction.

The first, second, and third conductive sheets 160 may be formed by electroplating, or may be fixed to the semiconductor element 110 by pressing or the like. Through the double-sided arrangement, the heat dissipation area can be increased, and the running performance of the chip is improved.

The first conductive sheet 140 has the same shape as the S-stage 120, and has an area smaller than the S-stage 120, and the first conductive sheet 140 is centrally disposed on the S-stage 120.

The second conductive sheet 150 has the same shape as the G-stage 130, and has an area smaller than the G-stage 130, and the second conductive sheet 150 is centrally disposed on the G-stage 130.

The area of the third conductive sheet 160 is the same as that of the second surface.

The edge of the S-stage 120 is 0.3mm or more from the edge of the first surface, and when the distance from the edge of the first surface is 0.6mm or more, the requirement of high pressure can be met.

The edge of the G-stage 130 is 0.3mm or more from the edge of the first surface, and when the distance from the edge of the first surface is 0.6mm or more, the requirement of high pressure can be met.

The area of the S pole 120 and the G pole 130 is not less than 80% of the first surface, and the specific silver paste coating area and range are determined according to the specification size of a chip in actual production and a chip pad area.

The coverage area of the silver is increased as much as possible, the heat dissipation capability of a subsequent chip can be enhanced, and the distance of electron transmission can be reduced.

The distance between the S pole 120 and the G pole 130 is greater than or equal to 0.2mm, and the S pole 120 and the G pole 130 may contain insulating fillers. No short circuit between the S-pole 120 and the G-stage 130 is ensured by the insulating filler.

According to the heat dissipation structure, the first and second conductive sheets with the largest area are arranged on the first surface provided with the S pole 120 and the G pole 130, and the third conductive sheet covers the second surface completely, so that the heat dissipation area is increased, the heat dissipation capacity is improved, and the running performance of a chip is improved; the S pole and the G pole are spaced reasonably to reduce the possibility of short circuit.

Example 1 can be better understood by example 2.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. The staggered packaging structure is characterized by comprising a semiconductor element (110), a first pressing sheet (200) and a second pressing sheet (300);

the semiconductor element (110) comprises a first surface and a second surface, wherein the first surface and the second surface are arranged oppositely;

a plurality of connecting ribs (400) are arranged on the periphery of the first pressing plate (200) and the second pressing plate (300), the first pressing plate (200) is connected with the first surface, the second pressing plate (300) is connected with the second surface, and after connection, any connecting rib (400) on the first pressing plate (200) is not positioned right above any connecting rib (400) on the second pressing plate (300).

2. The staggered package structure of claim 1, wherein said connecting ribs (400) are uniformly disposed around said first pressing plate (200) and said second pressing plate (300).

3. The staggered encapsulation structure of claim 2, wherein the connection rib (400) on the encapsulated first wafer (200) is located directly above the two connection ribs (400) on the second wafer (300).

4. The staggered encapsulation structure of claim 3, wherein the vertical distance between the encapsulated first wafer (200) and the encapsulated second wafer (300) is less than 0.15 mm.

5. The staggered encapsulation structure of claim 4, wherein the thickness of the tie bars (400) on the first wafer (200) is the same as the thickness of the first wafer (200).

6. The staggered encapsulation structure of claim 5, wherein the thickness of the tie bars (400) on the second wafer (300) is the same as the thickness of the second wafer (300).

7. The staggered encapsulation structure of claim 6, wherein the connecting ribs (400) on the first press plate (200) and the connecting ribs (400) on the second press plate (300) are the same size.

8. The staggered encapsulation structure of claim 7, wherein the width of the tie bars (400) on the first wafer (200) and the tie bars (400) on the second wafer (300) is 0.2-0.4 mm.

9. The staggered package structure of any of claims 1-8, wherein the area of said first paddle (200) is greater than the area of said first surface.

10. The staggered package structure of any of claims 1-8, wherein the area of said second wafer (300) is greater than the area of said second surface.