CN216528857U

CN216528857U - Flip-chip packaging structure

Info

Publication number: CN216528857U
Application number: CN202123026074.7U
Authority: CN
Inventors: 不公告发明人
Original assignee: Shenzhen Panyi Microelectronics Technology Co ltd
Current assignee: Shenzhen Panyi Microelectronics Technology Co ltd
Priority date: 2021-12-02
Filing date: 2021-12-02
Publication date: 2022-05-13
Anticipated expiration: 2031-12-02

Abstract

The utility model discloses a flip-chip packaging structure, which comprises a semiconductor element, a first conducting strip, a second conducting strip, a third conducting strip, a first pressing piece and a second pressing piece, wherein the first pressing piece is arranged on the first conducting strip; the semiconductor element comprises a first surface and a second surface, a first conducting strip and a second conducting strip are arranged on the first surface, and a third conducting strip is arranged on the second surface; the first pressing piece is provided with a first conductive end and a second conductive end, the first conductive end is connected with the first conductive piece, the second conductive end is connected with the second conductive piece, and the second pressing piece is connected with the third conductive piece. Encapsulate through the flip-chip mode, by semiconductor element, first conducting strip, second conducting strip, third conducting strip, the various structure cooperations that set up on first preforming, the second preforming have guaranteed that the electrode position is counterpointed accurately, and then normal connection uses, reduces follow-up application risk.

Description

Flip-chip packaging structure

Technical Field

The utility model relates to the technical field of electronics, in particular to a flip-chip packaging structure.

Background

Electronic products have evolved throughout toward smaller size, lighter weight, faster speed, higher frequency, lower cost, and higher reliability.

Then, when the specification of the chip becomes smaller, the problem that the electrode positions cannot be aligned accurately easily occurs in the packaging process, so that the electrodes cannot be connected normally for use, and further subsequent application risks may occur.

SUMMERY OF THE UTILITY MODEL

In order to solve the above problems, the present invention provides a flip chip package structure, which is suitable for packaging various types of devices, and can align the electrode position accurately and reduce the risk of subsequent applications.

The technical scheme adopted by the utility model is as follows:

a flip-chip packaging structure comprises a semiconductor element, a first conducting strip, a second conducting strip, a third conducting strip, a first pressing sheet and a second pressing sheet; the semiconductor element comprises a first surface and a second surface, the first conducting strip and the second conducting strip are arranged on the first surface, and the third conducting strip is arranged on the second surface; the first pressing piece is provided with a first conductive end and a second conductive end, the first conductive end is connected with the first conductive piece, the second conductive end is connected with the second conductive piece, and the second pressing piece is connected with the third conductive piece.

Preferably, the first compressed sheet comprises a first compressed sheet first divided sheet and a first compressed sheet second divided sheet.

Preferably, the first preform half is not joined to the first preform half.

Preferably, the first conductive end is arranged on the first pressing sheet and the second pressing sheet.

Preferably, the second conductive end is arranged on the first pressing piece bipartite piece.

Preferably, the connection surface of the first conductive terminal is identical to the connection surface of the first conductive sheet in shape and size.

Preferably, the connection surface of the second conductive terminal is identical to the connection surface of the second conductive sheet in shape and size.

Preferably, the second pressing sheet is provided with a protrusion.

Preferably, the protrusion is connected to the third conductive sheet.

Preferably, the shape and size of the connection surface of the protrusion are consistent with those of the connection surface of the third conductive sheet.

Preferably, the other side of the first pressing sheet is provided with a first conductive contact and a second conductive contact.

Compared with the prior art, the flip-chip packaging structure provided by the utility model is packaged in a flip-chip manner, and the electrode position alignment accuracy is ensured by matching the semiconductor element, the first conducting strip, the second conducting strip, the third conducting strip, and various structures arranged on the first pressing sheet and the second pressing sheet, so that the electrode position alignment accuracy is ensured, the electrode position alignment accuracy is further ensured, and the subsequent application risk is reduced.

Drawings

In order to more clearly explain the technical solution in the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be described below.

Fig. 1 is a schematic structural diagram of a flip-chip package structure according to an embodiment of the present invention;

fig. 2 is an exploded view of a flip-chip package structure according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a first pressing sheet in a flip-chip package structure according to an embodiment of the present invention;

fig. 4 is a schematic top view of a heat dissipation structure according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a heat dissipation structure according to an embodiment of the present invention;

fig. 6 is a schematic front view of a heat dissipation structure according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a packaged staggered package structure according to an embodiment of the present invention;

fig. 8 is an exploded view of a staggered package structure according to an embodiment of the present invention;

fig. 9 is a front view of a package with a staggered package structure according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the utility model and are not intended to limit the utility model.

The terms "first", "second", and the like in the embodiments of the present invention are only used for distinguishing related technical features, and do not indicate a sequential order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In this application, the terms "upper", "lower", "inner", "middle", "outer", "front", "rear", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings. These terms are used primarily to better describe the present application and its embodiments, and are not used to limit the indicated devices, elements or components to a particular orientation or to be constructed and operated in a particular orientation.

Moreover, some of the above terms may be used to indicate other meanings besides the orientation or positional relationship, for example, the term "on" may also be used to indicate some kind of attachment or connection relationship in some cases. The specific meaning of these terms in this application will be understood by those of ordinary skill in the art as appropriate.

Furthermore, the terms "disposed," "connected," and "secured" are to be construed broadly. For example, "connected" may be a fixed connection, a detachable connection, or a unitary construction; can be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements or components.

Example 1

The embodiment of the utility model provides a flip-chip packaging structure which is mainly applied to a chip in a power device packaging element, for example, flip-chip packaging in electronic elements such as a high-power transistor, a Thyristor, a bidirectional Thyristor GTO (Gate-Turn-Off Thyristor), a MOSFET (metal Oxide Semiconductor Field Effect transistor), an IGBT (insulated Gate bipolar transistor) and the like.

As shown in fig. 1 to 3, the semiconductor device includes a semiconductor element 110, a first conductive sheet 140, a second conductive sheet 150, a third conductive sheet 160, a first pressing sheet 200, and a second pressing sheet 300; the semiconductor device 110 includes a first surface and a second surface, wherein the first conductive sheet 140 and the second conductive sheet 150 are disposed on the first surface, and the third conductive sheet 160 is disposed on the second surface; the first pressing piece 200 is provided with a first conductive terminal 220 and a second conductive terminal 230, the first conductive terminal 220 is connected with the first conductive sheet 140, the second conductive terminal 230 is connected with the second conductive sheet 150, and the second pressing piece 300 is connected with the third conductive sheet 160.

The semiconductor element 110 may be simply understood as a "chip" or a crystalline silicon layer, and may be other elements capable of implementing the above two functions, such as a flat rectangular structure as shown in fig. 2, a flat circular structure, etc., and the specific shape and configuration may be determined according to actual needs and production variations. The first surface and the second surface are generally oppositely arranged as shown in the figure, but are not necessarily oppositely arranged, and can also be adjacently arranged on the premise of not influencing the function. Wherein the semiconductor element 110 includes, but is not limited to, an IGBT, a MOSFET, GaN, a silicon carbide chip, and the like.

The size and thickness of the semiconductor element 110 is largely dependent on the design of the packaged electronic component. Typically, the thickness of the semiconductor element 110(trench process) is 100-200 um, the thickness of the SGT (guard gate trench MOS) is typically 50-150 um, and the size of the semiconductor element 110 is from 2.0 × 3.0mm to 5.0 × 6.0 mm.

The first compressed piece 200 comprises a first compressed piece first sub-piece 200-1 and a first compressed piece second sub-piece 200-2, and the first compressed piece first sub-piece 200-1 and the first compressed piece second sub-piece 200-2 are not connected with each other. Thus, the first press piece-one segment 200-1 and the first press piece-two segment 200-2 are connected to different electrodes on the semiconductor element 110, respectively. The first conductive terminal 220 is disposed on the first segment 200-1, and the second conductive terminal 230 is disposed on the second segment 200-2.

The connection surface of the first conductive terminal 220 is identical to the connection surface of the first conductive sheet 140 in shape and size, and the connection surface of the second conductive terminal 230 is identical to the connection surface of the second conductive sheet 150 in shape and size. The connecting surfaces for connecting the two are the same in shape and size, so that the connection is more stable and the production is facilitated.

The second pressing piece 300 is provided with a protrusion 310, and the protrusion 310 is connected with the third conductive sheet 160. The connection surface of the protrusion 310 is identical to the connection surface of the third conductive sheet 160 in shape and size. A first conductive contact and a second conductive contact are provided on one surface of the first pressing piece 200.

Thus, as seen in fig. 1-3, the contactable area of the second conductive contact is significantly larger than the second conductive terminal 230 disposed on the first pressing piece two-piece 200-2, which is equivalent to enlarging the contactable area of the electrode on the semiconductor element 110 through the first pressing piece 200, thereby ensuring the accurate alignment of the subsequent electrode and reducing the risk of subsequent application. The corresponding protrusion 310 provided on the second pressing piece 300 also serves to enlarge the contact area of the electrode on the semiconductor element 110.

Example 2

The present embodiment provides a heat dissipation structure 100, which includes a semiconductor element 110, a first conductive sheet 140, a second conductive sheet 150, and a third conductive sheet 160; the semiconductor element 110 includes a first surface and a second surface, the first surface is provided with an S-level 120 and a G-level 130, the first conductive sheet 140 is disposed on the S-level 120, the second conductive sheet 150 is disposed on the G-level 130, and the third conductive sheet 160 is disposed on the second surface; the S-stage 120 and the G-stage 130 are disconnected and have a gap. The semiconductor element 110 may be simply understood as a "chip" or a crystalline silicon layer, and may be other elements capable of implementing the above two functions, such as a flat rectangular structure as shown in fig. 2, a flat circular structure, etc., and the specific shape and configuration may be determined according to actual needs and production variations. The first surface and the second surface are generally oppositely arranged as shown in the figure, but are not necessarily oppositely arranged, and can also be adjacently arranged on the premise of not influencing the function.

The first conductive sheet 140, the second conductive sheet 150, and the third conductive sheet 160 are made of silver, which is a material that can be used for chip manufacturing at present, and the silver is selected as the conductive sheet material, so that the heat dissipation capability of the chip is improved, and the conductive sheet can be used for circuit conduction.

The first, second, and third conductive sheets 160 may be formed by electroplating, or may be fixed to the semiconductor element 110 by pressing or the like. Through the double-sided arrangement, the heat dissipation area can be increased, and the running performance of the chip is improved.

The first conductive sheet 140 has the same shape as the S-stage 120, and has an area smaller than the S-stage 120, and the first conductive sheet 140 is centrally disposed on the S-stage 120.

The second conductive sheet 150 has the same shape as the G-stage 130, and has an area smaller than the G-stage 130, and the second conductive sheet 150 is centrally disposed on the G-stage 130.

The area of the third conductive sheet 160 is the same as that of the second surface.

The edge of the S-stage 120 is 0.3mm or more from the edge of the first surface, and when the distance from the edge of the first surface is 0.6mm or more, the requirement of high pressure can be met.

The edge of the G-stage 130 is 0.3mm or more from the edge of the first surface, and when the distance from the edge of the first surface is 0.6mm or more, the requirement of high pressure can be met.

The area of the S pole 120 and the G pole 130 is not less than 80% of the first surface, and the specific silver paste coating area and range are determined according to the specification size of a chip in actual production and a chip pad area.

The coverage area of the silver is increased as much as possible, the heat dissipation capability of a subsequent chip can be enhanced, and the distance of electron transmission can be reduced.

The distance between the S pole 120 and the G pole 130 is greater than or equal to 0.2mm, and the S pole 120 and the G pole 130 may contain insulating fillers. No short circuit between the S-pole 120 and the G-stage 130 is ensured by the insulating filler.

In the heat dissipation structure of the embodiment, the first and second conductive sheets with the largest area as possible are arranged on the first surface provided with the S pole 120 and the G pole 130, and the third conductive sheet covers the second surface completely, so that the heat dissipation area is increased, the heat dissipation capability is improved, and the operation performance of the chip is improved; the S pole and the G pole are spaced reasonably to reduce the possibility of short circuit.

Example 1 can be better understood by example 2.

Example 3

The present embodiment provides a staggered package structure, which is mainly a chip applied in a power device package component, for example, a waterproof package structure applied in electronic components such as a high-power transistor, a Thyristor, a bidirectional Thyristor GTO (Gate-Turn-Off Thyristor), a mosfet (metal Oxide Semiconductor Field Effect transistor), an igbt (insulated Gate bipolar transistor), and the like, and can be applied to the staggered package structure of the present embodiment as long as the components and parts are consistent with the present application.

As shown in fig. 7-9, comprises a semiconductor element 110, a first pressing piece 200, a second pressing piece 300; the semiconductor element 110 includes a first surface and a second surface, the first surface and the second surface being disposed opposite to each other; a plurality of connecting ribs 400 are arranged on the periphery of the first pressing plate 200 and the second pressing plate 300, the first pressing plate 200 is connected with the first surface, the second pressing plate 300 is connected with the second surface, and any connecting rib 400 on the first pressing plate 200 is not positioned right above any connecting rib 400 on the second pressing plate 300 after connection.

The upper and lower pressing sheets for packaging mostly adopt the same pressing sheet, so that the connecting rib 400 of the upper pressing sheet is positioned right above the connecting rib 400 of the lower pressing sheet after packaging, when the specification of the semiconductor element 110 is reduced, the linear distance between the connecting ribs 400 on the upper and lower pressing sheets is also reduced, for example, when the specification is smaller than 0.15mm, in the subsequent application (such as PCB welding) process, the direct short circuit of the two pressing sheets is easily caused, the normal use of the semiconductor element 110 is influenced, and even the semiconductor element is damaged. Any connecting rib 400 on the first pressing plate 200 is not positioned right above any connecting rib 400 on the second pressing plate 300, so that the linear distance between the connecting ribs 400 on the upper and lower pressing plates is increased.

The connecting rib 400 is uniformly arranged around the first pressing plate 200 and the second pressing plate 300, and the connecting rib 400 is uniformly arranged so that the stress of each connecting rib 400 is uniform, thereby avoiding the occurrence of the damage caused by the overlarge stress of the single connecting rib 400.

The connecting ribs 400 of the first wafer 200 after encapsulation are positioned directly above the two connecting ribs 400 of the second wafer 300. In this way, the straight distance between the connection ribs 400 is increased as much as possible without changing the size and number of the connection ribs 400.

The vertical distance between the first pressing plate 200 and the second pressing plate 300 after being packaged is less than 0.15mm, so that if the upper and lower pressing plates adopt the same pressing plate, the connecting rib 400 of the upper pressing plate after being packaged is positioned right above the connecting rib 400 of the lower pressing plate, and the linear distance between the connecting ribs 400 on the upper and lower pressing plates is also less than 0.15mm, so that in the subsequent application (such as PCB welding), the two pressing plates are easily directly short-circuited to influence the normal use of the semiconductor element 110.

The thickness of the connecting rib 400 on the first pressing plate 200 is the same as that of the first pressing plate 200, and the thickness of the connecting rib 400 on the second pressing plate 300 is the same as that of the second pressing plate 300. In actual manufacturing activities, the thickness of the tie bar 400 is generally the same as the thickness of the preform, taking into account the ease of manufacturing the preform, and the strength of the tie bar 400.

The connecting ribs 400 on the first pressing plate 200 are the same size as the connecting ribs 400 on the second pressing plate 300.

The width of the connecting rib 400 on the first pressing plate 200 and the width of the connecting rib 400 on the second pressing plate 300 are 0.2-0.4 mm.

The area of the first segment 200 is greater than that of the first surface, and the area of the second segment 300 is greater than that of the second surface.

Compared with the prior art, the dislocation packaging structure of this embodiment, through the position of the splice bar on the first preforming that the adjustment is used for the encapsulated component and the second preforming, make the encapsulated preforming expose partial hookup location stagger, under the unchangeable condition of splice bar quantity on each preforming, increased the linear distance between the splice bar on first preforming and the second preforming, reduced the short circuit risk.

The flip-chip package structure of embodiment 1 can be better understood by embodiment 3.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A flip-chip packaging structure is characterized by comprising a semiconductor element (110), a first conducting strip (140), a second conducting strip (150), a third conducting strip (160), a first pressing sheet (200) and a second pressing sheet (300);

the semiconductor element (110) comprises a first surface and a second surface, the first conducting strip (140) and the second conducting strip (150) are arranged on the first surface, and the third conducting strip (160) is arranged on the second surface;

one surface of the first pressing sheet (200) is provided with a first conductive end (220) and a second conductive end (230), the first conductive end (220) is connected with the first conductive sheet (140), the second conductive end (230) is connected with the second conductive sheet (150), and the second pressing sheet (300) is connected with the third conductive sheet (160).

2. The flip-chip packaging structure of claim 1, wherein the first die (200) comprises a first die one segment (200-1) and a first die two segment (200-2).

3. The flip-chip packaging structure of claim 2, wherein the first die-to-die (200-1) and the first die-to-die (200-2) are not connected to each other.

4. The flip-chip package structure of claim 3, wherein the first conductive terminal (220) is disposed on the first tab segment (200-1).

5. The flip-chip package structure of claim 4, wherein the second conductive terminals (230) are disposed on the first die paddle (200-2).

6. The flip-chip packaging structure of claim 5, wherein the connection surface of the first conductive terminal (220) is identical to the connection surface of the first conductive sheet (140) in shape and size.

7. The flip-chip packaging structure of claim 6, wherein the connection surface of the second conductive terminal (230) is identical to the connection surface of the second conductive sheet (150) in shape and size.

8. The flip-chip package structure of claim 7, wherein the second pressing sheet (300) is provided with a bump (310), and the bump (310) is connected to the third conductive sheet (160).

9. The flip-chip packaging structure according to claim 8, wherein the connection surface of the bump (310) is identical to the connection surface of the third conductive sheet (160) in shape and size.

10. The flip-chip package structure according to any one of claims 1 to 9, wherein the first pad (200) is provided with a first conductive contact and a second conductive contact on the other side.