CN216671626U - Frameless semiconductor packaging structure - Google Patents
Frameless semiconductor packaging structure Download PDFInfo
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- CN216671626U CN216671626U CN202220228733.0U CN202220228733U CN216671626U CN 216671626 U CN216671626 U CN 216671626U CN 202220228733 U CN202220228733 U CN 202220228733U CN 216671626 U CN216671626 U CN 216671626U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The utility model discloses a frameless semiconductor packaging structure.A semiconductor packaging unit comprises a plastic packaging body, a lead, a chip, a bonding layer and two carrier base islands which are connected from top to bottom; the carrier substrate island comprises a gold-plated layer, a nickel-plated support body and a silver-plated layer which are formed by electroplating layer by layer from bottom to top; the top surface of at least one silver coating is connected with a chip through an adhesive layer, one end of a lead is connected with the top of one chip, and the other end of the lead is connected with the top of another chip or the top of another silver coating; the plastic package body surrounds the lead, the chip, the bonding layer, the silver coating layer and the nickel plating support body from top to bottom, the plastic package body downwards surrounds the top and the outer side surface of the gold coating layer, the bottom surface of the gold coating layer is flush with the bottom surface of the plastic package body, and the bottom surface of the gold coating layer is electrically connected with the outside; the chip connected through the lead wire, the silver coating layer, the nickel plating support body and the gold coating layer form an electrical connection channel; the carrier base islands formed by electroplating are mutually independent and have smaller thickness.
Description
Technical Field
The utility model relates to the technical field of semiconductors, in particular to a frameless semiconductor packaging structure.
Background
The semiconductor in the prior art is produced by packaging a frame serving as a base island, the frame is made of metal and is formed by stamping or etching, an adhesive layer is covered on the back surface of the frame, so that arching is easy to occur, the phenomena of glue overflow and glue residue after plastic packaging are caused, the tube pin weldability of a product is influenced, the frame with the adhesive layer on the back surface is provided, connecting ribs are exposed on the periphery after forming and cutting, layering and burrs are easy to occur, and the reliability and the finished product qualification rate of the product are influenced; moreover, the thickness of the frame body is 0.2mm or more, and the structural defects thereof prevent the realization of thinner packaging requirements.
Therefore, it is difficult for the conventional semiconductor structure including a frame to satisfy the quality requirements of the current consumer electronic products with reduced weight, multiple functions, high integration, and high reliability.
SUMMERY OF THE UTILITY MODEL
In view of the above problems, an object of the present invention is to provide a frameless semiconductor package structure to meet the requirement of thinner package.
In order to achieve the purpose, the utility model adopts the following technical scheme:
a frameless semiconductor packaging structure comprises at least one semiconductor packaging unit, wherein the semiconductor packaging unit comprises a plastic packaging body, a lead, a chip, an adhesive layer and two carrier base islands which are connected from top to bottom;
the carrier substrate island comprises a gold-plated layer, a nickel-plated support body and a silver-plated layer which are formed by electroplating layer by layer from bottom to top;
the top surface of at least one silver coating is connected with one chip through the bonding layer, one end of the lead is connected with the top of one chip, and the other end of the lead is connected with the top of another chip or the top of another silver coating;
the plastic-sealed body surrounds from top to bottom the lead wire the chip the tie coat the silvered film with the nickel plating supporter, just the plastic-sealed body surrounds downwards the top and the lateral surface of gilt layer, the bottom surface parallel and level of gilt layer in the bottom surface of plastic-sealed body, the bottom surface and the outside electric connection of gilt layer.
Furthermore, the LED lamp also comprises a metal substrate;
the metal substrate is positioned below the plastic package body and the gold-plated layer, and the top surface of the metal substrate is used for bearing the gold-plated layer in the semiconductor packaging unit and the plastic package body.
Specifically, the top edge of the nickel-plated support body protrudes out of the outer side surface of the nickel-plated support body towards the periphery, and the surface of the top edge of the nickel-plated support body is bent and sagged;
the edge of the silver plating layer protrudes out of the top edge of the nickel plating support body by 0.005-0.055 mm;
the bottom surface of the nickel-plated support body is consistent with the top surface of the gold-plated layer in shape and size;
the edge of the silver plating layer protrudes out of the top edge of the nickel plating support body towards the periphery;
the edge of the silver plating layer and the top edge of the nickel plating supporting body form a mechanical connection structure which is buckled with the plastic package body.
Preferably, the bottom surface of the silver plating layer is consistent with the top surface of the nickel plating support body in shape and size;
the thickness of the silver coating is not less than 0.002 mm.
Preferably, the thickness of the gold-plating layer is not less than 0.00005 mm.
Preferably, the overall thickness of the carrier substrate is 0.060 ± 0.02mm, and the thickness of the nickel-plated support is 0.05 ± 0.005 mm.
Furthermore, one corner of the carrier base island positioned on the same side in each semiconductor packaging unit is subjected to chamfering treatment and is used for marking the polarity direction of the semiconductor packaging unit.
The technical scheme of the utility model has the beneficial effects that: the frameless semiconductor packaging structure adopts the layout of the frameless connecting ribs, has smaller thickness compared with the traditional semiconductor packaging unit with the frame structure, is beneficial to realizing the production of thinner and miniaturized packaged semiconductor devices, and can also improve the production efficiency and stability of the scribing process of semiconductor packaging finished products; the plastic package body 5 fully encapsulates the chip 3, the chip 3 and the carrier substrate 1 form a vertical connection structure, a heat conduction path can be reduced, the performance of rapid outward heat conduction is improved, the air tightness is high, and the product reliability is good.
Drawings
Fig. 1 is a schematic structural view of a packaging unit containing a single core structure of one embodiment of the frameless semiconductor package structure of the present invention;
fig. 2 is a schematic structural view of a packaging unit containing a dual-core structure of one embodiment of the frameless semiconductor package structure of the present invention;
fig. 3 is a schematic structural diagram of a multi-core package containing multiple dual-core structures for one embodiment of the frameless semiconductor package structure of the present invention;
fig. 4 is a schematic structural view of a multi-core package containing multiple single-core structures of one embodiment of the frameless semiconductor package structure of the present invention;
fig. 5 is a schematic top view of a metal substrate of an embodiment of the frameless semiconductor package structure of the present invention;
fig. 6 is a schematic structural view of a carrier island during fabrication of one embodiment of the frameless semiconductor package structure of the present invention;
fig. 7 is a partially enlarged view of a portion a of fig. 5;
FIG. 8 is a schematic diagram of a structure during fabrication of a multi-core package using a flip-chip process;
wherein: a carrier base island 1; an adhesive layer 2; a chip 3; a lead 4; a plastic package body 5; a metal substrate 6; a gold plating layer 11; a nickel-plated support 12; and a silver plating layer 13.
Detailed Description
The technical solution of the present invention is further described by the following embodiments in conjunction with the accompanying fig. 1-8.
The drawings are for illustrative purposes only and are not to be construed as limiting the patent; for the purpose of better illustrating the present embodiments, certain elements of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, so to speak, as communicating between the two elements. The specific meanings of the above terms in the present invention can be understood as specific cases by those skilled in the art.
In the description of the present invention, it is to be understood that the orientation or positional relationship indicated by the orientation words such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc. are usually based on the orientation or positional relationship shown in the drawings, and are only for convenience of description and simplicity of description, and in the case of not making a reverse description, these orientation words do not indicate and imply that the device or element being referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore, should not be considered as limiting the scope of the present invention; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.
A frameless semiconductor packaging structure comprises at least one semiconductor packaging unit, wherein the semiconductor packaging unit comprises a plastic packaging body 5, a lead 4, a chip 3, an adhesive layer 2 and two carrier base islands 1 which are connected from top to bottom;
the carrier substrate island 1 comprises a gold-plated layer 11, a nickel-plated support body 12 and a silver-plated layer 13 which are formed by electroplating layer by layer from bottom to top;
the top surface of at least one silver coating layer 13 is connected with one chip 3 through the bonding layer 2, one end of the lead 4 is connected with the top of one chip 3, and the other end of the lead 4 is connected with the top of the other chip 3 or the top of the other silver coating layer 13;
the plastic-sealed body 5 surrounds from top to bottom lead wire 4 the chip 3 the tie coat 2 silver coating layer 13 with nickel plating supporter 12, just the plastic-sealed body 5 surrounds downwards the top and the lateral surface of gold coating 11, the bottom surface parallel and level of gold coating 11 in the bottom surface of plastic-sealed body 5, the bottom surface and the outside electric connection of gold coating 11.
As shown in fig. 1-2, in the frameless semiconductor package structure of the present invention, an assembly of the gold plating layer 11, the nickel plating support 12 and the silver plating layer 13 is defined as a carrier substrate 1, one end of the lead 4 is connected to the top of one chip 3, and the other end of the lead 4 is connected to the top of another chip 3, so as to form a dual-chip semiconductor package unit; or one end of the lead 4 is connected with the top of one chip 3, and the other end of the lead 4 is connected with the top of the other silver-plated layer 13 to form a single-chip semiconductor packaging unit; the chip 3 connected through the lead 4, the silver coating layer 13, the nickel plating support body 12 and the gold coating layer 11 form an electrical connection channel; the carrier base islands 1 formed by electroplating are mutually independent, and the packaging structure of the semiconductor packaging unit adopts a layout without frame connecting ribs, so that the semiconductor packaging unit has smaller thickness compared with the traditional semiconductor packaging unit with a frame structure, is beneficial to realizing the production of thinner and miniaturized packaged semiconductor devices, and can also improve the production efficiency and stability of the scribing process of semiconductor packaging finished products; the plastic package body 5 fully encapsulates the chip 3, the chip 3 and the carrier substrate 1 form a vertical connection structure, a heat conduction path can be reduced, the performance of rapid outward heat conduction is improved, the air tightness is high, and the product reliability is good.
Further, the device also comprises a metal substrate 6;
the metal substrate 6 is located below the plastic package body 5 and the gold plating layer 11, and the top surface of the metal substrate 6 is used for bearing the gold plating layer 11 and the plastic package body 5 in the semiconductor package unit.
As shown in fig. 5 to 7, the adopted metal substrate 6 can be a stainless steel plate or a copper plate, which can improve the production efficiency of electroplating the silver plating layer 13, the nickel plating support 12 and the gold plating layer 11; in the preparation process, the chip 3 connected with the metal substrate 6 and the lead 4, the silver plating layer 13, the nickel plating support body 12 and the gold plating layer 11 form an electric loop; in addition, the traditional semiconductor packaging process with the frame only can adopt a resin blade to perform scribing to form a packaging unit, and the scribing process of the semiconductor packaging body after the metal substrate 6 is removed can adopt a metal blade to perform scribing, so that compared with the prior art, the material cost can be saved again, the production speed of scribing can be greatly improved, and the manufacturing cost advantage is good.
Specifically, the top edge of the nickel-plated support body 12 protrudes outward from the outer side surface of the nickel-plated support body 12, and the surface of the top edge of the nickel-plated support body 12 is bent and sagged;
the edge of the silver plating layer 13 protrudes out of the top edge of the nickel plating support body 12 by 0.005-0.055 mm;
the bottom surface of the nickel-plated support body 12 is consistent with the top surface of the gold-plated layer 11 in shape and size;
the edge of the silver plating layer 13 protrudes from the top edge of the nickel plating support body 12 towards the periphery;
the edge of the silver plating layer 13 and the top edge of the nickel plating support body 12 form a mechanical connection structure with the plastic package body 5 in a mutually buckled mode.
As shown in fig. 1 to 4, the edge of the silver plating layer 13 and the top edge of the nickel plating support 12 respectively form a mechanical connection structure with the plastic package body 5, which can prevent the internal structure of the semiconductor package unit from being layered under the action of external force during the cutting process, effectively prevent the chip 3 from loosening, improve the air tightness of the semiconductor package unit, prevent water vapor from permeating, and improve the reliability of the product.
The edge of the silver plating layer 13 protrudes to the periphery from the top edge of the nickel plating support body 12, so that the electric conduction and heat conduction area of the silver plating layer 13 can be increased, and the phenomenon of electric leakage of the chip 3 caused by overlarge thickness of the silver plating layer 13 can be prevented.
Preferably, the bottom surface of the silver plating layer 13 is consistent with the top surface of the nickel plating support body 12 in shape and size;
the thickness of the silver plating layer 13 is not less than 0.002 mm.
The thickness of the silver coating layer 13 is not less than 0.002mm, which can ensure the electric conduction and heat conduction performance of the carrier substrate 1, meet the welding requirement in the production process and prevent the nickel layer from migrating.
Preferably, the thickness of the gold-plating layer 11 is not less than 0.00005 mm.
The thickness of the gold-plating layer 11 is not less than 0.00005mm, so that the conductivity of the semiconductor packaging finished product can be ensured, and the increase of the production cost caused by the excessive thickness of the gold-plating layer 11 can be avoided.
Preferably, the entire thickness of the carrier base island 1 is 0.060 ± 0.02mm, and the thickness of the nickel-plated support 12 is 0.05 ± 0.005 mm.
The thickness of the conventional frame is more than 0.2mm, the overall thickness of the carrier base island 1 of the embodiment is controlled to be 0.060 ± 0.02mm, the thickness of the carrier base island 1 is less than 1/3 of the thickness of the conventional frame, the total thickness of the semiconductor packaging unit is not more than 0.3mm, the packaging requirement of high integration level can be met, and the production of ultra-thin semiconductor packaging finished products can be realized.
Furthermore, one corner of the carrier base island 1 on the same side in each semiconductor packaging unit is chamfered to identify the polarity direction of the semiconductor packaging unit.
In an electroplating-grown Block (Block) of the metal substrate 6 as shown in fig. 7, one corner of one of the carrier base islands 1 on the same side in each of the semiconductor package units in the same row or column of the package array is chamfered, and the chamfered carrier base island 1 can identify the polarity direction of the semiconductor package unit, so that the chamfered carrier base island 1 can be used as a first lead and another carrier base island 1 which is not chamfered can be used as a second lead in later electronic product preparation.
The above process for manufacturing the frameless semiconductor package structure includes the following steps:
s1) using the top surface of the straight and warp-free metal substrate 6 as the plating growth plane of the carrier base island 1, and arranging four blocks at equal intervals on the top surface of the metal substrate 6 as the areas for supporting the growth of the carrier base island 1;
s2) arranging and electroplating the gold-plated layer 11 in an array at equal intervals in each block; the size of the gold-plating layer 11 is set to 0.23mm x 0.19mm, and the thickness of the gold-plating layer 11 is not less than 0.00005 mm;
s3), growing and forming the nickel plating support body 12 on the surface of the gold plating layer 11 by adopting a layer-by-layer growth technology; the top of the nickel-plated support body 12 is set to be 0.27mm by 0.23mm, and the thickness of the nickel-plated support body 12 is 0.05 +/-0.005 mm; the top edge of the nickel-plated support body 12 protrudes outwards from the outer side surface of the nickel-plated support body 12, and the surface of the top edge of the nickel-plated support body 12 is bent and sagged; the thickness of the silver plating layer 13 is not less than 0.002mm, and the edge of the silver plating layer 13 protrudes out of the top edge of the nickel plating support body 12 towards the periphery; the downward projection size of the silver plating layer 13 is the same as the downward projection size of the nickel plating support body 12; the whole thickness of the prepared carrier base island 1 is 0.060 +/-0.02 mm;
s4) forming the silver plating layer 13 on the surface of the nickel-plated support 12 by electroplating growth to obtain the carrier base islands 1, forming a package substrate by matching two adjacent carrier base islands 1 distributed in an array, chamfering one corner of one carrier base island 1 in the package substrate, and defining the carrier base island 1 as a first pin and the other carrier base island 1 matched with the carrier base island as a second pin;
s5) scribing the wafer by matching the size of the gold plating layer 11 to obtain the chip 3; the chip 3 is a chip with the thickness of 100 +/-50 mu m, and is scribed by using a single knife or double knives;
s6) coating an adhesive material on the surface of the carrier base island 1, and placing the chip 3 on the surface of the carrier base island 1 to obtain a body to be packaged containing the adhesive material;
s7) if a single-core structure is selected, firstly solidifying the adhesive material to form the adhesive layer 2 through high-temperature solidification, and then connecting the welding spot on the top of the chip 3 of the first pin with the silver coating 13 on the top surface of the second pin through the lead 4; if a dual-core structure is selected, the bonding material is solidified to form the bonding layer 2 through pressure welding, and then the welding spot of the chip 3 positioned on the first pin is connected with the welding spot of the chip 3 positioned on the second pin through the lead 4;
s8) performing injection molding and encapsulation on the leads 4, the chip 3, the bonding layer 2 and the island carrier 1 in the four blocks by using a plastic molding machine and a mold to form four packaging blocks;
s9) removing the metal substrate 6 at the bottom of the package block by a physical method to expose the bottom surface of the gold plating layer 11, thereby obtaining a package body with the block as a unit;
s10) dividing the package into individual units each having the package substrate as a unit, using a metal blade, to obtain the semiconductor package unit.
Fig. 5 shows the metal substrate 6 of the above-described example, and the carrier base islands 1 on the metal substrate 6 in the production process shown in fig. 6 and 7.
On the metal substrate 6, single core packaging unit and two core packaging unit batch production can be carried out through carrier base island 1 in step, still can divide into the multicore encapsulation body that contains a plurality of encapsulation units as required to satisfy different encapsulation and set up the requirement, can practice thrift the die sinking expense, reduction in production cost promotes the competitiveness of product.
In order to facilitate the direction recognition of the product control circuit, in step S7), when the single-core structure is selected, the chip 3 may be selectively placed on the upper surface of the first pin, or may be selectively placed on the upper surface of the second pin.
In the above embodiment, the size of the gold plating layer 11 is 0.23mm by 0.19mm, which can provide a sufficient soldering area for the later use of the semiconductor package unit; the silver plating layer 13 and the nickel plating supporting body 12 are 0.27mm by 0.23mm, the silver plating layer 13 protrudes outwards by 0.04mm, and the effective area of a welding surface during welding of the lead 2 can be enlarged; the thickness of the chip 3 is 100 +/-50 mu m, enough space can be reserved for the welding radian of the lead 2, and the thickness of the prepared semiconductor packaging unit is not more than 0.3 mm.
The chip 3 can be mounted in a gluing mode, a reflow soldering mode or a wave soldering mode so as to adapt to different chips 3 and obtain better mounting firmness of the chips 3.
As shown in fig. 8, if the chip 3 is formed by a flip chip process, two ends of the chip 3 are respectively mounted on the two carrier islands 1, and then are soldered to the top surfaces of the two carrier islands 1 by wave soldering or reflow soldering, the chip 3 is connected to the two carrier islands 1 and the metal substrate 6 to form an electrical circuit, and it is not necessary to connect the two carrier islands 1 by using the leads 4 and perform the bonding step of step S7).
In summary, as shown in fig. 1 to 8, the frameless semiconductor package structure according to the embodiments of the present invention adopts a layout of frameless ribs, so that the frameless semiconductor package structure has a smaller thickness than a conventional semiconductor package unit with a frame structure, which is beneficial for realizing the production of thinner and miniaturized packaged semiconductor devices, and can also improve the production efficiency and stability of the dicing process of the semiconductor package finished product; the plastic package body 5 fully encapsulates the chip 3, the chip 3 and the carrier substrate 1 form a vertical connection structure, a heat conduction path can be reduced, the performance of rapid outward heat conduction is improved, the air tightness is high, and the product reliability is good.
The technical principles of the present invention have been described above with reference to specific embodiments. The description is made for the purpose of illustrating the principles of the utility model and should not be construed in any way as limiting the scope of the utility model. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive effort, which would fall within the scope of the present invention.
Claims (7)
1. A frameless semiconductor packaging structure is characterized by comprising at least one semiconductor packaging unit, wherein the semiconductor packaging unit comprises a plastic packaging body, a lead, a chip, an adhesive layer and two carrier islands which are connected from top to bottom;
the carrier substrate island comprises a gold-plated layer, a nickel-plated support body and a silver-plated layer which are formed by electroplating layer by layer from bottom to top;
the top surface of at least one silver coating is connected with one chip through the bonding layer, one end of the lead is connected with the top of one chip, and the other end of the lead is connected with the top of another chip or the top of another silver coating;
the plastic-sealed body surrounds from top to bottom the lead wire the chip the tie coat the silvered film with the nickel plating supporter, just the plastic-sealed body surrounds downwards the top and the lateral surface of gilt layer, the bottom surface parallel and level of gilt layer in the bottom surface of plastic-sealed body, the bottom surface and the outside electric connection of gilt layer.
2. The frameless semiconductor package structure of claim 1, further comprising a metal substrate;
the metal substrate is positioned below the plastic package body and the gold-plated layer, and the top surface of the metal substrate is used for bearing the gold-plated layer in the semiconductor packaging unit and the plastic package body.
3. The frameless semiconductor package structure of claim 1, wherein the top edge of the nickel-plated support protrudes peripherally beyond the outer side of the nickel-plated support, and the surface of the top edge of the nickel-plated support is bent downwardly;
the edge of the silver plating layer protrudes out of the top edge of the nickel plating support body by 0.005-0.055 mm;
the bottom surface of the nickel-plated support body is consistent with the top surface of the gold-plated layer in shape and size;
the edge of the silver plating layer protrudes out of the top edge of the nickel plating support body towards the periphery;
the edge of the silver plating layer and the top edge of the nickel plating supporting body form a mechanical connection structure which is buckled with the plastic package body.
4. The frameless semiconductor package structure of claim 3, wherein the bottom surface of the silver-plated layer conforms to the top surface of the nickel-plated support;
the thickness of the silver coating is not less than 0.002 mm.
5. The frameless semiconductor package structure of claim 1, wherein the gold-plating layer has a thickness of not less than 0.00005 mm.
6. The frameless semiconductor package structure of claim 1, wherein the carrier base island has an overall thickness of 0.060 ± 0.02mm, and the nickel-plated support has a thickness of 0.05 ± 0.005 mm.
7. The frameless semiconductor package structure of claim 1, wherein a corner of the carrier base island on the same side in each semiconductor package unit is chamfered for identifying a polarity direction of the semiconductor package unit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202220228733.0U CN216671626U (en) | 2022-01-27 | 2022-01-27 | Frameless semiconductor packaging structure |
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| CN202220228733.0U CN216671626U (en) | 2022-01-27 | 2022-01-27 | Frameless semiconductor packaging structure |
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