CN216162679U

CN216162679U - High-energy-efficiency amplifier

Info

Publication number: CN216162679U
Application number: CN202122211501.2U
Authority: CN
Inventors: 解宁; 李梧萤; 王欣
Original assignee: Shanghai Institute of Technical Physics of CAS
Current assignee: Shanghai Institute of Technical Physics of CAS
Priority date: 2021-09-14
Filing date: 2021-09-14
Publication date: 2022-04-01
Anticipated expiration: 2031-09-14

Abstract

The patent relates to the technical field of electronic circuits, in particular to an energy-efficient amplifier, which comprises more than one transistor, more than one switch and more than one capacitor which are integrated in the same circuit, wherein the transistor, the switch and the capacitor are connected to form an output end V of the amplifier_ONAnd V_OPAnd an input terminal V_IPAnd V_IN(ii) a This patent introduces an energy storage capacitor C in the amplifier structure_RESThe floating power supply provides bias current for the amplifier, so that the amplifier can normally perform amplification operation. And in the amplification process, the energy storage capacitor C_RESThe overdrive voltage of the input transistor is reduced, and the high energy efficiency of the amplifier is improved. At the same time, the amplifier also adopts a method based on inversionDue to the structure of the amplifier, current multiplexing is realized, and the energy efficiency of the amplifier is improved. Therefore, the method has a wide application prospect in the design of comparators with low power consumption and high energy efficiency, particularly in the design of full-dynamic comparators.

Description

High-energy-efficiency amplifier

Technical Field

The patent relates to the technical field of electronic circuits, in particular to an energy-efficient amplifier.

Background

The operational amplifier is one of the most important basic circuit units in an analog integrated circuit and a digital-analog hybrid integrated circuit, can realize the amplification and transmission of signals, and can realize the functions of signal operation, filtering and the like by adding appropriate peripheral components.

With the continuous forward development of semiconductor technology, the characteristic size of the semiconductor technology is also continuously reduced, the integration level of a chip is also higher and higher, the power consumption is one of factors restricting the development of an analog integrated circuit and a digital-analog hybrid integrated circuit, and the power supply voltage and the quiescent current of an integrated circuit chip jointly determine the power consumption of the chip.

Nowadays, in some applications of electronic systems, such as portable products, in order to meet the requirement of long-time operation, a lower power supply voltage and a lower power consumption are required, and meanwhile, the low power consumption also responds to the environmental protection concept of green energy conservation and emission reduction, and conforms to the trend of times development.

In recent years, researchers at home and abroad have made many studies on the subject of low power consumption amplifiers, and all in all, amplifiers are continuously developed towards the directions of high gain and low power consumption.

Disclosure of Invention

In view of the deficiencies of the prior art, the present patent discloses a high energy efficient amplifier for achieving high gain and low power consumption of the amplifier.

The patent is realized by the following technical scheme:

the patent provides an energy-efficient amplifier, including more than one transistor, more than one switch and more than one electric capacity integrated in the same circuit, wherein, this transistor, switch and electric capacity connect and constitute output V of this amplifier_ONAnd V_OPAnd an input terminal V_IPAnd V_IN(ii) a At the same time, the user can select the desired position,

the output V of the amplifier is in the reset state_ON、V_OPAnd C in the capacitor_XIs reset to a common mode level V_cm；

Amplifying the differential input signal when the amplifier is in the amplifying state, and outputting the amplified signal at the output end V of the amplifier_ONAnd V_OPObtaining a differential output voltage, under the action of a differential input signal, a node V_S-Is lowered, node V_S+The potential of (2) rises.

Further, the transistors include M1, M2, M3, M4, M5, M6, M7, and M8; the switch comprises S1 and S2; the capacitor comprises C_RESAnd C_X。

Furthermore, the sources of the transistors M1 and M2 are connected and connected to the capacitor C through a switch_RESThe drains of the transistors M1, M2 are connected to the sources of the transistors M3, M4, respectively.

Further, the gates of the transistors M3, M4 are connected and connected to a bias voltage V_BPThe drains of the transistors M3 and M4, the drains of the transistors M5 and M6, and the capacitor C_XAre connected to form the output end V of the amplifier_ONAnd V_OP。

Further, the capacitor C_XThe upper pole plate of the switch is connected with a common mode voltage V through switches S1 and S2_cmConnected with its lower plate connected to ground potential.

Further, the gates of the transistors M5, M6 are connected in parallel to a bias voltage V_BNAnd the sources thereof are connected to the drains of the transistors M7, M8.

Furthermore, the sources of the transistors M7 and M8 are connected and connected to the capacitor C through a switch_RESAnd the gates of the transistors M1, M7 are connected as the input V of the amplifier_IPThe gates of the transistors M2, M8 are connected as the input V of the amplifier_IN。

Furthermore, the capacitor C is arranged in the reset state of the amplifier_RESThe upper electrode plate of the capacitor is connected with a power supply potential, and the capacitor C_RESThe upper plate potential is precharged to the power supply potential, the capacitor C_RESIs connected to ground potential and the switches S1, S2 are turned on, the output V of the amplifier is connected to ground potential_ON，V_OPAnd a capacitor C_XIs reset to a common mode level V_cm。

Furthermore, when the amplifier is in an amplifying state, the capacitor C_RESIs connected to the sources of transistors M1, M2, and a capacitor C_RESIs connected with the sources of the transistors M7, M8, and a capacitor C_RESThe floating power supply starts discharging, and the amplifier starts operating by supplying a bias current to the amplifier.

Further, the amplifier is operative to amplify the differential input signal and to provide a signal at an output V of the amplifier_ON，V_OPObtaining a differential output voltage, under the action of differential input signals, the transistors M1, M2, M3, M4, M5, M6, M7 and M8 all work in weak inversion region, and the node V is connected with the node V_S-Is lowered, node V_S+The potential of (2) rises.

Furthermore, the amplifier comprises two working states of resetting and amplifying, when phi reset is high level and phi amp is low level, the amplifier is in the resetting state, when phi reset is low level and phi amp is high level, the amplifier is in the amplifying state.

The beneficial effect of this patent does:

the patent introduces an energy storage capacitor C in the amplifier structure_RESThe floating power supply provides bias current for the amplifier, so that the amplifier can normally perform amplification operation. And in the amplification process, the energy storage capacitor C_RESThe overdrive voltage of the input transistor is reduced, and the high energy efficiency of the amplifier is improved. Meanwhile, the amplifier also adopts a structure based on an inverter, so that current multiplexing is realized, and the energy efficiency of the amplifier is also improved. Therefore, the design method has a wide application prospect in the design of the comparator with low power consumption and high energy efficiency, particularly the design of a full dynamic comparator.

Drawings

In order to more clearly illustrate the embodiments of the present patent or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present patent, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic diagram of an energy efficient amplifier circuit.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present patent clearer, the technical solutions in the embodiments of the present patent will be clearly and completely described below with reference to the drawings in the embodiments of the present patent, and it is obvious that the described embodiments are some embodiments of the present patent, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the scope of protection of this patent.

Example 1

The embodiment discloses an energy-efficient amplifier as shown in fig. 1, and the specific circuit structure is as follows: the transistor M1, M2, M3, M4, M5, M6, M7, M8, switch S1, S2 and capacitor C_RES，C_XAnd (4) forming.

In this embodiment, the sources of the transistors M1 and M2 are connected to the capacitor C via the switch_RESThe drains of the transistors M1, M2 are connected to the sources of the transistors M3, M4, respectively.

The gates of the transistors M3, M4 in this embodiment are connected to the bias voltage V_BPThe drains of the transistors M3 and M4 are connected with the drains of the transistors M5 and M6 and the capacitor C respectively_XAre connected with each other and are respectively used as the output end V of the amplifier_ON，V_OP。

This embodiment combines two capacitors C_XThe upper plate of the capacitor is connected with a common mode voltage Vcm through switches S1 and S2, and the capacitor C_XThe lower plate of (a) is connected to ground potential.

The gates of the transistors M5, M6 of this embodiment are connected to a bias voltage V_BNAnd the sources are connected with the drains of the transistors M7, M8. The sources of the transistors M7 and M8 are connected and connected to the capacitor C through the switch_RESThe lower plate of (2).

In this embodiment, the gates of the transistors M1 and M7 are connected as the input V of the amplifier_IPThe gates of the transistors M2, M8 are connected as the input V of the amplifier_IN。

In the embodiment, an energy storage capacitor C is introduced into the amplifier structure_RESThe floating power supply provides bias current for the amplifier, so that the amplifier can normally perform amplification operation.

In the amplification process of the embodiment, the energy storage capacitor C_RESThe overdrive voltage of the input transistor is reduced, and the high energy efficiency of the amplifier is improved.

Example 2

In a specific application, the present embodiment provides two operating states of an energy-efficient amplifier, and the principle is described in this way, specifically as follows: the amplifier has two working modes of reset and amplification:

in this embodiment, when Φ reset is at a high level and Φ amp is at a low level, the amplifier is in a reset state, and when Φ reset is at a low level and Φ amp is at a high level, the amplifier is in an amplification state.

In this embodiment, when φ reset is high and φ amp is low, the amplifier is in a reset state. Capacitor C_RESThe upper electrode plate of the capacitor is connected with a power supply potential, and the capacitor C_RESThe upper plate potential is precharged to the power supply potential, the capacitor C_RESThe lower plate of which is connected to ground potential. And the switches S1, S2 are turned on, the output terminal V of the amplifier is turned on_ON，V_OPAnd a capacitor C_XIs reset to a common mode level V_cm。

In this embodiment, when φ reset is low and φ amp is high, the amplifier is in an amplifying state. Capacitor C_RESIs connected to the sources of transistors M1, M2, and a capacitor C_RESIs connected to the sources of the transistors M7, M8, and thus the capacitor C_RESStarting discharging as floating power supply, providing bias current for the amplifier, starting to work, amplifying differential input signal, and outputting V at output end of amplifier_ON，V_OPA differential output voltage is obtained.

Under the action of differential input signals, the transistors M1-M8 work in a weak inversion region, and a node V_S-Is lowered, node V_S+At a potential ofThe rise results in that the overdrive voltages of the transistors M1, M3, M5 and M7 are all reduced, the power consumption of the amplifier is reduced, and the energy efficiency is improved.

The amplifier of the embodiment is also based on an amplifier structure of an inverter, current multiplexing is realized, and the energy efficiency of the amplifier is improved.

In summary, the patent uses an energy storage capacitor C_RESThe floating power supply provides bias current for the amplifier, so that the amplifier normally performs amplification operation. And during amplification due to the capacitance C_RESThe over-drive voltage of the input transistor is reduced, the high energy efficiency of the amplifier is realized, meanwhile, the current multiplexing is realized based on the amplifier structure of the inverter, and the energy efficiency of the amplifier is also improved. The patent has a wider application prospect in the design of a comparator with low power consumption and high energy efficiency, particularly the design of a full dynamic comparator.

The above examples are only intended to illustrate the technical solution of the present patent, but not to limit it; although the present patent is described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the spirit and scope of the technical solutions of the embodiments of the present patent.

Claims

1. The high-energy-efficiency amplifier is characterized by comprising more than one transistor, more than one switch and more than one capacitor which are integrated in the same circuit, wherein the transistor, the switch and the capacitor are connected to form an output end V of the amplifier_ONAnd V_OPAnd an input terminal V_IPAnd V_IN(ii) a At the same time, the user can select the desired position,

Amplifying the differential input signal when the amplifier is in an amplifying stateThe output end V of the amplifier_ONAnd V_OPObtaining a differential output voltage, under the action of a differential input signal, a node V_S-Is lowered, node V_S+The potential of (2) rises.

2. The power efficient amplifier of claim 1, wherein the transistors comprise M1, M2, M3, M4, M5, M6, M7, and M8; the switch comprises S1 and S2; the capacitor comprises C_RESAnd C_X。

3. An energy efficient amplifier as claimed in claim 2, characterized in that the sources of the transistors M1, M2 are connected to a capacitor C via a switch_RESThe drains of the transistors M1, M2 are connected to the sources of the transistors M3, M4, respectively.

4. An energy efficient amplifier as claimed in claim 3, characterized in that the gates of the transistors M3, M4 are connected in parallel to a bias voltage V_BPThe drains of the transistors M3 and M4, the drains of the transistors M5 and M6, and the capacitor C_XAre connected to form the output end V of the amplifier_ONAnd V_OP。

5. An energy efficient amplifier as claimed in claim 2, characterized in that the capacitor C is arranged to_XThe upper pole plate of the switch is connected with a common mode voltage V through switches S1 and S2_cmConnected with its lower plate connected to ground potential.

6. An energy efficient amplifier as claimed in claim 2, wherein the gates of the transistors M5, M6 are connected in parallel to a bias voltage V_BNAnd the sources thereof are connected to the drains of the transistors M7, M8.

7. The power efficient amplifier of claim 6, wherein the sources of the transistors M7, M8 are connected to a capacitor C through a switch_RESAnd the gates of the transistors M1, M7 are connected as the input V of the amplifier_IPThe gates of the transistors M2, M8 are connected as the input V of the amplifier_IN。

8. An energy efficient amplifier as claimed in claim 1, wherein the capacitor C is present in a reset state of the amplifier_RESThe upper electrode plate of the capacitor is connected with a power supply potential, and the capacitor C_RESThe upper plate potential is precharged to the power supply potential, the capacitor C_RESIs connected to ground potential and the switches S1, S2 are turned on, the output V of the amplifier is connected to ground potential_ON，V_OPAnd a capacitor C_XIs reset to a common mode level V_cm。

9. An energy efficient amplifier as claimed in claim 1, wherein the capacitor C is arranged to be in the amplifying state_RESIs connected to the sources of transistors M1, M2, and a capacitor C_RESIs connected with the sources of the transistors M7, M8, and a capacitor C_RESThe floating power supply starts discharging, and the amplifier starts operating by supplying a bias current to the amplifier.

10. An energy efficient amplifier as claimed in claim 9, wherein the amplifier is operable to amplify a differential input signal and provide a signal at the output terminal V of the amplifier_ON，V_OPObtaining a differential output voltage, under the action of differential input signals, the transistors M1, M2, M3, M4, M5, M6, M7 and M8 all work in weak inversion region, and the node V is connected with the node V_S-Is lowered, node V_S+The potential of (2) rises.