CN216016871U - Optical module - Google Patents
Optical module Download PDFInfo
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- CN216016871U CN216016871U CN202122338995.0U CN202122338995U CN216016871U CN 216016871 U CN216016871 U CN 216016871U CN 202122338995 U CN202122338995 U CN 202122338995U CN 216016871 U CN216016871 U CN 216016871U
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Abstract
The optical module provided by the application comprises a golden finger, a reference level output device, a logic chip and a laser driving chip, wherein the golden finger is electrically connected with an input end of the logic chip, the reference level output device is electrically connected with another input end of the logic chip, a reset pin of the laser driving chip is electrically connected with an output end of the logic chip, a TX _ Disable signal sent by an upper computer is transmitted to the logic chip through the golden finger, the logic chip generates a corresponding control signal according to the level state of the reference level and the level state of the TX _ Disable signal, then the control signal is transmitted to the reset pin of the laser driving chip, the reset pin of the laser driving chip makes the response of resetting or normal work according to the level state of the control signal, when the reset pin of the laser driving chip is reset in response to the control signal, the laser is closed, and the hardware TX Disable function of the laser driving chip is realized.
Description
Technical Field
The application relates to the technical field of optical fiber communication, in particular to an optical module.
Background
An optical module realizes the function of photoelectric conversion in the technical field of optical communication, and is one of key devices in optical communication equipment, the optical module includes a laser, an upper computer sends a TX Disable signal to control the on or off of the laser, and specifically includes a hardware TX Disable function and a software TX Disable function, the hardware TX Disable function refers to: transmitting a TX Disable signal to a laser driving chip through the connection of a golden finger TX Disable signal pin and a laser driving chip TX Disable signal pin; the software TX Disable function refers to: the TX Disable signal sent by the upper computer is transmitted to the laser driving chip through the singlechip, but the software TX Disable functional time sequence is too long, and the requirement of a protocol on the time sequence duration is not met.
Some laser driving chips do not have a TX Disable signal pin, so that the laser cannot be turned on or off through a hardware TX Disable function, and a software TX Disable function cannot meet the requirement of a protocol on the time sequence duration.
SUMMERY OF THE UTILITY MODEL
The embodiment of the application provides an optical module to realize hardware TX Disable control of some lasers.
The optical module provided by the embodiment of the application comprises:
a circuit board;
the golden finger is arranged on the surface of the circuit board and used for inputting a TX _ Disable signal to the logic chip;
the reference level output device is electrically connected with the logic chip and is used for inputting a reference level to the logic chip;
the logic chip is arranged on the surface of the circuit board, is electrically connected with the golden finger and the reference level output device, and comprises a first input end and a second input end, wherein the first input end receives the reference level, the second input end receives the TX _ Disable signal, performs logic operation on the reference level and the TX _ Disable signal, and then generates a control signal;
and the laser driving chip is provided with a reset pin, and the logic chip is electrically connected with the reset pin and used for receiving the control signal output by the logic chip.
The optical module provided by the application comprises a golden finger, a reference level output device, a logic chip and a laser driving chip, wherein the golden finger is electrically connected with an input end of the logic chip, the reference level output device is electrically connected with another input end of the logic chip and is used for outputting a reference level, a reset pin of the laser driving chip is electrically connected with an output end of the logic chip, a TX _ Disable signal sent by an upper computer is transmitted to the logic chip through the golden finger, the logic chip generates a corresponding control signal according to the level state of the reference level and the level state of the TX _ Disable signal and then transmits the control signal to the reset pin of the laser driving chip, the reset pin of the laser driving chip makes a reset or normal work response according to the level state of the control signal, when the reset pin resets in response to the control signal, the laser driving chip is in a reset state, the output of the laser driving chip is closed, and stopping outputting the driving current to the laser, and further closing the laser to realize the hardware TX Disable function of the laser driving chip, particularly the hardware TX Disable function of the laser driving chip without a TX Disable signal pin.
The hardware TX Disable function is realized through the cooperation of the reset pin of the laser driving chip and the logic circuit, and the scheme is simple and flexible.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic diagram of a connection relationship of an optical communication terminal;
FIG. 2 is a schematic diagram of an optical network unit;
fig. 3 is a schematic structural diagram of an optical module according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of an exploded structure of an optical module according to an embodiment of the present application;
fig. 5 is a connection schematic diagram of structures of an optical module provided in the embodiment of the present application;
fig. 6 is a connection schematic diagram of structures of an optical module according to an embodiment of the present application.
Detailed Description
In order to make those skilled in the art better understand the technical solutions in the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
In the optical communication technology, light is used to carry information to be transmitted, and an optical signal carrying the information is transmitted to information processing equipment such as a computer through information transmission equipment such as an optical fiber or an optical waveguide, so that the transmission of the information is completed. Because the optical signal has the passive transmission characteristic when being transmitted through the optical fiber or the optical waveguide, the information transmission with low cost and low loss can be realized. Further, since a signal transmitted by an information transmission device such as an optical fiber or an optical waveguide is an optical signal and a signal that can be recognized and processed by an information processing device such as a computer is an electrical signal, it is necessary to perform interconversion between the electrical signal and the optical signal in order to establish an information connection between the information transmission device such as an optical fiber or an optical waveguide and the information processing device such as a computer.
The optical module realizes the function of interconversion between the optical signal and the electrical signal in the technical field of optical fiber communication. The optical module comprises an optical port and an electrical port, the optical module realizes optical communication with information transmission equipment such as optical fibers or optical waveguides and the like through the optical port, realizes electrical connection with an optical network terminal (such as an optical modem) through the electrical port, and the electrical connection is mainly used for realizing power supply, I2C signal transmission, data signal transmission, grounding and the like; the optical network terminal transmits the electric signal to the computer and other information processing equipment through a network cable or a wireless fidelity (Wi-Fi).
Fig. 1 is a diagram of optical communication system connections according to some embodiments. As shown in fig. 1, the optical communication system mainly includes a remote server 1000, a local information processing device 2000, an optical network terminal 100, an optical module 200, an optical fiber 101, and a network cable 103;
one end of the optical fiber 101 is connected to the remote server 1000, and the other end is connected to the optical network terminal 100 through the optical module 200. The optical fiber itself can support long-distance signal transmission, for example, signal transmission of several kilometers (6 kilometers to 8 kilometers), on the basis of which if a repeater is used, ultra-long-distance transmission can be theoretically achieved. Therefore, in a typical optical communication system, the distance between the remote server 1000 and the optical network terminal 100 may be several kilometers, tens of kilometers, or hundreds of kilometers.
One end of the network cable 103 is connected to the local information processing device 2000, and the other end is connected to the optical network terminal 100. The local information processing apparatus 2000 may be any one or several of the following apparatuses: router, switch, computer, cell-phone, panel computer, TV set etc..
The physical distance between the remote server 1000 and the optical network terminal 100 is greater than the physical distance between the local information processing apparatus 2000 and the optical network terminal 100. The connection between the local information processing device 2000 and the remote server 1000 is completed by the optical fiber 101 and the network cable 103; and the connection between the optical fiber 101 and the network cable 103 is completed by the optical module 200 and the optical network terminal 100.
The optical module 200 includes an optical port and an electrical port. The optical port is configured to connect with the optical fiber 101, so that the optical module 200 establishes a bidirectional optical signal connection with the optical fiber 101; the electrical port is configured to be accessed into the optical network terminal 100, so that the optical module 200 establishes a bidirectional electrical signal connection with the optical network terminal 100. The optical module 200 converts an optical signal and an electrical signal to each other, so that a connection is established between the optical fiber 101 and the optical network terminal 100. For example, an optical signal from the optical fiber 101 is converted into an electrical signal by the optical module 200 and then input to the optical network terminal 100, and an electrical signal from the optical network terminal 100 is converted into an optical signal by the optical module 200 and input to the optical fiber 101.
The optical network terminal 100 includes a housing (housing) having a substantially rectangular parallelepiped shape, and an optical module interface 102 and a network cable interface 104 provided on the housing. The optical module interface 102 is configured to access the optical module 200, so that the optical network terminal 100 establishes a bidirectional electrical signal connection with the optical module 200; the network cable interface 104 is configured to access the network cable 103 such that the optical network terminal 100 establishes a bi-directional electrical signal connection with the network cable 103. The optical module 200 is connected to the network cable 103 via the optical network terminal 100. For example, the optical network terminal 100 transmits an electrical signal from the optical module 200 to the network cable 103, and transmits a signal from the network cable 103 to the optical module 200, so that the optical network terminal 100 can monitor the operation of the optical module 200 as an upper computer of the optical module 200. The upper computer of the Optical module 200 may include an Optical Line Terminal (OLT) and the like in addition to the Optical network Terminal 100.
The remote server 1000 establishes a bidirectional signal transmission channel with the local information processing device 2000 through the optical fiber 101, the optical module 200, the optical network terminal 100, and the network cable 103.
Fig. 2 is a structure diagram of an optical network terminal according to some embodiments, and fig. 2 only shows the structure of the optical module 200 of the optical network terminal 100 in order to clearly show the connection relationship between the optical module 200 and the optical network terminal 100. As shown in fig. 2, the optical network terminal 100 further includes a PCB circuit board 105 disposed in the housing, a cage 106 disposed on a surface of the PCB circuit board 105, and an electrical connector disposed inside the cage 106. The electrical connector is configured to access an electrical port of the optical module 200; the heat sink 107 has a projection such as a fin that increases a heat radiation area.
The optical module 200 is inserted into a cage 106 of the optical network terminal 100, the cage 106 holds the optical module 200, and heat generated by the optical module 200 is conducted to the cage 106 and then diffused by a heat sink 107. After the optical module 200 is inserted into the cage 106, an electrical port of the optical module 200 is connected to an electrical connector inside the cage 106, and thus the optical module 200 establishes a bidirectional electrical signal connection with the optical network terminal 100. Further, the optical port of the optical module 200 is connected to the optical fiber 101, and the optical module 200 establishes bidirectional electrical signal connection with the optical fiber 101.
Fig. 3 is a diagram of an optical module provided according to some embodiments, and fig. 4 is an exploded structural view of an optical module according to some embodiments. As shown in fig. 3 and 4, the optical module 200 includes a housing, a circuit board 105 disposed in the housing, and an optical transceiver;
the shell comprises an upper shell 201 and a lower shell 202, wherein the upper shell 201 is covered on the lower shell 202 to form the shell with two openings 204 and 205; the outer contour of the housing generally appears square.
In some embodiments, the lower housing 202 includes a bottom plate and two lower side plates disposed at both sides of the bottom plate and perpendicular to the bottom plate; the upper housing 201 includes a cover plate, and two upper side plates disposed on two sides of the cover plate and perpendicular to the cover plate, and is combined with the two side plates by two side walls to cover the upper housing 201 on the lower housing 202.
The direction of the connecting line of the two openings 204 and 205 may be the same as the length direction of the optical module 200, or may not be the same as the length direction of the optical module 200. For example, the opening 204 is located at an end (left end in fig. 3) of the optical module 200, and the opening 205 is also located at an end (right end in fig. 3) of the optical module 200. Alternatively, the opening 204 is located at an end of the optical module 200, and the opening 205 is located at a side of the optical module 200. Wherein, the opening 204 is an electrical port, and the gold finger of the circuit board 105 extends out of the opening 204 and is inserted into an upper computer (such as the optical network terminal 100); the opening 205 is an optical port configured to receive the external optical fiber 101, so that the optical fiber 101 is connected to an optical transceiver inside the optical module 200.
The upper shell 201 and the lower shell 202 are combined in an assembly mode, so that devices such as the circuit board 105 and the optical transceiver device can be conveniently installed in the shells, and the upper shell 201 and the lower shell 202 can form packaging protection for the devices. In addition, when the devices such as the circuit board 105 and the like are assembled, the positioning components, the heat dissipation components and the electromagnetic shielding components of the devices are convenient to arrange, and the automatic implementation production is facilitated.
In some embodiments, the upper housing 201 and the lower housing 202 are generally made of metal materials, which is beneficial to achieve electromagnetic shielding and heat dissipation.
In some embodiments, the optical module 200 further includes an unlocking component 203 located on an outer wall of a housing thereof, and the unlocking component 203 is configured to realize a fixed connection between the optical module 200 and an upper computer or release the fixed connection between the optical module 200 and the upper computer.
Illustratively, the unlocking members 203 are located on the outer walls of the two lower side plates of the lower housing 202, and include snap-fit members that mate with a cage of an upper computer (e.g., the cage 106 of the optical network terminal 100). When the optical module 200 is inserted into the cage of the upper computer, the optical module 200 is fixed in the cage of the upper computer by the engaging member of the unlocking member 203; when the unlocking member 203 is pulled, the engaging member of the unlocking member 203 moves along with the unlocking member, and the connection relationship between the engaging member and the upper computer is changed, so that the engagement relationship between the optical module 200 and the upper computer is released, and the optical module 200 can be drawn out from the cage of the upper computer.
The circuit board 105 includes circuit traces, electronic components (such as capacitors, resistors, triodes, and MOS transistors), and chips (such as MCU, laser driver chip, amplitude limiting amplifier chip, clock data recovery CDR, power management chip, and data processing chip DSP).
The circuit board 105 connects the above devices in the optical module 200 together according to circuit design through circuit routing to implement functions of power supply, electrical signal transmission, grounding, and the like.
The circuit board 105 is generally a rigid circuit board, which can also perform a bearing function due to its relatively rigid material, for example, the rigid circuit board can stably bear a chip; the hard circuit board can also be inserted into an electric connector in the cage of the upper computer, and in some embodiments disclosed in the application, a metal pin/golden finger is formed on the surface of the tail end of one side of the hard circuit board and is used for being connected with the electric connector; these are not easily implemented with flexible circuit boards.
Flexible circuit boards are also used in some optical modules; the flexible circuit board is generally used in combination with the rigid circuit board, and for example, the rigid circuit board may be connected to the optical transceiver device to supplement the rigid circuit board.
The upper computer sends a TX Disable signal to control the on or off of the laser, and specifically comprises a hardware TX Disable function and a software TX Disable function, wherein the hardware TX Disable function refers to: transmitting a TX Disable signal to a laser driving chip through the connection of a golden finger TX Disable signal pin and a laser driving chip TX Disable signal pin; the software TX Disable function refers to: the TX Disable signal sent by the upper computer is transmitted to the laser driving chip through the singlechip, but the software TX Disable functional time sequence is too long, and the requirement of a protocol on the time sequence duration is not met.
In some embodiments, the golden finger has a TX _ Disable PIN, the PIN3 of the golden finger is a TX _ Disable PIN, the upper computer transmits a Disable command signal or an Enable command signal to the TX _ Disable PIN of the golden finger, the laser driver chip also has a TX _ Disable PIN, the TX _ Disable PIN of the golden finger is electrically connected to the TX _ Disable PIN of the laser driver chip, the Disable command signal or the Enable command signal sent by the upper computer can be transmitted to the laser driver chip, when the Disable command signal sent by the upper computer is transmitted to the TX _ Disable PIN of the laser driver chip through the TX _ Disable PIN of the golden finger, the laser driver chip stops providing the driving current to the laser to turn off the laser, the laser stops emitting light, when the Enable command signal sent by the upper computer is transmitted to the TX _ Disable PIN of the laser driver chip through the TX _ Disable PIN of the golden finger, the laser driver chip can Enable the laser driver chip to turn on the driving current, the laser emits light.
The upper computer sends a Disable instruction signal or an Enable instruction signal to the laser driving chip through a gold finger according to the control requirement of the upper computer, and the Disable instruction signal or the Enable instruction signal respectively controls the laser to be turned off and on, so that the laser is controlled to be in a non-light emitting state or a light emitting state.
Specifically, when the upper computer monitors that the power supply is unstable, the upper computer needs to be restarted, power is turned on or off, and the like, an instruction signal for turning off the laser needs to be sent out through the golden finger end.
When the Disable instruction signal sent by the upper computer is at a high level, namely the Disable instruction signal transmitted to the laser driving chip through the golden finger is at the high level, the laser driving chip responds to stop providing the driving current for the laser, and then the laser is turned off, and when the Disable instruction signal sent by the upper computer is at a low level, namely the Disable instruction signal transmitted to the laser driving chip through the golden finger is at the low level, the laser driving chip responds to provide the driving current for the laser, and then the laser is turned on.
The PIN3 PIN of the gold finger is the TX _ Disable PIN through which the laser is turned on and off, which is also a requirement in the SFF-8431 protocol.
In some embodiments, some laser driving chips do not have TX Disable signal pins, so that the laser cannot be controlled to be turned on or off through the hardware TX Disable function, and the software TX Disable function cannot meet the requirement of the protocol on the timing duration.
Aiming at the laser driving chip without the TX Disable signal pin, the hardware TX Disable function is realized through the cooperation of the reset pin of the laser driving chip and the logic circuit, and the scheme is simple and flexible.
In order to make the objects, technical solutions and advantages of the embodiments of the present application more apparent, the embodiments of the present application will be described in detail with reference to the accompanying drawings and specific embodiments.
In the embodiment of the application, the optical module comprises a golden finger, a logic chip, a resistor and a laser driving chip, the golden finger comprises a TX Disable signal pin, the golden finger is electrically connected with an input end of the logic chip, the resistor is electrically connected with an input end of the logic chip, and the laser driving chip is electrically connected with an output end of the logic chip.
After the optical module is powered on and started, the optical module is in a TX Disable state (namely a laser non-light-emitting state) by default, and the laser does not emit light.
The golden finger is provided with a TX Disable signal pin, receives a TX Disable signal from the upper computer, outputs the TX Disable signal with high level or the TX Disable signal with low level, and transmits the TX Disable signal to the logic chip through the golden finger; the TX Disable signal needs to be pulled up according to the hardware protocol requirement, so a pull-up resistor R1 is further provided in the embodiment of the present application, specifically, a branch is formed between the TX Disable signal pin of the gold finger and the logic chip, a pull-up resistor R1 is provided between the branch and the power supply, and the pull-up resistor R1 can pull up the TX Disable signal.
As shown in fig. 5, the logic chip in the embodiment of the present application may include two input ends and one output end, where the two input ends are respectively electrically connected to the reference level output device and the gold finger, where the reference level output device is configured to input a reference level to the logic chip, and the TX Disable signal from the upper computer is input to the logic chip through the gold finger. It is understood that the logic chip in the embodiments of the present application may include two inputs and one output, which are non-limiting embodiments, and the logic chip may include one input, one output, or include one input, two outputs, and the like, and then the logic chip performs a logic operation on a signal from the input to obtain a control signal, and outputs the control signal through the output, which all belong to the protection scope of the embodiments of the present application.
As shown in fig. 6, the reference level output apparatus according to the embodiment of the present application may include a resistor R2, the resistor R2 may be configured as a pull-up resistor or a pull-down resistor according to the type of the logic chip, the pull-up resistor is a resistor connected to the power supply voltage VCC, the pull-down resistor is a resistor connected to ground, the pull-up resistor may process a signal into a high-level signal of 3.3V, and the pull-down resistor may process a signal into a low-level signal of 0V; therefore, when the resistor R2 is a pull-up resistor, the reference level output device includes a power terminal and a pull-up resistor, and when the resistor R2 is a pull-down resistor, the reference level output device includes a ground terminal and a pull-down resistor.
The reference level output device of the present application may also be in other forms, and is not limited to the resistor R2.
The logic chip comprises a first input end, a second input end and an output end, the first input end is electrically connected with a golden finger TX Disable signal pin, the second input end is electrically connected with a resistor, the output end is electrically connected with the laser driving chip, the logic chip can generate a corresponding control signal according to a received TX Disable signal transmitted by the golden finger and the level state of the resistor, and the control signal is transmitted to a reset pin of the laser driving chip through the output end, so that the laser driving chip responds to whether the laser driving chip is reset or not, and then the laser is controlled to be turned on or turned off.
The laser driving chip comprises a Reset pin, when the Reset pin is Reset, the effective level of the Reset pin is high level, when the instruction quotation mark received by the Reset pin is in a high level state, the laser driving chip is in a Reset mode, and the laser does not emit light; when the instruction quotation mark received at the reset pin is in a low level state, the laser driving chip is in a normal mode, and the laser emits light.
When the laser driving chip is in the reset mode, the output of the laser driving chip is turned off, and then the laser driving chip stops outputting the driving current to the laser, so that the laser cannot emit light, and the function of turning off the laser is realized.
When the reset pin is ResetL, the effective level of the reset pin is low level, when the instruction quotation mark received by the reset pin is in a high level state, the laser driving chip is in a normal mode, and the laser emits light; when the instruction quotation mark received at the reset pin is in a low level state, the laser driving chip is in a reset mode, and the laser does not emit light.
As non-limiting examples, the logic chip in the present application may be a nand gate logic chip, a nor gate logic chip, an xor gate logic chip, an xnor gate logic chip, and the like.
When the logic chip is configured as a nand gate logic chip, the output is low level when both the first input terminal and the second input terminal are high level, and the output is high level if at least one of the first input terminal and the second input terminal is low level.
When the logic chip is configured as a nor gate logic chip, the output is at a high level when both the first input terminal and the second input terminal are at a low level, and the output is at a low level if at least one of the first input terminal and the second input terminal is at a high level.
When the logic chip is configured as an exclusive-or gate logic chip, if the first input terminal and the second input terminal are in different level states, a high level is output, and if the first input terminal and the second input terminal are in the same level states, a low level is output.
When the logic chip is configured as an exclusive-nor logic chip, if the first input terminal and the second input terminal are in the same level state, a high level is output, and if the first input terminal and the second input terminal are in the different level states, a low level is output.
It should be understood that the present application is not limited to specific types of logic chips, and any logic chip that can implement the TX _ Disable signal as an input signal and output a control signal according to the level state of the TX _ Disable signal is within the scope of the embodiments of the present application.
In some embodiments, when the logic chip is a nand gate logic chip, the resistor R2 is a pull-up resistor, the level output by the resistor R2 is maintained at a high level state, if the TX _ Disable signal transmitted by the gold finger is in a high level state, the logic chip generates a low level control signal, at this time, if the Reset pin is a Reset pin, the laser driver chip is in a normal operating mode, the laser is turned on, and if the Reset pin is a ResetL pin, the laser driver chip is in a Reset mode, and the laser is turned off. If the TX _ Disable signal transmitted by the golden finger is in a low level state, the logic chip generates a control signal of a high level, at this time, if the Reset pin is a Reset pin, the laser driving chip is in a Reset mode, the laser is turned off, and if the Reset pin is a Reset L pin, the laser driving chip is in a normal working mode, and the laser is turned on.
In some embodiments, when the logic chip is a nor logic chip, the resistor R2 is a pull-down resistor, the level output by the resistor R2 is maintained at a low level state, if the TX _ Disable signal transmitted by the gold finger is at a high level state, the logic chip generates a low level control signal, at this time, if the Reset pin is a Reset pin, the laser driver chip is in a normal operating mode, the laser is turned on, and if the Reset pin is a ResetL pin, the laser driver chip is in a Reset mode, and the laser is turned off. If the TX _ Disable signal transmitted by the golden finger is in a low level state, the logic chip generates a control signal of a high level, at this time, if the Reset pin is a Reset pin, the laser driving chip is in a Reset mode, the laser is turned off, and if the Reset pin is a Reset L pin, the laser driving chip is in a normal working mode, and the laser is turned on.
In some embodiments, when the logic chip is an exclusive or gate logic chip, the resistor R2 may be a pull-up resistor or a pull-down resistor.
When the logic chip is an exclusive-or gate logic chip and the resistor R2 is a pull-up resistor, the level output by the resistor R2 is maintained at a high level state, if a TX _ Disable signal transmitted by a gold finger is in a high level state, the logic chip generates a low level control signal, at this time, if a Reset pin is a Reset pin, the laser driving chip is in a normal working mode, the laser is turned on, and if the Reset pin is a ResetL pin, the laser driving chip is in a Reset mode, and the laser is turned off. If the TX _ Disable signal transmitted by the golden finger is in a low level state, the logic chip generates a control signal of a high level, at this time, if the Reset pin is a Reset pin, the laser driving chip is in a Reset mode, the laser is turned off, and if the Reset pin is a Reset L pin, the laser driving chip is in a normal working mode, and the laser is turned on.
When the logic chip is an exclusive-or gate logic chip and the resistor R2 is a pull-down resistor, the level output by the resistor R2 is maintained at a low level state, if a TX _ Disable signal transmitted by a gold finger is at a high level state, the logic chip generates a high level control signal, at this time, if a Reset pin is a Reset pin, the laser driving chip is in a Reset mode, the laser is turned off, and if the Reset pin is a ResetL pin, the laser driving chip is in a normal operating mode, and the laser is turned on. If the TX _ Disable signal transmitted by the golden finger is in a low level state, the logic chip generates a control signal of a low level, at this time, if the Reset pin is a Reset pin, the laser driving chip is in a normal working mode, the laser is started, and if the Reset pin is a Reset pin, the laser driving chip is in a Reset mode, and the laser is stopped.
In some embodiments, when the logic chip is an exclusive nor logic chip, the resistor R2 may be a pull-up resistor or a pull-down resistor.
When the logic chip is an exclusive-nor logic chip and the resistor R2 is a pull-up resistor, the level output by the resistor R2 is maintained at a high level state, if a TX _ Disable signal transmitted by a gold finger is in a high level state, the logic chip generates a high level control signal, at this time, if a Reset pin is a Reset pin, the laser driving chip is in a Reset mode, the laser is turned off, and if the Reset pin is a ResetL pin, the laser driving chip is in a normal operating mode, and the laser is turned on. If the TX _ Disable signal transmitted by the golden finger is in a low level state, the logic chip generates a control signal of a low level, at this time, if the Reset pin is a Reset pin, the laser driving chip is in a normal working mode, the laser is started, and if the Reset pin is a Reset pin, the laser driving chip is in a Reset mode, and the laser is stopped.
When the logic chip is an exclusive-nor logic chip and the resistor R2 is a pull-down resistor, the level output by the resistor R2 is maintained at a low level state, if a TX _ Disable signal transmitted by a gold finger is at a high level state, the logic chip generates a control signal at a low level, at this time, if a Reset pin is a Reset pin, the laser driving chip is in a normal working mode, the laser is turned on, and if the Reset pin is a ResetL pin, the laser driving chip is in a Reset mode, and the laser is turned off. If the TX _ Disable signal transmitted by the golden finger is in a low level state, the logic chip generates a control signal of a high level, at this time, if the Reset pin is a Reset pin, the laser driving chip is in a Reset mode, the laser is turned off, and if the Reset pin is a Reset L pin, the laser driving chip is in a normal working mode, and the laser is turned on.
Therefore, the application provides a simple and flexible optical module circuit structure, and a logic chip and a resistor R2 are added on the basis of the original circuit structure, so that the problem that when a laser driving chip has no TX Disable signal pin is solved, the hardware TX Disable function is realized; the laser driving chip has the advantages that the hardware TX Disable function is achieved through the cooperation of the reset pin of the laser driving chip and the logic circuit, and the circuit structure is simple and flexible.
The optical module provided by the application comprises a golden finger, a resistor, a logic chip and a laser driving chip, wherein the golden finger is electrically connected with an input end of the logic chip, the resistor is electrically connected with the other input end of the logic chip, a reset pin of the laser driving chip is electrically connected with an output end of the logic chip, a TX _ Disable signal sent by an upper computer is transmitted to the logic chip through the golden finger, the logic chip generates a corresponding control signal according to the level state of the resistor and the level state of the TX _ Disable signal, then the control signal is transmitted to the reset pin of the laser driving chip, the reset pin of the laser driving chip makes the response of resetting or normal work according to the level state of the control signal, when the reset pin is reset in response to the control signal, the laser driving chip is in a reset state, and the laser is further closed, so that the hardware TX Disable function of the laser driving chip is realized, and particularly the hardware TX Disable function of the laser driving chip without the TX Disable signal pin is realized.
The application provides a simple and flexible optical module circuit structure, increases logic chip and resistance R2 on original circuit structure's basis to when solving laser driver chip and not having TX Disable signal pin, realize hardware TX Disable function.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solutions of the present disclosure, not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present disclosure.
Claims (9)
1. A light module, comprising:
a circuit board;
the golden finger is arranged on the surface of the circuit board and used for inputting a TX _ Disable signal to the logic chip;
the reference level output device is electrically connected with the logic chip and is used for inputting a reference level to the logic chip;
the logic chip is arranged on the surface of the circuit board, is electrically connected with the golden finger and the reference level output device, and comprises a first input end and a second input end, wherein the first input end receives the reference level, the second input end receives the TX _ Disable signal, performs logic operation on the reference level and the TX _ Disable signal, and then generates a control signal;
and the laser driving chip is provided with a reset pin, and the logic chip is electrically connected with the reset pin and used for receiving the control signal output by the logic chip.
2. The optical module of claim 1, wherein the logic chip is configured as a nand gate logic chip, the reference level output device is set as a pull-up resistor, and the reference level is in a high state;
when the TX _ Disable signal is a high-level instruction signal, the logic chip generates a low-level control signal;
and when the TX _ Disable signal is a low-level instruction signal, the logic chip generates a high-level control signal.
3. The optical module of claim 1, wherein the logic chip is configured as a nor gate logic chip, the reference level output device comprises a pull-down resistor, and the reference level is a low state;
when the TX _ Disable signal is a high-level instruction signal, the logic chip generates a low-level control signal;
and when the TX _ Disable signal is a low-level instruction signal, the logic chip generates a high-level control signal.
4. The optical module of claim 1, wherein the logic chip is configured as an exclusive-or gate logic chip, the reference level output device comprises a pull-up resistor, and the reference level is a high state;
when the TX _ Disable signal is a high-level instruction signal, the logic chip generates a low-level control signal;
and when the TX _ Disable signal is a low-level instruction signal, the logic chip generates a high-level control signal.
5. The optical module of claim 4, wherein the logic chip is configured as an exclusive-or logic chip, the reference level output device comprises a pull-down resistor, and the reference level is a low state;
when the TX _ Disable signal is a high-level instruction signal, the logic chip generates a high-level control signal;
and when the TX _ Disable signal is a low-level instruction signal, the logic chip generates a low-level control signal.
6. The optical module of claim 1, wherein when the logic chip is configured as an exclusive-nor logic chip, the reference level output device comprises a pull-up resistor, and the reference level is in a high state;
when the TX _ Disable signal is a high-level instruction signal, the logic chip generates a high-level control signal;
and when the TX _ Disable signal is a low-level instruction signal, the logic chip generates a low-level control signal.
7. The optical module of claim 6, wherein when the logic chip is configured as an exclusive-nor logic chip, the reference level output device comprises a pull-down resistor, and the reference level is in a low state;
when the TX _ Disable signal is a high-level instruction signal, the logic chip generates a low-level control signal;
and when the TX _ Disable signal is a low-level instruction signal, the logic chip generates a high-level control signal.
8. The optical module according to claim 1, wherein when the Reset pin is a Reset pin, the laser driver chip is in a Reset state when the logic chip generates a high-level control signal, and the laser driver chip is in a working state when the logic chip generates a low-level control signal;
when the reset pin is a ResetL pin, the laser driving chip is in a working state when the logic chip generates a high level control signal, and the laser driving chip is in a reset state when the logic chip generates a low level control signal.
9. The optical module according to claim 1, wherein the gold finger is provided with a TX _ Disable signal pin, the logic chip comprises a first input end, a second input end and an output end, and the laser driving chip is provided with a reset pin;
the TX _ Disable signal pin is electrically connected with the first input end, the reference level output device is electrically connected with the second input end, and the reset pin is electrically connected with the output end.
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| CN202122338995.0U CN216016871U (en) | 2021-09-26 | 2021-09-26 | Optical module |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115664528A (en) * | 2022-12-27 | 2023-01-31 | 绍兴中科通信设备有限公司 | Optical module, system and method for realizing ultra-fast squelch function |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115664528A (en) * | 2022-12-27 | 2023-01-31 | 绍兴中科通信设备有限公司 | Optical module, system and method for realizing ultra-fast squelch function |
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