CN113300773B - Optical module - Google Patents

Optical module Download PDF

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Publication number
CN113300773B
CN113300773B CN202010113806.7A CN202010113806A CN113300773B CN 113300773 B CN113300773 B CN 113300773B CN 202010113806 A CN202010113806 A CN 202010113806A CN 113300773 B CN113300773 B CN 113300773B
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Prior art keywords
microprocessor
low
frequency signal
data
optical module
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CN202010113806.7A
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CN113300773A (en
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王力
王庆华
薛登山
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Hisense Broadband Multimedia Technology Co Ltd
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Hisense Broadband Multimedia Technology Co Ltd
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Priority to CN202210380297.3A priority Critical patent/CN114826410B/en
Priority to CN202010113806.7A priority patent/CN113300773B/en
Priority to PCT/CN2020/133865 priority patent/WO2021169463A1/en
Publication of CN113300773A publication Critical patent/CN113300773A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/40—Transceivers

Abstract

The application provides an optical module, sets up first microprocessor and the second microprocessor of electricity connection on the circuit board, is connected with the golden finger electricity on the circuit board through setting up first microprocessor to set up second microprocessor and be used for realizing the sending and receiving work of low frequency signal. Therefore, when the data related to the low-frequency signal is sent, the first microprocessor sends the data to the second microprocessor, and then the second microprocessor sends the data related to the low-frequency signal out by controlling the light emitting circuit in the optical module; when receiving the data related to the low-frequency signal, the second microprocessor receives the low-frequency signal analyzed by the light receiving circuit, and after receiving the low-frequency signal, the second microprocessor transfers the received low-frequency signal to the first microprocessor for the upper computer to read. Therefore, the optical module can be quickly polled by the upper computer, and the message receiving and sending process in the optical module is not influenced.

Description

Optical module
Technical Field
The application relates to the technical field of optical communication, in particular to an optical module.
Background
In the access network communication system, mutual optical connection is established between an optical line terminal and an optical network unit to realize data communication. Specifically, the optical line terminal is provided with a first optical module, the optical network unit is provided with a second optical module, and optical connection is established between the first optical module and the second optical module; the optical line terminal sends an optical signal to the second optical module through the first optical module to realize that the optical line terminal sends data to the optical network unit; the optical line terminal receives the optical signal from the second optical module through the first optical module, so that the optical line terminal receives the data from the optical network unit.
In the above communication system, the optical line terminal and the optical network unit are upper computers of the optical module. In order to realize that the optical line terminal and/or the optical network unit are positioned in environments which are inconvenient for manual operation, such as high mountains, forests, water bodies and the like, the optical module is difficult to operate by operating an upper computer or using the upper computer. In view of the above, a technical solution for message transmission of a color light module based on a message channel function is proposed at present, so that the optical module can implement remote control.
However, in the message passing technology based on the color light optical module, in the process of sending or receiving a single message by the sending end module, if the upper computer performs an I2C access operation on the optical module at this time, since the I2C access right is the highest and the MCU ((MicroControllerUnit, microprocessor) in the optical module is a single-thread processor, the sending or receiving of the message is interrupted, so that a failure occurs.
Disclosure of Invention
The embodiment of the application provides an optical module, which aims to solve the problem that in the existing color light optical module message transmission technology, polling access of an upper computer to an optical module easily causes optical module message transmission failure, so that the optical module system message transmission efficiency is affected.
An optical module according to an embodiment of the present application includes:
a circuit board;
the first microprocessor is arranged on the circuit board, is electrically connected with the golden finger arranged on the circuit board and is used for sending data related to the low-frequency signal to the second microprocessor;
and the second microprocessor is arranged on the circuit board, is electrically connected with the first microprocessor, is used for sending out the data related to the low-frequency signal through the light emitting circuit, is used for receiving the low-frequency signal analyzed by the light receiving circuit and then forwards the low-frequency signal to the first microprocessor.
As can be seen from the above embodiments, in the optical module provided in the embodiments of the present application, the circuit board is provided with the first microprocessor and the second microprocessor which are electrically connected, the first microprocessor is electrically connected to the gold finger on the circuit board, and the second microprocessor is configured to implement sending and receiving of the low-frequency signal. Therefore, when the data related to the low-frequency signal is sent, the first microprocessor sends the data to the second microprocessor, and then the second microprocessor sends the data related to the low-frequency signal out by controlling the light emitting circuit in the optical module; when receiving the data related to the low-frequency signal, the second microprocessor receives the low-frequency signal analyzed by the light receiving circuit, and after receiving the low-frequency signal, the second microprocessor transfers the received low-frequency signal to the first microprocessor for the upper computer to read. Because the two microprocessors are responsible for different working contents, the upper computer can quickly poll the optical module and does not influence the message receiving and sending process in the optical module, so that the problem that the upper computer damages the message transmission of the optical module is avoided while the upper computer can timely acquire and update the status bytes sent by the optical module is ensured, and the message transmission rate of the system is integrally improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic diagram of a connection relationship of an optical communication terminal;
fig. 2 is a schematic structural diagram of an optical network terminal;
fig. 3 is a schematic structural diagram of an optical module according to an embodiment of the present invention;
FIG. 4 is an exploded view of an optical module according to an embodiment of the present invention;
fig. 5 is a schematic partial structural diagram of an optical module according to an embodiment of the present invention;
fig. 6 is a block diagram of an internal structure of an optical module provided in this embodiment;
fig. 7 is a schematic basic flowchart of a data transmission method according to an embodiment of the present invention;
fig. 8 is a schematic basic flow chart of a data receiving method according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
One of the core links of optical fiber communication is the interconversion of optical and electrical signals. The optical fiber communication uses optical signals carrying information to transmit in information transmission equipment such as optical fibers/optical waveguides, and the information transmission with low cost and low loss can be realized by using the passive transmission characteristic of light in the optical fibers/optical waveguides; meanwhile, the information processing device such as a computer uses an electric signal, and in order to establish information connection between the information transmission device such as an optical fiber or an optical waveguide and the information processing device such as a computer, it is necessary to perform interconversion between the electric signal and the optical signal.
The optical module realizes the function of interconversion of optical signals and electrical signals in the technical field of optical fiber communication, and the interconversion of the optical signals and the electrical signals is the core function of the optical module. The optical module is electrically connected with an external upper computer through a golden finger on an internal circuit board of the optical module, and the main electrical connection comprises power supply, I2C signals, data signals, grounding and the like; the electrical connection mode realized by the gold finger has become the mainstream connection mode of the optical module industry, and on the basis of the mainstream connection mode, the definition of the pin on the gold finger forms various industry protocols/specifications.
Fig. 1 is a schematic diagram of connection relationship of an optical communication terminal. As shown in fig. 1, the connection of the optical communication terminal mainly includes the interconnection among the optical network terminal 100, the optical module 200, the optical fiber 101 and the network cable 103;
one end of the optical fiber 101 is connected with a far-end server, one end of the network cable 103 is connected with local information processing equipment, and the connection between the local information processing equipment and the far-end server is completed by the connection between the optical fiber 101 and the network cable 103; and the connection between the optical fiber 101 and the network cable 103 is made by the optical network terminal 100 having the optical module 200.
An optical port of the optical module 200 is externally accessed to the optical fiber 101, and establishes bidirectional optical signal connection with the optical fiber 101; an electrical port of the optical module 200 is externally connected to the optical network terminal 100, and establishes bidirectional electrical signal connection with the optical network terminal 100; the optical module realizes the interconversion of optical signals and electric signals, thereby realizing the establishment of information connection between the optical fiber and the optical network terminal; specifically, the optical signal from the optical fiber is converted into an electrical signal by the optical module and then input to the optical network terminal 100, and the electrical signal from the optical network terminal 100 is converted into an optical signal by the optical module and input to the optical fiber.
The optical network terminal is provided with an optical module interface 102, which is used for accessing an optical module 200 and establishing bidirectional electric signal connection with the optical module 200; the optical network terminal is provided with a network cable interface 104, which is used for accessing the network cable 103 and establishing bidirectional electric signal connection with the network cable 103; the optical module 200 is connected to the network cable 103 through the optical network terminal 100, specifically, the optical network terminal transmits a signal from the optical module to the network cable and transmits the signal from the network cable to the optical module, and the optical network terminal serves as an upper computer of the optical module to monitor the operation of the optical module.
At this point, a bidirectional signal transmission channel is established between the remote server and the local information processing device through the optical fiber, the optical module, the optical network terminal and the network cable.
Common information processing apparatuses include routers, switches, electronic computers, and the like; the optical network terminal is an upper computer of the optical module, provides data signals for the optical module, and receives the data signals from the optical module, and the common upper computer of the optical module also comprises an optical line terminal and the like.
Fig. 2 is a schematic diagram of an optical network terminal structure. As shown in fig. 2, the optical network terminal 100 has a circuit board 105, and a cage 106 is disposed on a surface of the circuit board 105; an electric connector is arranged in the cage 106 and used for connecting an electric port of an optical module such as a golden finger; the cage 106 is provided with a heat sink 107, and the heat sink 107 has a projection such as a fin that increases a heat radiation area.
The optical module 200 is inserted into the optical network terminal, specifically, the electrical port of the optical module is inserted into the electrical connector inside the cage 106, and the optical port of the optical module is connected to the optical fiber 101.
The cage 106 is positioned on the circuit board, and the electrical connector on the circuit board is wrapped in the cage, so that the electrical connector is arranged in the cage; the optical module is inserted into the cage, held by the cage, and the heat generated by the optical module is conducted to the cage 106 and then diffused by the heat sink 107 on the cage.
Fig. 3 is a schematic diagram of an optical module according to an embodiment of the present invention, and fig. 4 is a schematic diagram of an optical module according to an embodiment of the present invention. As shown in fig. 3 and 4, the optical module 200 provided by the embodiment of the present invention includes an upper housing 201, a lower housing 202, an unlocking member 203, a circuit board 300, a light emitting module 400, and a light receiving module 500;
the upper shell 201 is covered on the lower shell 202 to form a wrapping cavity with two openings; the outer contour of the wrapping cavity is generally a square body, and specifically, the lower shell comprises a main plate and two side plates which are positioned at two sides of the main plate and are perpendicular to the main plate; the upper shell comprises a cover plate, and the cover plate covers two side plates of the upper shell to form a wrapping cavity; the upper shell can also comprise two side walls which are positioned at two sides of the cover plate and are perpendicular to the cover plate, and the two side walls are combined with the two side plates to realize that the upper shell covers the lower shell.
The two openings may be two ends (204, 205) in the same direction, or two openings in different directions; one opening is an electric port 204, and a gold finger of the circuit board extends out of the electric port 204 and is inserted into an upper computer such as an optical network terminal; the other opening is an optical port 205 for external optical fiber access to connect the optical transmitting assembly 400 and the optical receiving assembly 500 inside the optical module; the optoelectronic devices such as the circuit board 300, the light emitting assembly 400 and the light receiving assembly 500 are positioned in the package cavity.
The assembly mode of combining the upper shell and the lower shell is adopted, so that the circuit board 300, the light emitting assembly 400, the light receiving assembly 500 and other devices can be conveniently installed in the shells, and the outermost packaging protection shell of the optical module is formed by the upper shell and the lower shell; the upper shell and the lower shell are made of metal materials generally, so that electromagnetic shielding and heat dissipation are facilitated; generally, the housing of the optical module is not made into an integrated component, so that when devices such as a circuit board and the like are assembled, the positioning component, the heat dissipation component and the electromagnetic shielding component cannot be installed, and the production automation is not facilitated.
The unlocking component 203 is located on the outer wall of the wrapping cavity/lower shell 202, and is used for realizing the fixed connection between the optical module and the upper computer or releasing the fixed connection between the optical module and the upper computer.
The unlocking component 203 is provided with a clamping component matched with the upper computer cage; the end of the unlocking component can be pulled to enable the unlocking component to move relatively on the surface of the outer wall; the optical module is inserted into a cage of the upper computer, and the optical module is fixed in the cage of the upper computer by a clamping component of the unlocking component; by pulling the unlocking component, the clamping component of the unlocking component moves along with the unlocking component, so that the connection relation between the clamping component and the upper computer is changed, the clamping relation between the optical module and the upper computer is released, and the optical module can be drawn out from the cage of the upper computer.
The circuit board 300 is located in a packaging cavity formed by the upper shell and the shell, and the circuit board 300 is provided with chips, capacitors, resistors and other electric devices. The method comprises the following steps of selecting chips to be set according to the requirements of products, wherein common chips comprise a microprocessor MCU, a clock data recovery chip CDR, a laser driving chip, a transimpedance amplifier TIA chip, an amplitude limiting amplifier LA chip, a power management chip and the like.
The transimpedance amplifier chip is closely associated with the light receiving chip, the short-distance wiring design can ensure good received signal quality, and in one packaging form of the optical module, the transimpedance amplifier chip and the light receiving chip are packaged together in an independent packaging body, such as the same coaxial tube shell TO or the same square cavity; the independent packaging body is independent of the circuit board 300, and the light receiving chip and the transimpedance amplifier chip are electrically connected with the circuit board 300 through the independent packaging body; in another package form of the optical module, the light receiving chip and the transimpedance amplifier chip may be disposed on the surface of the circuit board 300 without using a separate package. Of course, the light receiving chip may be packaged separately, and the transimpedance amplifier chip may be disposed on the circuit board 300, so that the received signal quality may also meet some relatively low requirements.
The chip on the circuit board 300 may be an all-in-one chip, for example, a laser driver chip and an MCU chip are integrated into one chip, or a laser driver chip, a limiting amplifier chip and an MCU chip are integrated into one chip, and the chip is an integrated circuit, but the functions of each circuit do not disappear due to the integration, and only the circuit form is integrated. Therefore, when the circuit board 300 is provided with three independent chips, namely, the MCU, the laser driving chip and the amplitude limiting amplifier chip, the scheme is equivalent to that when a single chip with three functions is provided on the circuit.
The circuit board 300 is a carrier of main components of the optical module, and components not arranged on the circuit board 300 are finally electrically connected with the circuit board 300, and the connector on the circuit board 300 realizes the electrical connection between the optical module and an upper computer thereof. Such as the light emitting assembly 400 and the light receiving assembly 500 of fig. 4. The light emitting assembly 400 and the light receiving assembly 500 may be collectively referred to as an optical sub-assembly.
The optical transmission assembly 400 in this embodiment is packaged in a coaxial TO package, physically separated from the circuit board, and electrically connected through a flexible board; the light receiving module 500 is also a coaxial TO package, physically separated from the circuit board, and electrically connected through a flexible board. In another common implementation, may be disposed on a surface of the circuit board 300.
The circuit board 300 has a gold finger 301 on the surface of the end, the gold finger is composed of a pin independent from each other, the circuit board 300 is inserted into the electric connector in the cage, and the gold finger is electrically connected with the upper computer. The upper computer and the optical module can adopt an I2C protocol to carry out information transmission through I2C pins. The upper computer can write information into the optical module, and particularly, the upper computer can write the information into a register of the optical module; the optical module cannot write information into the upper computer, and when the optical module needs to provide information to the upper computer, the optical module writes the information into a preset register (such as a transmission status register, a data transmission failure register, and the like set in this embodiment) in the optical module, and the upper computer reads the register, and the register of the optical module is generally integrated in an MCU of the optical module, or can be independently set on the circuit board 300 of the optical module.
In the working process of the optical module, the optical module is configured to send a relatively high-frequency data optical signal according to a data electrical signal from the optical line terminal so as to maintain an original external data transmission service of the optical line terminal, and at the same time, the optical module also sends a relatively low-frequency control optical signal according to a non-data electrical signal (i.e., a signal not used for a normal transmission service) so as to send control information to the optical module at the opposite end, so that control data is transmitted to the remote system without interrupting the normal service, for example, online upgrade of the remote system, report of DDM (Digital Diagnostic Monitoring ) information and the like are realized by using a low-frequency message channel transmission system upgrade package.
Since the optical module and the optical module at the opposite end are both externally connected by one optical fiber, the data optical signal and the control optical signal are mixed in the same light beam to be transmitted by the same optical fiber, in order to distinguish different signals, the data optical signal and the control optical signal are set to have different frequencies in the embodiment, and specifically, a low-frequency signal (control optical signal) is superposed on a high-frequency signal (data optical signal) sent by the optical module. For example, a low frequency signal of 50Kbps is superimposed on a 10Gbps or 25Gbps signal, wherein the 10Gbps or 25Gbps signal is a normal traffic signal, and another 50Kbps low frequency signal added performs other manipulation functions.
Further, due to the role of the MCU in the light module, it is necessary to: the control module controls the operation of circuits such as LDD, LD and APD, the communication between the optical module and the upper computer, and the data receiving and sending operations of the message channel. However, the MCU is a single-threaded processor, so that there is a conflict between the above three applications, for example, when the upper computer I2C accesses the optical module, since the access right of I2C is the highest, the MCU may interrupt the control of the optical module probabilistically, but the performance of the optical module is not affected even if the relevant control parameters of the optical module are not refreshed, and the access of I2C does not occupy the resources of the MCU completely, so the normal operation of the optical module is not affected. However, when the optical module has transmission or reception of a non-data electrical signal, the external I2C may cause message transmission failure because the MCU transmits a long string of data to the light emitting circuit, wherein the present embodiment refers to a path formed by devices used for transmission of an optical signal as the light emitting circuit, such as the signal transmitting circuit 304 and the light emitting module 400 in fig. 5, constituting the light emitting circuit, or receives a long string of data from the light receiving circuit, wherein the present embodiment refers to a path formed by devices used for reception of an optical signal as the light receiving circuit, such as the signal receiving circuit 305, the matching circuit 306 and the light receiving module 500 in fig. 5, constituting the light receiving circuit.
Based on the above problem, in the optical module provided in this embodiment, the circuit board is provided with the first microprocessor and the second microprocessor which are electrically connected, the first microprocessor is electrically connected with the golden finger on the circuit board and is used for communicating with the upper computer, and the second microprocessor is used for realizing the sending and receiving work of the non-data electrical signal. Namely, the message channel function is separated from the communication function of the optical module and the upper computer, so that the problem that the message transmission fails due to the external I2C when the optical module sends or receives a message is solved. Based on the foregoing implementation principle, the optical module provided in this embodiment will be described in detail below with reference to the accompanying drawings.
Fig. 5 is a schematic partial structure diagram of an optical module according to an embodiment of the present invention. As shown in fig. 5, the circuit board 300 of the present embodiment is provided with a first microprocessor 302 and a second microprocessor 303.
The first microprocessor 302 is electrically connected with the golden finger 301 and is used for realizing data interaction with an upper computer; in addition, the first microprocessor 302 is also electrically connected to a signal transmitting circuit 304 and a signal receiving circuit 305 disposed on the circuit board, and is configured to control power-on initialization, parameter configuration, operation supervision, and the like of relevant chips in the signal transmitting circuit 304 and the signal receiving circuit 305. The second microprocessor 303 is electrically connected to the first microprocessor 302, the light emitting module 400 and the matching circuit 306, respectively.
Based on the configuration, in the message sending process, the first microprocessor 302 receives the non-data electric signal, namely the data related to the low-frequency signal from the upper computer through the golden finger 301, and stores the data into the internal preset data storage area; then, while the second microprocessor 303 is in an idle state, the non-data electrical signal is written into the second microprocessor 303 through I2C; in addition, the first microprocessor 302 may also write internal monitoring data of the optical module, such as voltage, temperature, and the like, into the second microprocessor 303 through I2C when the second microprocessor 303 is in an idle state. In this embodiment, the data received by the first microprocessor 302 from the upper computer and the collected data inside the optical module are collectively referred to as data related to the low frequency signal. The second microprocessor 303 receives the data related to the low frequency signal and then transmits the data through the optical transmission circuit, wherein the optical transmission module 400 can be controlled to modulate the low frequency signal into the high frequency signal for data signal transmission, i.e., to load the optical signal of the low frequency signal, so as to transmit the data related to the low frequency signal.
It should be noted that, in this embodiment, two microprocessors are configured to communicate in an I2C manner, so that when data transmission is performed, the microprocessors do not need to verify received data, and meanwhile, since the first microprocessor 302 needs to interact with an upper computer, the first microprocessor 302 is set as a master processor and the second microprocessor 303 is a slave processor in this embodiment, in a specific implementation process, the first microprocessor 302 may also be set as a slave processor, that is, the second microprocessor 303 may copy data related to the low-frequency signal from the first microprocessor 302 to the inside thereof, so as to implement a function of the first microprocessor 302 sending the data related to the low-frequency signal to the second microprocessor 303. Of course, the data transmission method between the two microprocessors is not limited to the I2C method.
In the message receiving process, the optical receiving assembly 500 receives an optical signal sent by an opposite-end optical module, converts the received optical signal into an electrical signal, and the signal receiving circuit 305 connected with the optical receiving assembly 500 performs corresponding processing such as signal amplification and filtering on the electrical signal and sends the electrical signal to an upper computer through the golden finger 301, so that a high-frequency data optical signal received by the optical module can be converted into a data electrical signal and then sent to the upper computer. Meanwhile, the matching circuit 306 is electrically connected to the light receiving module 500, and is configured to analyze a low-frequency signal from the mixing signal output by the light receiving module 500; then, the low frequency signal is sent to the second microprocessor 303 electrically connected to the second microprocessor 303, after the second microprocessor 303 completes the reception of the low frequency signal this time, an indication message indicating that the data reception is completed may be sent to the first microprocessor 302, and after the first microprocessor 302 receives the indication message, the message data stored in the second microprocessor 303 is copied to the content thereof in the manner of I2C, and the upper computer is notified to read the low frequency signal from the first microprocessor 302.
Because the two microprocessors are responsible for different working contents, the upper computer can access the first microprocessor 302 while rapidly polling the optical module, and further the message receiving and sending process of the second microprocessor 303 is not affected, so that the problem that the upper computer damages the optical module is solved while the upper computer can timely acquire and update the status bytes sent by the optical module is ensured, and the message transmission rate of the system is integrally improved.
Further, in order to prevent the first microprocessor 302 from interrupting the data processing process of the second microprocessor 303 when reading data from the second microprocessor 303 or writing data to the second microprocessor 303, the second microprocessor 303 may generate indication information of whether it is in an idle state, wherein the first microprocessor 302 may perform a read or write operation only when it is in the idle state. In a specific implementation manner, an idle status indication bit may be set, or, as in the internal block diagram of the optical module in fig. 6, a message indication pin is set between two microprocessors, where a sending status indication pin I/O1 and a receiving status indication pin I/O2 are respectively set between the first microprocessor 302 and the second microprocessor 303.
With respect to the design manner in fig. 6, the following description will be made by taking components used in the light emitting circuit and the light receiving circuit and the working process as examples.
For the optical transmission circuit, the input end of the first clock data recovery module 3041 is electrically connected to the gold finger 301 for shaping the high-frequency signal from the upper computer, so that the distortion degree of the signal sent to the laser driving chip 3042 can be reduced, and the optical transmission module 400 can output the optical signal with low signal distortion degree based on the high-quality high-frequency signal. The laser driving chip 3042 is electrically connected to the anode of the laser 401 and the high-frequency control pin of the electro-absorption modulator 402, wherein the laser driving chip 3042 can output a constant-power current to the laser 401, so that the laser 401 can output a laser without carrying a signal to the electro-absorption modulator 402. In addition, the laser driving chip 3042 is further configured to output the high-frequency differential signal shaped by the first clock data recovery module 3041 to the electro-absorption modulator 402 after performing amplitude adjustment.
The electro-absorption modulator 402 is an optical signal modulation device manufactured by utilizing the exciton absorption effect in a semiconductor, and can output optical signals with different powers according to voltage changes caused by reference voltages and received high-frequency electric signals, and the magnitude of the reference voltages is directly related to the absorption capacity of the electro-absorption modulator 402 for laser light, so that the reference voltage pin of the electro-absorption modulator 402 is electrically connected with the output end of the second microprocessor 303 through a digital-to-analog conversion chip (not shown in the figure).
The second microprocessor 303 receives the data related to the low frequency signal transmitted by the first microprocessor 302, wherein the second microprocessor 303 receives the data related to the low frequency signal transmitted by the first microprocessor 302, and the second microprocessor 303 sets the level value of the transmission status indication pin I/O1 to a second level value, such as a high level value, to indicate that it is in an operating state and deny access to the first microprocessor 302. The second microprocessor 303 outputs low-frequency-varying digital signals of 0 and 1 based on the received data related to the low-frequency signal, so as to control the variation of the analog signal value output by the digital-analog conversion chip, and further enable the digital-analog conversion chip to output a low-frequency-varying analog voltage signal, and when the low-frequency-varying analog voltage signal is used as the reference voltage of the electro-absorption modulator 402, the absorption capability of the electro-absorption modulator 402 for the laser light is changed along with the variation of the voltage value of the low-analog voltage signal, so as to modulate the low-frequency signal in the high-frequency signal. After the second microprocessor 303 completes the current transmission of the non-data electrical signal, the level value of the transmission status indication pin I/O1 is set to a first level value, for example, a low level value, to indicate that the second microprocessor 303 is in an idle state, that is, the first microprocessor 302 can transmit new data related to the low frequency signal to the second microprocessor 303 again.
For the light receiving circuit, if the light receiving chip in the light receiving module 500 adopts an APD avalanche photodiode, since the APD avalanche photodiode needs a voltage higher than the voltage for normal operation of the optical module when operating, a voltage boost circuit is added in the optical module, and the voltage boost circuit is used for providing a working high voltage for the APD; in order to receive photocurrent, a mirror image circuit is added in the optical module, the booster circuit is connected with the APD through a passage in the mirror image circuit, the current in the passage is the photocurrent generated by the APD, and the current in the passage is used for receiving high-frequency signals subsequently; and mirroring the current in the path through a mirroring circuit so as to obtain a mirroring current of the photocurrent, wherein the mirroring current is used for receiving a low-frequency signal subsequently. The photocurrent from the light receiving chip is the most original current and is preferentially used for demodulation of the high-frequency signal to ensure the quality of service data, but theoretically, since the mirrored current is the same as the original current, the mirrored current may be used for receiving the high-frequency signal, and the original current may be used for receiving the low-frequency signal. A conversion circuit may also be integrated in the mirror circuit to convert the current for low frequency signal reception into a voltage signal.
As shown in fig. 6, the optical receiving assembly 500 is configured to receive an optical signal sent by an opposite-end optical module, and convert the received optical signal into a current signal; the transimpedance amplifier 3051 connected to the output terminal of the light receiving element 500 converts the current signal into a voltage signal, and transmits the voltage signal to the limiting amplifier 3052 connected thereto in the form of a high-frequency differential signal, and the limiting amplifier 3052 amplifies a signal output from the transimpedance amplifier 3051; and the second clock data recovery module 3053 is connected to the output end of the limiting amplifier 3052 and is configured to shape the signal output by the limiting amplifier 3052, and the output end of the second clock data recovery module 3053 is connected to the gold finger 301. The connecting finger 301 is connected with an upper computer, so that high-frequency signals, namely data electric signals, received by the optical module can be sent to the upper computer.
The matching circuit 306 is electrically connected to the light receiving module 500, for example, a boost mirror circuit, a first low-pass filter circuit, a second low-pass filter circuit and a comparator circuit may be disposed inside the matching circuit 306, the boost mirror circuit is electrically connected to the light receiving chip and the first low-pass filter circuit in the light receiving module 500, respectively, and the boost mirror circuit outputs working high voltage to the light receiving chip; the boosting mirror circuit outputs a mirror electric signal of the first mixed frequency electric signal to the first low-pass filter circuit; the second low-pass filter circuit is electrically connected with the first low-pass filter circuit, and the first low-pass filter circuit outputs a first initial low-frequency electric signal to the second low-pass filter circuit; the first input end of the comparison circuit is electrically connected with the first low-pass filter circuit, the second input end of the comparison circuit is electrically connected with the second low-pass filter circuit, and the output end of the comparison circuit is connected with the microprocessor; the first low-pass filter circuit inputs a second initial low-frequency electric signal to the comparison circuit; the second low-pass filter circuit inputs a decision threshold electric signal to the comparison circuit; the comparison circuit outputs the final low-frequency electric signal to the second microprocessor 303. The second microprocessor 303 stores the received signal in its internal preset storage area, and then after the second microprocessor 303 completes the reception of the signal and checks the data content correctly, the level value of the reception status indication pin I/O2 is set to the second level value, for example, the pin level value is set to 1, and after the first microprocessor 302 checks that the reception status indication pin I/O2 is changed to the second level value, the non-data electrical signal is copied to its internal and the host computer is notified to read the non-data electrical signal.
Meanwhile, the action of the first microprocessor 302 accessing the second microprocessor 302 will cause the second microprocessor 302 to set the level value of the reception status indication pin I/O2 from the second level value to the first level value, such as setting the pin level value to 0, for example, the second microprocessor 302 detects whether a data length byte in a data packet received by the second microprocessor with respect to a non-data electrical signal is accessed, and if accessed, sets the level value of the reception status indication pin I/O2 to the first level value. Of course, the second microprocessor 302 may also set the level value of the reception status indication pin I/O2 to the first level value when it starts receiving low frequency data, indicating that the message is being received and the access of the first microprocessor 302 is denied.
Further, the light receiving module 500 in this embodiment uses an APD avalanche diode for photoelectric conversion, and in order to supply power to the APD, the matching circuit 306 in this embodiment is further provided with a boost chip, specifically, since the first microprocessor 302 is configured to take charge of power-on operation of each chip in this embodiment, the first microprocessor 302 is also electrically connected to the matching circuit 306. Of course, if the light receiving module 500 performs photoelectric conversion by using a PIN (photodetector), a boost chip is not required to be provided in the matching circuit 306, and further, the matching circuit 306 is not connected to the first microprocessor 302.
It should be noted that the low-frequency signal analyzing circuit in this embodiment is not limited to the above implementation, and for example, a mirror circuit may be provided in the transimpedance amplifier 3051 in fig. 6, so as to mirror the photocurrent from the light receiving chip in the light receiving module 500, and output the mirrored current through the current output terminal, thereby realizing output of a mixed-frequency electrical signal for subsequent low-frequency signal reception. The mirror circuit may be disposed in the transimpedance amplifier 3051, or may be disposed on a circuit board outside the transimpedance amplifier 3051. The mirror current can be directly output by the mirror circuit, or can be connected to the transimpedance amplifier 3051 and output by the current output terminal of the transimpedance amplifier 3051. Then, a first low-pass filter circuit, a second low-pass filter circuit and a comparison circuit are arranged, wherein the transimpedance amplification chip outputs a mixed-frequency electric signal to the first low-pass filter circuit, the second low-pass filter circuit is electrically connected with the first low-pass filter circuit, and the first low-pass filter circuit outputs a first initial low-frequency electric signal to the second low-pass filter circuit; the first input end of the comparison circuit is electrically connected with the first low-pass filter circuit, the second input end of the comparison circuit is electrically connected with the second low-pass filter circuit, the output end of the comparison circuit is connected with the microprocessor, and the first low-pass filter circuit inputs a second initial low-frequency electric signal to the comparison circuit; the second low-pass filter circuit inputs a decision threshold electric signal to the comparison circuit; the comparison circuit outputs the final low-frequency electric signal to the second microprocessor 303. In addition, to implement the transmission of data related to the low frequency signal, the second microprocessor 303 may also be electrically connected to the signal transmission circuit 304, for example, the second microprocessor 303 may add a low frequency signal to a bias (bias) direct current for controlling the laser in the light emitting assembly 400 to emit light based on the data it receives, and further implement the modulation of the previous low frequency signal based on the high frequency signal for the transmission of the non-data electrical signal.
Further, in the transmission and reception of the low-frequency signal, in order to implement the functions that the first microprocessor 302 can enable the second microprocessor 303 to transmit a message, and the first microprocessor 302 can perform corresponding interaction with an upper computer, and the like, the present embodiment further sets a preset register in the optical module, where the preset register is generally integrated in the microprocessor of the optical module, and may also be independently set on a circuit board of the optical module.
The method for transmitting a low frequency signal according to this embodiment will be described in detail with reference to the accompanying drawings. Fig. 7 is a schematic basic flow chart of a data transmission method provided in this embodiment. As shown in fig. 7, the method specifically includes the following steps:
s701, the first microprocessor judges whether the second microprocessor is in an idle state or not.
For example, when a transmission status indication pin is provided between two processors, the first microprocessor may monitor whether a level value of the transmission status indication pin is a first level value, for example, is set to 0, and if so, determine that the second microprocessor is in an idle state, and then may execute step S702 to write data related to the low frequency signal into the second microprocessor. Or, a corresponding idle state indication bit may be set in the second microprocessor, and the first microprocessor determines whether the second microprocessor is in an idle state by reading the idle state indication bit.
Furthermore, if the data related to the low-frequency signal is from the upper computer, the data amount to be transmitted is usually large due to the control data transmitted to the far-end system at present, and the number of data bytes transmitted at one time by the existing low-frequency message channel is limited. Therefore, in this embodiment, a manner of splitting, sending, receiving and integrating the data packets to be transmitted is provided, and when the manner is adopted, the sending end needs to ensure that the sending end upper computer can perform enabling sending of the next data only after the receiving end upper computer finishes reading the data sent by the sending end each time. To meet the above requirement, a sending status flag bit for the first microprocessor is set in a register of the optical module, which is referred to as a first sending status flag bit g _ message sendable 1 in this embodiment, and meanwhile, a two-end system (which relates to a sending-end upper computer, a sending-end optical module, a receiving-end upper computer, and a receiving-end optical module) establishes an interaction system for implementing a data transmission mode of splitting, sending, receiving, and integrating the data packet.
Therefore, based on the application scenario, when the first microprocessor monitors that the sending state flag bit is the first preset value, it is determined whether the second microprocessor is in an idle state. For the enabling mode of the first microprocessor for sending the status flag bit, the first microprocessor may change the first preset value of the first microprocessor to a second preset value, for example, from 1 to 0, the upper computer to which the optical module is connected may change the second preset value of the optical module to the first preset value, for example, from 0 to 1, and of course, if actually needed, the first microprocessor may also change the second preset value of the optical module to the first preset value. In addition, when the optical module is initially powered on, the default value of the sending state flag bit g _ messagesendable 1 is a second preset value.
The upper computer (which may be referred to as a sending end upper computer for short) to which the optical module is connected can divide a data packet to be sent into N small data packets, and the N small data packets are sequentially sent out through the optical transmitting circuit. Before the upper computer enables the optical module to transmit data, the upper computer firstly queries the first transmission status flag g _ messagesendable 1, wherein the register in the transmission optical module can be queried through an I2C communication mode by using an I2C pin on a gold finger on the surface of the optical module circuit board. When the flag bit is a second preset value, for example, 0, it indicates that the optical module is in an idle state, and the optical module can be enabled to transmit data, and at this time, the upper computer needs to set the flag bit to be the first preset value, for example, 1, so as to enable the optical module to transmit data; when the zone bit is the first preset value, the upper computer can not transmit new data until the zone bit is changed into the second preset value in the module, which indicates that the upper computer can transmit the next data
Further, the first microprocessor in the optical module can detect whether the upper computer has an action of changing the sending state mark; and if the action of changing the sending state flag of the upper computer is detected, inquiring whether the value written into a sending state flag bit register by the upper computer is a first preset value or not. If the sending state flag bit is changed into a first preset value by the upper computer, monitoring whether the second microprocessor is in an idle state or not is executed; otherwise, the sending status flag bit may be continuously queried after a preset time interval.
For the query mode of the sending status flag g _ messagesendable, both the optical module and the upper computer may query the sending status flag in a polling manner, for example, when the upper computer queries that the flag is the first preset value, the upper computer queries the flag after a preset time interval, for example, 1 ms.
S702, the first microprocessor sends the data related to the low-frequency signal stored in the preset data storage space of the first microprocessor to the second microprocessor, and sets the sending state flag bit of the second microprocessor to be a first preset value, if the flag is set to be 1, the second microprocessor is instructed to send the data related to the low-frequency signal.
Wherein the first microprocessor can write the data related to the low frequency signal stored in the preset data storage space thereof into the second microprocessor through I2C. Of course, the second microprocessor may also copy the data from the first microprocessor to its interior.
The plurality of registers for storing data in the optical module form the preset data storage space, and of course, the preset data storage space may also be an area for storing data opened in one of the registers.
Further, since all the positions in the register are not filled with data every time, the embodiment further provides a transmission data length register g _ SendLength in the optical module, and the upper computer writes the data length that needs to be transmitted in this time into the register. Meanwhile, the data has a default initial position, so that the storage position of the data in the register is represented by the default initial position and the data length together, and the correctness of data transmission can be effectively ensured.
When the first microprocessor inquires that the sending state flag bit g _ messagesendable 1 is the first preset value, the first microprocessor sends the data stored in the preset data storage space, the data packets to be sent if needed, and the sending length to the second microprocessor in sequence, and simultaneously, the sending state flag bit g _ messagesendable 2 of the second microprocessor is set to be the first preset value, and if the flag is set to be 1, the second microprocessor is instructed to send out the data related to the low-frequency signal.
And S703, when monitoring that the sending state flag bit is a first preset value, the second microprocessor sends the received data related to the low-frequency signal out through an optical transmission circuit.
Meanwhile, in the process of sending a message by the second microprocessor, in order to prevent the access interruption of the data sending process by the first microprocessor, the second microprocessor sets the level value of the sending state indicating pin to a second level value, for example, 1, before sending the data, so as to indicate the processing data sending state and refuse the access of the first microprocessor.
Further, in order to ensure that the optical module at the opposite end can correctly receive the transmitted data, the embodiment sets a data retransmission mechanism in the optical module, wherein during the data transmission of the optical module, the transmission status flag g _ message sendable 1 of the first microprocessor and the transmission status flag g _ message sendable 2 of the second microprocessor are both kept unchanged, that is, both are kept at the first preset value, and further, the embodiment provides a time when the two transmission status flags are changed to the second preset value, that is, after this step, steps S704 to S708 are further included.
It should be noted that, in practical applications, the data sent by the optical module may also be initial data written by the upper computer, and the data obtained after the optical module performs corresponding processing. In addition, when a data length register g _ SendLength is arranged in the optical module, data in a preset data storage space is sent out according to the sending data length and the default data starting position.
In addition, the encoding format of the transmitted data may include a data frame header, a data length, a command code number, valid data, a checksum, and a data frame trailer. The receiving end can instruct an upper computer of the receiving end to read the data stored in the optical module register according to the length value of the data; the use of the data sent this time can be indicated by using the command code number; the receiving end can check the correctness of the valid data in the received data packet according to the checksum.
S704: the second microprocessor determines whether a response message that the data has been read is received.
The embodiment is described by taking as an example that the transmitted data is read by an upper computer (which may be referred to as a receiving end upper computer for short) accessed by the receiving end optical module, so as to realize the functions of upgrading the receiving end system or reporting digital diagnostic information. In order to enable the receiving-end optical module to notify an upper computer connected thereto to read data related to the low-frequency signal received by the optical module, a receiving-state flag g _ MessageReceState is set in the receiving-end optical module. When the receiving-end optical module receives data through the low-frequency information channel and checks the data correctly, the receiving state flag bit is set to a first preset value, for example, the receiving state flag bit g _ messagerecestat is set to 1, which is used for informing the receiving-end upper computer that new data has been received and simultaneously returning a response message that the data has been correctly received to the sending end.
Furthermore, after the receiving end upper computer inquires that the receiving state flag bit is set to be the first preset value in a polling mode, the receiving end upper computer can immediately read the received data, and the receiving state flag bit is changed from the first preset value to the second preset value after the reading is finished. The operation of changing the receiving state flag bit from the first preset value to the second preset value can stimulate the receiving end optical module to send back a response message that the data is read to the sending end optical module.
If a response message that the data sent by the receiving-end optical module has been read is received, step S705 is performed. Otherwise, step S707 is executed.
S705: and if a response message that the data is read is received, the second microprocessor sets the sending state flag bit to be a second preset value and sends an indication message that the second microprocessor is in an idle state to the first microprocessor.
For example, the second microprocessor may send an indication message to the first microprocessor that it is in an idle state by setting the level value of the transmission status indication pin to a first level value, e.g., to 0.
S706: and when the first microprocessor receives the indication message that the second microprocessor is in the idle state, setting the sending state flag bit of the first microprocessor to be a second preset value.
The first microprocessor changes the sending state zone bit from a first preset value to a second preset value, and is used for informing the upper computer connected with the first microprocessor that the data sending is finished, so that the next data sending can be carried out.
In order to prevent a long time waiting for a return message of the optical module at the receiving end, the present embodiment further sets an internal active clear mechanism of the optical module, and may also set other clear mechanisms, such as clear by an upper computer, and correspondingly, the present embodiment configures the sending state control byte for the second microprocessor, for example, bit0 for sending the state control byte is a sending state flag bit, bit1 is a receiving state flag bit, bit2 is a bottom layer sending failure flag bit, and bit3 is a far-end failure flag bit, so as to represent different data transmission results. Correspondingly, the present embodiment sets a mode in which the first microprocessor configures the transmission status flag bit thereof, specifically, the first microprocessor sets the transmission status flag bit of the first microprocessor to a second preset value according to the read transmission status control byte of the second microprocessor, where the transmission status control byte includes the transmission status flag bit.
S707: and if the response message that the data is read is not received, judging whether the sent time length of the data exceeds a preset time length threshold value.
The preset time length threshold is larger than the time required by the optical module at the receiving end for receiving, checking and returning the message. After the data stored in the preset data storage space is sent out, the second microprocessor starts timing and waits for a response message that the data returned by the optical module at the receiving end is read, if the response message that the data is read is not received yet after the preset time length threshold is exceeded, step S708 is executed, otherwise, the second microprocessor continues to wait for the return message of the optical module at the receiving end.
S708: if the time length exceeds the preset time length threshold value, the second microprocessor changes the sending state flag bit from the first preset value to the second preset value, and sends an indication message that the second microprocessor is in an idle state to the first microprocessor.
Similarly, the first microprocessor may also set the transmission status flag bit of the first microprocessor to the second preset value according to the read transmission status control byte of the second microprocessor, and may also generate identification information of the receiving end fault.
Wherein, in order to facilitate the differentiation of the fault of the receiving end, corresponding processing measures are taken. In this embodiment, when the second microprocessor receives a response message that the data returned by the receiving end has been correctly received by the receiving end optical module, but does not receive a response message that the data has been read by the receiving end upper computer, first identification information for indicating a fault of the upper computer at the receiving end may be generated, and then, after the upper computer accessed by the sending end optical module receives the identification information, retransmission of the data may be enabled or a notification of a fault of the remote upper computer may be generated. In addition, if the second microprocessor does not receive the response message that the sending data returned by the receiving-end optical module has been correctly received all the time, the sending state flag bit is changed from the first preset value to the second preset value, meanwhile, second identification information for indicating that sending between the optical modules fails is generated, and then after the sending-end upper computer receives the identification information, measures such as enabling data to be sent again can be taken.
Corresponding to the two response messages, the preset duration threshold in step S707 may be composed of a first preset duration threshold used for waiting for a response message that the data returned by the receiving-end optical module has been correctly received by the receiving-end optical module, and a second preset duration threshold used for waiting for a response message that the data returned by the receiving-end optical module has been read after receiving a response message that the data has been correctly received by the receiving-end optical module. Further, if the data retransmission mechanism is adopted after the data transmission fails, the first preset duration threshold consists of N preset sub-duration thresholds, the specific number of the N preset sub-duration thresholds is determined according to the upper limit value of the retransmission times, and the specific duration of each preset sub-duration threshold is set according to the time required for correctly receiving the transmitted data and the returned data.
The following describes the receiving method of the low frequency signal provided in this embodiment in detail. Fig. 8 is a basic flowchart of a receiving and transmitting method provided in this embodiment. As shown in fig. 8, the method specifically includes the following steps:
s801: and after the second microprocessor checks the related data content of the received low-frequency signal correctly, generating the indication information of the received low-frequency signal.
For example, when the receiving status indication pin is disposed between the two processors, the first microprocessor may monitor whether the level value of the sending status indication pin is set to the second level value by the second microprocessor, for example, whether the level value is set to 1, and if so, it is determined that the second microprocessor receives the data related to the low frequency signal, and then step S802 may be executed. Or, a corresponding indication bit for receiving the low-frequency signal may be set in the second microprocessor, and the first microprocessor may obtain the state of the second microprocessor by reading the indication bit.
In addition, after the second microprocessor checks the data content of the low-frequency signal correctly, in order to make the sending-end optical module know the data transmission result, it will also return a message that the data has been correctly read to the sending-end module, and at the same time, set its receiving status flag g _ MessageReceState2 to a first preset value, for example, to 1.
S802: after the first microprocessor detects the indication information of the received low-frequency signal, the low-frequency signal received by the second microprocessor is copied to the internal preset data storage space.
In this embodiment, the access from the first microprocessor to the second microprocessor is set to enable the second microprocessor to set the level value of the reception status indication pin to the first level value, for example, to 0.
Further, if the received data needs to be sent to the upper computer, in order to enable the receiving-end optical module to notify the upper computer (referred to as the receiving-end upper computer for short) to which the receiving-end optical module is connected to read the data related to the received low-frequency signal, the embodiment further configures a receiving status flag g _ MessageReceState1 for the first microprocessor. Moreover, for the enabling mode of the receiving status flag bit, the first microprocessor may change the second preset value of the first microprocessor to the first preset value, for example, from 0 to 1, and the upper computer to which the receiving-end optical module is connected may only change the first preset value of the upper computer to the second preset value, for example, from 1 to 0. In addition, when the receiving end optical module is initially powered on, the receiving state flag bit g _ messagesendable 1 defaults to be the second preset value.
When the first microprocessor copies the low frequency signal received by the second microprocessor into its internal preset data storage space, the receiving status flag is set to the first preset value, for example, the receiving status flag g _ MessageReceState1 is set to 1, so as to inform the connected upper computer that new data has been received.
Furthermore, the receiving end upper computer may query that the receiving status flag g _ MessageReceState1 is set as a first preset value in a polling manner, and then immediately read the data, wherein the data is not filled in all positions in the preset data storage space every time, so that the embodiment further includes a data length sending register in the first microprocessor, and the first microprocessor writes the data length received this time into the register.
Then, after the receiving end upper computer finishes data reading, the receiving state flag g _ MessageReceState1 is changed from a first preset value to a second preset value, and of course, a receiving end optical module can be used to change the receiving state flag, which is only changed by the upper computer more directly and accurately.
Further, the second microprocessor may notify the sending-end optical module whether the message has been correctly read, and in this embodiment, after this step, the following step is further included:
s803: the first microprocessor monitors whether the receiving state flag bit is changed from the first preset value to a second preset value.
If so, step S804 is performed, otherwise step S805 is performed.
S804: if the first preset value is changed into a second preset value, the first microprocessor changes the receiving state flag bit of the second microprocessor from the first preset value into the second preset value, so that the second microprocessor sends a message that the data is read.
For example, the first microprocessor changes the receiving status flag bit of the second microprocessor from 1 to 0, so that the laser second microprocessor sends back a message that the data has been read to the sending-end module.
S805: and if the received time length of the low-frequency signal is not changed to the second preset value, the first microprocessor judges whether the received time length of the low-frequency signal exceeds the preset time length.
S806: and if the time length exceeds the preset time length, the first microprocessor changes the receiving state flag bit from the first preset value to a second preset value.
The first microprocessor actively changes the receiving status flag bit from the first preset value to the second preset value, which indicates that the data received this time is discarded. Furthermore, the receiving status flag bit of the second microprocessor is kept at the first preset value, the function of transmitting a message that the data is correctly received back to the sending-end optical module is not triggered, and meanwhile, at the sending end, if the sending-end optical module does not receive a response message that the data is read by the receiving-end upper computer after a certain time, the sending status flag bit is actively changed from the first preset value to the second preset value, which indicates that the sent data is discarded, and identification information of equipment faults at the receiving end is generated.
It should be noted that, the present embodiment provides an optical module with dual microprocessors, and a scheme for separating a message channel function of the optical module from functions of the optical module and an upper computer is applicable to not only the form in which the optical transmitter module and the optical receiver module are separately packaged, but also the form in which the optical transmitter module and the optical receiver module are packaged together to form an optical transceiver sub-module, and a package form in which an optical transceiver chip is mounted on a circuit board, and for any package form, a related device for transmitting an optical signal is referred to as an optical transmitter module in the present embodiment, and a related device for receiving an optical signal is referred to as an optical receiver module in the present embodiment.
Finally, it should be noted that: the embodiment is described in a progressive manner, and different parts can be mutually referred; in addition, the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (10)

1. A light module, comprising:
a circuit board;
the first microprocessor is arranged on the circuit board, is electrically connected with the golden finger arranged on the circuit board and is used for sending data related to the low-frequency signal to the second microprocessor in an idle state;
the second microprocessor is arranged on the circuit board, is electrically connected with the first microprocessor, is used for sending out data related to the low-frequency signal through the light emitting circuit, is used for receiving the low-frequency signal analyzed by the light receiving circuit and then forwards the low-frequency signal to the first microprocessor;
and the sending state indication pin is arranged between the first microprocessor and the second microprocessor and used for indicating whether the second microprocessor is in an idle state or not.
2. The light module of claim 1, wherein the step of the first microprocessor sending low frequency signal related data to the second microprocessor comprises:
the first microprocessor judges whether the second microprocessor is in an idle state;
and if the second microprocessor is in an idle state, the first microprocessor sends the data related to the low-frequency signal stored in the preset data storage space of the first microprocessor to the second microprocessor, and sets the sending state flag bit of the second microprocessor to a first preset value so as to indicate the second microprocessor to send the data related to the low-frequency signal out.
3. The optical module of claim 2, wherein if the data related to the low frequency signal is data received by the first microprocessor through the gold finger, the first microprocessor determines whether the second microprocessor is in an idle state, and further comprising:
the first microprocessor monitors whether the sending state flag bit is a first preset value or not;
and if the first microprocessor monitors that the sending state flag bit is a first preset value, the first microprocessor judges whether the second microprocessor is in an idle state.
4. A light module according to any one of claims 1 to 3, wherein a send status indication pin is provided between the first microprocessor and the second microprocessor, wherein:
after the second microprocessor receives the data related to the low-frequency signal from the first microprocessor, the second microprocessor sets the level value of the sending state indicating pin to be a second level value so as to indicate that the second microprocessor is in a data sending state;
after the second microprocessor sends out the data related to the low-frequency signal, if the second microprocessor receives a response message that the data has been read, the level value of the sending state indication pin is set to a first level value to indicate that the second microprocessor is in an idle state.
5. The light module of claim 1, wherein the step of the second microprocessor forwarding the low frequency signal to the first microprocessor comprises:
after the data content of the low-frequency signal is checked to be correct, the second microprocessor generates indication information of the received low-frequency signal;
after the first microprocessor detects the indication information of the received low-frequency signal, the low-frequency signal received by the second microprocessor is copied to the internal preset data storage space.
6. The optical module of claim 5, wherein after the second microprocessor verifies the data content of the low frequency signal, the optical module further comprises:
the second microprocessor sets the receiving state flag bit thereof to a first preset value;
after the first microprocessor copies the low-frequency signal received by the second microprocessor to its internal preset data storage space, the method further includes:
the first microprocessor sets the receiving state flag bit thereof to a first preset value;
the first microprocessor monitors whether the receiving state flag bit is changed from the first preset value to a second preset value;
if the receiving state flag bit of the first microprocessor is changed from the first preset value to the second preset value, the first microprocessor changes the receiving state flag bit of the second microprocessor from the first preset value to the second preset value so as to indicate the second microprocessor to send a message that the low-frequency signal is read.
7. The light module according to claim 1 or 5, wherein a receive status indication pin is provided between the first microprocessor and the second microprocessor, wherein:
after the second microprocessor checks the data content of the low-frequency signal correctly, setting the level value of the receiving state indicating pin as a second level value to indicate that the receiving state indicating pin receives the low-frequency signal;
the action of the first microprocessor reading the low frequency signal from the second microprocessor triggers the second microprocessor to set the level value of the receiving state indication pin from the second level value to the first level value.
8. The light module of claim 1, wherein the first microprocessor and the second microprocessor are electrically connected via an I2C bus.
9. The light module of claim 1, further comprising a light emission drive circuit and a light emission assembly, wherein:
the second microprocessor is electrically connected with the input end of the light emission driving circuit, and the output end of the light emission driving circuit is electrically connected with the light emission component;
alternatively, the first and second electrodes may be,
the optical module further comprises a light emission driving circuit and a light emission assembly, the light emission assembly comprises a laser and an electro-absorption modulator, wherein:
the laser is electrically connected with the light emission driving circuit;
the electroabsorption modulator is electrically connected with the second microprocessor and the light emission driving circuit respectively.
10. The optical module according to claim 1 or 9, further comprising a light receiving chip, a transimpedance amplification chip, a clipping amplification chip, a first low-pass filter circuit, a second low-pass filter circuit, and a comparison circuit, wherein:
the transimpedance amplification chip is electrically connected with the light receiving chip, the amplitude limiting amplification chip and the first low-pass filter circuit respectively;
the second low-pass filter circuit is electrically connected with the first low-pass filter circuit;
the first input end of the comparison circuit is electrically connected with the first low-pass filter circuit, the second input end of the comparison circuit is electrically connected with the second low-pass filter circuit, and the output end of the comparison circuit is electrically connected with the second microprocessor;
alternatively, the first and second electrodes may be,
the optical module further comprises a light receiving chip, a boost mirror circuit, a first low-pass filter circuit, a second low-pass filter circuit and a comparison circuit, wherein:
the boosting mirror circuit is electrically connected with the light receiving chip and the first low-pass filter circuit respectively;
the second low-pass filter circuit is electrically connected with the first low-pass filter circuit;
the first input end of the comparison circuit is electrically connected with the first low-pass filter circuit, the second input end of the comparison circuit is electrically connected with the second low-pass filter circuit, and the output end of the comparison circuit is electrically connected with the second microprocessor.
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