CN216016848U

CN216016848U - System for collecting ultra-wideband wireless signals

Info

Publication number: CN216016848U
Application number: CN202122227757.2U
Authority: CN
Inventors: 李广兴
Original assignee: Shanghai TransCom Instruments Co Ltd
Current assignee: Transcom Shanghai Technologies Co Ltd
Priority date: 2021-09-14
Filing date: 2021-09-14
Publication date: 2022-03-11
Anticipated expiration: 2031-09-14

Abstract

The utility model relates to a system for collecting ultra wide band wireless signals, which comprises an anti-aliasing filter for anti-aliasing treatment; the ADC communication unit is used for transmitting data to the FPGA; the JESD204B dual-core synchronization unit is used for performing clock domain crossing data transmission through two FIFO units; the data caching unit is used for realizing the timed and quantitative continuous data caching; the DSP data processing unit is used for continuously reading the cache data and performing digital down-conversion and filtering processing; the processing data buffer unit buffers the processed IQ data in a DDR4 memory. Adopted the utility model discloses a storage unit for gathering ultra wide band radio signal, make full use of hardware circuit provides changes space resource into time resource, guarantees the reliable storage and the visit of super large bandwidth signal data stream, has reduced high-speed signal processing's the degree of difficulty.

Description

System for collecting ultra-wideband wireless signals

Technical Field

The utility model relates to a broadband wireless communication field especially relates to digital communication logic design field, specifically indicates a system for gathering ultra wide band radio signal.

Background

Currently, the running master clock of a high-speed FPGA generally does not exceed 400MHz, most FPGA logic designs are carried out, and the running clock is concentrated below 300 MHz. The traditional single-rate processing method can not process the quantized data with the bandwidth as high as 2GHz and the sampling rate as high as 6 GHz. In order to process high-bandwidth signals, a digital signal processing theory provides a multi-item processing method, DSP logic realization of the high-bandwidth signals is realized by adopting a multi-item parallel processing mode, the method needs to occupy more DSP hard core resources, and compromise consideration is needed under the condition that FPGA resources are limited. When the signal analyzer is used to analyze and demodulate a wireless signal, the signal is not continuously processed in real time, but only data continuity is ensured within a period of time, for example, when a 5G NR signal is analyzed, 2 frames of data are sampled, that is, 20ms of data is generally used to implement protocol analysis. In view of the above facts, and hope to adopt less logic resources, the technology adopted is mature and simple single rate processing method, the utility model provides a hardware architecture and FPGA logic realization that data are kept in storage-read transform in succession utilizes DDR4 buffer memory data, later reads data with the low-speed clock in succession from DDR4 and carries out the transform processing's method, can guarantee to adopt minimum DSP logic resources, realizes that signal analyzer is to ultra wideband signal's sampling, demodulation and protocol analysis.

SUMMERY OF THE UTILITY MODEL

The utility model aims at overcoming the shortcoming of above-mentioned prior art, providing one kind and satisfying the system that the accuracy is high, the complexity is few, application scope is comparatively extensive be used for gathering ultra wide band radio signal.

In order to achieve the above object, the utility model discloses a system for gathering ultra wide band wireless signal as follows:

the system for collecting the ultra-wideband wireless signal is mainly characterized by comprising the following components:

the anti-aliasing filter is used for carrying out anti-aliasing processing and feeding the anti-aliasing processing into the ADC for quantization;

the ADC communication unit is connected with the anti-aliasing filter and used for transmitting data to the FPGA so as to realize stable and efficient transmission of quantized data;

the JESD204B dual-core synchronization unit is connected with the ADC communication unit and is used for performing clock domain crossing data transmission through two FIFO units;

the data cache unit is connected with the JESD204B dual-core synchronization unit and is used for being controlled by an upper computer, providing operation parameters and realizing timed and quantitative continuous data cache;

the DSP data processing unit is connected with the data cache unit and is used for continuously reading cache data in the DDR4 memory and carrying out digital down-conversion and filtering processing;

and the processing data cache unit is connected with the DSP data processing unit and is used for caching the IQ data obtained by processing in a DDR4 memory.

Preferably, the system further includes a DDR4 memory connected to the DSP data processing unit and the processed data buffer unit for reading or writing data and performing data read-back operation to make the data stream continuous.

Preferably, the ADC communication unit uses 16 high-speed JESD204B protocol links, the single JESD204B protocol link has the speed of 6.144Gbps and the carrying signal throughput rate of no 98.304 Gbps.

Preferably, the clock domain of the system is divided into an ADC JESD204B (a) clock domain, an ADC JESD204B (B) clock domain, a DDR4(a) clock domain, a DDR4(B) clock domain, a digital signal processing clock domain and a PCIe communication clock domain, the ADC JESD204B (a) clock domain and the ADC JESD204B (B) clock domain are connected to the input of the DDR4(a) clock domain, the DDR4(a) clock domain, the digital signal processing clock domain, the DDR4(B) clock domain and the PCIe communication clock domain are connected in sequence, and the output end of each clock domain is connected to the cross-clock-domain FIFO unit.

Preferably, the ADC communication unit has a plurality of converters, and transmits the same sample data stream together through 2 separate JESD204B links.

Preferably, the JESD204B dual-core synchronization unit includes 2 independent clock domains, and performs synchronization through two FIFO units.

Preferably, the DSP data processing unit includes a DDR4 read function module and a data processing module, the DDR4 read function module and the data processing module are sequentially connected, and the data processing module performs digital down conversion, filtering and arbitrary sampling rate conversion.

Adopted the utility model discloses a storage unit for gathering ultra wide band radio signal, make full use of hardware circuit provides changes space resource into time resource, guarantees the reliable storage and the visit of super large bandwidth signal data stream. By means of caching, the digital down-conversion clock is changed in an equal proportion, the difficulty of high-speed signal processing is reduced, the operation method is compatible with a conventional method, and system integration is facilitated. The system architecture is reasonable, the data flow is clear, the DSP adopts single-time rate processing, and the use of DSP hard core resources is reduced.

Drawings

Fig. 1 is a conceptual block diagram of the system for acquiring ultra-wideband wireless signals according to the present invention, which implements low-speed clock processing of high-speed signals.

Fig. 2 is a basic block diagram of the system for acquiring ultra-wideband wireless signals of the present invention.

Fig. 3 is a schematic diagram of the division and synchronization method for different clock domains in the FPGA architecture of the system for acquiring ultra-wideband wireless signals of the present invention.

Detailed Description

In order to more clearly describe the technical content of the present invention, the following further description is given with reference to specific embodiments.

The technical solution of the system for collecting ultra-wideband wireless signals of the present invention is that the hardware structure and connection relationship of the whole hardware function platform supporting the realization of corresponding functions are mainly protected, and each of the included functional modules and module units can correspond to the actual known hardware device or specific hardware circuit in the integrated circuit structure, so that only the improvement of the specific hardware topology connection structure and specific hardware circuit is involved, the improvement of the hardware part exists, and does not depend on the computer control software, and does not belong to the carrier only executing the control software or computer program, so that the application of any control software or computer program is not involved to solve the corresponding technical problem and obtain the corresponding technical effect, that is, the present invention can solve the problem to be solved only by the improvement of the actual known hardware device or hardware circuit structure involved by these modules and units The technical problem is solved, and the corresponding technical effect is obtained, and the corresponding function can be realized without the assistance of specific control software or computer programs.

The utility model discloses a this a system for be used for gathering ultra wide band radio signal, include wherein:

the ADC communication unit is connected with the ADC intermediate frequency analog unit and is used for transmitting data to the FPGA so as to realize stable and efficient transmission of quantized data;

As a preferred embodiment of the present invention, the system further includes a DDR4 memory, connected to the DSP data processing unit and the processed data buffer unit, for reading or writing data, and performing data read-back operation to make the data flow continuous.

As the preferred embodiment of the utility model, the ADC communication unit uses 16 high-speed JESD204B protocol links, the single JESD204B protocol link has the speed of 6.144Gbps and the carrying signal throughput rate of no 98.304 Gbps.

As a preferred embodiment of the present invention, the clock domain of the system is divided into ADC JESD204B (a) clock domain, ADC JESD204B (B) clock domain, DDR4(a) clock domain, DDR4(B) clock domain, digital signal processing clock domain and PCIe communication clock domain, the ADC JESD204B (a) clock domain and ADC JESD204B (B) clock domain are connected to the input of DDR4(a) clock domain, the DDR4(a) clock domain, digital signal processing clock domain, DDR4(B) clock domain and PCIe communication clock domain are connected in sequence, and the output end of each clock domain is connected to the FIFO unit across clock domains.

As a preferred embodiment of the present invention, the ADC communication unit has a plurality of converters, and transmits the same sample data stream through 2 separate JESD204B links.

As a preferred embodiment of the present invention, the JESD204B dual-core synchronization unit includes 2 independent clock domains, and performs synchronization through two FIFO units.

As the preferred embodiment of the present invention, the DSP data processing unit includes DDR4 read function module and data processing module, DDR4 read function module and data processing module link to each other in proper order, data processing module carry out digital down conversion, filtering and arbitrary sampling rate conversion processing.

The utility model discloses an among the concrete embodiment, provide one kind and utilized DDR4 as the signal buffer memory, later read DDR4 buffer memory data in succession through the low-speed clock, realize that single-time rate digit down conversion and a circuit of filtering realize with the scheme that the logic realized, solved the signal analysis appearance to the long data signal analysis's of one section continuity of ultra wide band signal demand.

The utility model discloses a figure 1 utilizes the cache mechanism, realizes that the low-speed clock handles high-speed signal concept block diagram, and the meaning lies in that ultra wide band high-speed signal can't use single rate to carry out FPGA signal processing, changes into earlier cache, reads again to the low-speed is handled, and the design of handling clock and wave filter carries out the scaling, and the real signal is through the IQ data that the low-speed processing obtained, and frequency spectrum information is the same with the high-speed mechanism completely.

Fig. 2 is a basic block diagram of the present invention, illustrating the basic structure and components for implementing data buffering and low-rate continuous-flow signal processing by using DDR 4. The functional units are drawn in detail through the functional block diagram, signal flow and control flow are marked, and design concepts and methods are fully displayed.

FIG. 3 is a schematic of the method of partitioning and synchronizing different clock domains in an FPGA architecture. The block diagram further illustrates the clock domain division in the schematic functional block diagram, and indicates the rate change and the connection mode of each functional unit.

The functional structure of the scheme is shown in fig. 2, and mainly comprises six parts, namely a high sampling rate data acquisition circuit taking a high-speed JESD204B as a data interface, a data cache unit taking a DDR4 as a storage unit, a low-speed clock DDR4 continuous reading and subsequent stream processing real-time flow control unit, a digital signal processing unit such as a digital down-conversion and filter and a PCIE data communication and control unit of an upper computer. The scheme is divided into six clock domains, namely an ADC JESD204B (A) clock domain, an ADC JESD204B (B) clock domain, a DDR4(A) clock domain, a DDR4(B) clock domain, a digital signal processing clock domain and a PCIe communication clock domain. The signal flow and cross-clock domain interaction is shown in fig. 3.

The utility model discloses a system has different functional unit:

ADC intermediate frequency analog unit: the device consists of a band-pass anti-aliasing filter and a high-speed ADC. This section enables quantization of passband signals up to 2GHz bandwidth.

ADC-JESD204B communication Unit: and the 16 Lane high-speed JESD204B protocol links are used for realizing the transmission of data from the ADC to the FPGA and realizing the stable and efficient transmission of the quantized data. The single Lane rate of the JESD204B reaches 6.144Gbps, and the throughput rate of the bearing signals reaches 98.304 Gbps.

JESD204B dual core synchronization unit: the synchronization of the data received by the transmitting core of the dual JESD204B is realized by using two FIFOs and adopting a simultaneous non-empty and simultaneous reading algorithm.

JESD204B-DDR4(A) data cache Unit: the data cache is controlled by an upper computer, provides operation parameters, has a trigger function, and realizes the continuous data cache of timing and quantification.

DDR4(a) -DSP data continuous read processing unit: the upper computer controls and the adaptive flow control, realizes continuous non-dislocation reading of the cache data in the DDR4, and sends the cache data to the DSP unit for digital down conversion and filtering processing.

DSP-DDR4(B) post-processing data cache Unit: and caching the IQ data obtained after the DSP processing into a DDR4 (B).

DDR4(B) -PCIE data upload unit: and uploading the IQ data stored in the DDR4(B) to an upper computer for demodulation or protocol analysis processing according to the instruction requirement.

The utility model discloses a processing procedure as follows:

1. the front-end circuit of the signal analyzer performs frequency conversion processing on the radio-frequency signal to a fixed frequency point 4608 MHz; the passband signal is subjected to anti-aliasing processing through a passband 2GHz band-pass filter and fed into an ADC for quantization; the ADC sampling frequency is 6144 MHz;

2. the high-speed ADC is an interleaved sampling architecture, and high-speed sampling of 6144MHz is realized; a plurality of converters are arranged in the ADC, and the number of the final corresponding JESD204B transmission units is 2; two separate JESD204B links are used to collectively transport the same sample data stream.

3. The FPGA communicates with the ADC internally using a JESD204B IP core provided by Xilinx. The number of used JESD204B receiving units is two, and two receiving units can be regarded as two independent clock domains and need to be synchronized through two FIFOs. The synchronization strategy is that both FIFOs are simultaneously read non-empty. The synchronous FIFO is bridged across two clock domains, so that reliable signal transfer across the clock domains is ensured, and meanwhile, the data bit width on two sides of the synchronous FIFO is matched with user logic, so that the conversion of the data bit width is realized.

4. And caching the synchronized JESD204B data according to an instruction issued by the upper computer, wherein the instruction comprises information such as a trigger response, a data starting address core data length and the like. Such as buffering 20ms of data in 5G NR TM mode.

5. The running clock of the DSP processing unit is not more than 300MHz, and the performance of the FPGA device is met. The DSP processing unit comprises an uninterrupted DDR4 reading function module (flow control module) and a digital down-conversion, filtering and arbitrary sampling rate conversion module. The unit reads DDR data according to an instruction issued by an upper computer, ensures that the stream continuously and uninterruptedly carries out DSP processing, and obtains IQ data.

6. And the DSP-DDR4(B) post-processing data cache unit stores the IQ data into the DDR4(B) so as to meet the requirement of a subsequent upper computer on the IQ data and subsequent flow control.

7. The PCIE data transmission unit transmits the maintained continuous IQ data back to the upper computer according to the request of the upper computer;

8. the upper computer acquires continuous IQ data stream and performs subsequent signal demodulation and protocol analysis operations.

The technical scheme of the utility model is further explained in detail with the attached drawings as follows:

the utility model provides a system based on DDR4 cache technique realizes ultra-high bandwidth signal processing, has realized through carrying out data cache to high-speed signal in advance, and follow-up through reasonable flow control, realized that the low-speed is read cache data and is carried out digital signal processing operations such as digital down conversion, filtering and arbitrary sampling rate transform.

In this routine, as shown in fig. 2, there are 11 data nodes in total, and the node definitions and parameters are shown in the following table.

Table 1 data node definitions and descriptions

The upper computer with the X86 architecture runs a Windows or Linux operating system and is an initiating unit for issuing and controlling sampling parameters. The FPGA communicates with the upper computer through a PCIe link, and is a communication link for data return and instruction issue. The FPGA serves as a peripheral device, PCIE equipment is formed in system startup enumeration, and after a proper driver and an API frame library are loaded, upper computer software can send a write instruction and a read instruction to the FPGA logic function block. The above description emphasizes the master-slave architecture of the system and the end-use of the data.

Referring to fig. 2, from left to right, the ADC quantization unit is at the front end, and the FPGA device is at the rear end, and performs logical entity operations. The data flow direction is from left to right, and 11 nodes are respectively marked. The node names and parameter meanings refer to the contents of table 1. Firstly, the intermediate frequency signal is fed into the ADC through the anti-aliasing filter for quantization, the ADC is communicated with the FPGA by adopting a JESD204B high-speed serial link, and quantized data are transmitted into the FPGA. The JESD204B Link adopted by the ADC is composed of two links, and clock synchronization needs to be performed inside the FPGA to form data with the same clock synchronization and 512bit width. Referring to fig. 3, the synchronized data is transferred at node 4 to DDR4 memory via a data cache control unit, which is controlled by the host computer, has a plurality of configurable parameters and actions, and has the capability to respond to external trigger events. The node 5 is a DDR4 memory write interface, and the node data is subjected to clock synchronization and data bit width conversion through clock domain crossing FIFO, and is matched with logic clocks and data bit widths at two ends. The data reading flow control unit is also controlled by an upper computer, has a plurality of configurable parameters and actions, and mainly aims to read DDR4 data according to an instruction sent by the upper computer, and adopts a flow control mechanism in the period to ensure the continuity of outlet data, so as to perform the bit width matching of a clock and data of the data for the next signal processing. The signal processing unit mainly adopts a single rate method to realize digital down conversion, filtering and random sampling rate conversion, and the single rate method can reduce the complexity of coefficient generation and reduce the use amount of DSP hard core resources. The data processing unit is controlled by the upper computer, has the actions of starting, running, stopping and the like, can continuously carry out DSP processing on a section of data, and the processed I/Q data is further cached to DDR (B) after being synchronized by an FIFO clock to wait for the upper computer to send a data return instruction. The data communication control unit has two functions, namely responding to the instruction of the upper computer and then controlling other functional units, and secondly, returning and controlling data, so that the I/Q data after the DSP is ensured to be correctly uploaded to the upper computer.

For a specific implementation of this embodiment, reference may be made to the relevant description in the above embodiments, which is not described herein again.

It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.

It should be noted that, in the description of the present invention, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means at least two unless otherwise specified.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and the scope of the preferred embodiments of the present invention includes other implementations in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present invention.

It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by suitable instruction execution devices. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, and the corresponding program may be stored in a computer readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

In addition, each functional unit in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may also be stored in a computer readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In this specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system for acquiring ultra-wideband wireless signals, the system comprising:

2. The system for acquiring ultra-wideband wireless signals of claim 1, further comprising a DDR4 memory coupled to the DSP data processing unit and the processed data buffer unit for reading or writing data and performing data read-back operations to continue data flow.

3. The system for acquiring ultra-wideband wireless signals as claimed in claim 1, wherein said ADC communication unit uses 16 high-speed JESD204B protocol links, a single JESD204B protocol link has a speed of 6.144Gbps, and a signal throughput rate of 98.304 Gbps.

4. The system for acquiring the ultra-wideband wireless signal as claimed in claim 1, wherein the clock domain of the system is divided into an ADC JESD204B (a) clock domain, an ADC JESD204B (B) clock domain, a DDR4(a) clock domain, a DDR4(B) clock domain, a digital signal processing clock domain and a PCIe communication clock domain, the ADC JESD204B (a) clock domain and the ADC JESD204B (B) clock domain are connected to the input of the DDR4(a) clock domain, the DDR4(a) clock domain, the digital signal processing clock domain, the DDR4(B) clock domain and the PCIe communication clock domain are connected in sequence, and the output end of each clock domain is connected to the cross-clock-domain FIFO unit.

5. The system for acquiring ultra-wideband wireless signals of claim 1, wherein said ADC communication unit has a plurality of converters, and transmits the same sampled data stream jointly through 2 separate JESD204B links.

6. The system for acquiring ultra-wideband wireless signals of claim 1, wherein said JESD204B dual core synchronization unit comprises 2 independent clock domains, synchronized by two FIFO units.

7. The system for acquiring ultra-wideband wireless signals according to claim 1, wherein the DSP data processing unit comprises a DDR4 read function module and a data processing module, the DDR4 read function module and the data processing module are connected in sequence, and the data processing module performs digital down-conversion, filtering and arbitrary sample rate conversion.