CN2159582Y

CN2159582Y - Electronic programable timer

Info

Publication number: CN2159582Y
Application number: CN 93208477
Authority: CN
Inventors: 丘双安
Original assignee: QIU SHUAN AN
Current assignee: QIU SHUAN AN
Priority date: 1993-03-29
Filing date: 1993-03-29
Publication date: 1994-03-23
Anticipated expiration: 2003-03-29

Abstract

The utility model relates to a programmable electronic timer, which is mainly composed of an oscillator, a multi-stage frequency divider, an output control circuit, an alarm circuit, etc. The adoption of the crystal oscillator makes the timing time relatively accurate; the output control circuit comprises a plurality of RS triggers, and single group of normally open contact button switches is used to change the state of the rs triggers to achieve the purpose of programming. The utility model easily achieves thinness, miniaturization and micropower consumption, and the utility model is convenient in carrying; as a frequently used timing alarm device, the utility model is in particular suitable for the household and travelling requirements.

Description

Electronic programable timer

The utility model relates to a kind of electronic timer, particularly a kind of regularly programmable electronic timer of alarm set that is suitable for use as.

The timedreminder that is suitable for requires and can adjust timing in the scope of broad, and it is easy to require to set timing (i.e. programming) method, and timing accuracy is higher, and cost is lower.More existing timedreminders all exist some defective, and wherein Gong You weak point is: put noisy-be that programming operation is easy inadequately, therefore it is promoted the use of and is restricted.Introduced a kind of " family expenses timedreminder " such as 1992 the 2nd phases " radio " magazine, this machine mainly is made up of oscillator, multistage frequency divider, output control circuit, the noisy circuit of sound.8 common toggle switches are adopted in this machine programming, and the toggle switch volume is bigger, and machine volume is also bigger, and cost is higher.If but selected the toggle switch of small size for use, the difficulty of operation could be increased again.This machine regularly divide 8 grades adjustable, promptly pull 8 program switch and can make delay time increase by 1.25 fens respectively, 2.5 minutes, 5 ... 160 minutes, this two advance Cotton step-by-step counting mode also made the user feel not too convenient in practicality.Common commercially available electronic alarm clock, alarm watch is a common class timedreminder, and electronic alarm clock, alarm watch all use keyswitch to put noisy (i.e. programming) operation push-button on-off ratio operation toggle switch will to make things convenient for, but this class alarm clock, alarm watch to put the operator preface of making a noise more tired.And the alarm watch volume is too little, puts the outstanding sense inconvenience of the operation of making a noise.

The purpose of this utility model is to design a kind of electronic timer that utilizes the programming of some single group normal opened contact keyswitches, and this measuring device programming operation of keeping is easy, and is easy to realize thin typeization, miniaturization, is easy to carry.This machine at those rooms, tourism, need regularly to ring the user who reminds that makes a noise continually and design.

Programmable electronic timer of the present utility model comprises oscillator, multistage frequency divider, rings make a noise circuit and output control circuit.The input end of multistage frequency divider is sent in the output pulse of quartz oscillator, 2～3 output terminals of multistage frequency divider are received the input end that rings the circuit that makes a noise, provide driving pulse for ringing the circuit that makes a noise, ringing the circuit that makes a noise is many input ends gate circuit ［ D of a band output buffer stage ₆, one of them input end is as the input control end that rings the circuit that makes a noise, and the output terminal that rings the circuit that makes a noise is connected to electro-acoustic transducer ［ B ₂; other output terminals of multistage frequency divider are received the input end of output control circuit; influence the output state of output control circuit; and the output terminal of output control circuit is received the input control end that rings the circuit that makes a noise; the noisy circuit of control sound has the noisy signal output of sound or does not have the noisy signal of sound and export; the compound end of whole or big portion of multistage frequency divider connects together, and can pass through a compound button ［ S ₁Reset, and the state of output control circuit can be controlled by manual operation (be called reset, set operation).Difference according to set operation, the different output states of corresponding multistage frequency divider can make the noisy circuit of sound that output is arranged, promptly after multistage frequency divider is reset, the signal that makes a noise appears ringing through different delay times, thereby reach time-delay and ring the purpose of making a noise and reminding, of the present utility model being characterised in that has one 8 input end Sheffer stroke gate ［ D in the output control circuit ₇, 8 input end Sheffer stroke gate ［ D ₇Output terminal be exactly the output terminal of output control circuit, it receives the input control end of the circuit that ring to make a noise, when output control circuit output high level, its control rings the circuit that makes a noise to be had and rings the pulse output of making a noise.8 input end Sheffer stroke gate ［ D ₇8 input ends respectively with 8 two input ends or the door ［ D ₈～D ₁₅Output terminal link to each other, an input end of these 8 two input ends or door respectively with 8 rest-set flip-flop ［ D ₁₆～D ₂₃The Q output terminal link to each other, another input end of these 8 two input ends or door links to each other with some output terminals of multistage frequency divider by some simple logic gate circuits.The reset terminal of 8 rest-set flip-flops-S end has been connected in, can be by pressing reset button ［ S ₁Reset simultaneously, after 8 rest-set flip-flops resetted simultaneously, their Q output terminal all was output as 1, and by 8 two input ends or door ［ D ₈～D ₁₅Make 8 input end Sheffer stroke gate ［ D ₇Output low level, have this moment and ring the signal output of making a noise.Because of the reset terminal of rest-set flip-flop and the reset terminal of multistage frequency divider connect together, so pressing reset key ［ S ₁When 8 rest-set flip-flops were resetted, the whole or big portion of multistage frequency divider also was reset simultaneously, i.e. whole frequency dividers or all become low level (the not return-to-zero of prime minority frequency divider does not have influence to the timer operate as normal) at most of frequency divider output terminal.If only or several setting switch ［ S by next ₁～S ₉, just can make one or the output of several rest-set flip-flops become low level, and make 8 two input ends or door ［ D ₈～D ₁₅In one or several be output as low level, thereby make reminiscences end valve, have only through the some time, the output state of multistage frequency divider becomes certain particular state, make when 8 two input end OR circuit outputs all become high level, ring the sound generation again of making a noise, promptly reaching time-delay and ringing the purpose of making a noise and reminding, the length of delay time is decided by progression and frequency divider and interior 8 two inputs of output control circuit or the door ［ D of the frequency of oscillator, frequency divider ₈～D ₁₅Between the structure of simple combinatorial logic circuit, the simple combinatorial logic circuit is according to " certain of multistage frequency divider what when being output as high level, and high level appears in the input end of a certain two input end or door " to design.

From the above, the operation scheme for programming of timedreminder of the present invention is such, clicks reset key switch ［ S earlier ₁Rest-set flip-flop and some grades of frequency dividers are resetted simultaneously, then according to must delay time press 1 or several set keyswitches, programming operation has just been finished.But the wind programming operation is very easy.

Thereby timedreminder of the present utility model adopts quartz oscillator to guarantee timing accuracy; Program switch adopts single group normal opened contact keyswitch, such as using conductive rubber keyswitch or film key switch, not only make timer operation use very easy (be easy to obtain using always delay time), and make that the complete machine manufacture craft is simple, long service life also is easy to realize thin typeization; That multistage frequency divider and output control circuit are all realized easily is integrated, miniaturization and little power consumptionization.

Fig. 1 is the circuit diagram of an embodiment-a kind of timedreminder of the present utility model.

Be described in further detail below in conjunction with Fig. 1.

Fig. 1 circuit mainly comprises three parts: oscillatory circuit, 29 grades of two-dividers and output control circuit.By two not gate D ₁, D ₂And resistance R ₁, R ₂, quartz crystal B ₁And capacitor C ₁Form oscillator, the oscillation frequency of oscillator is defined as 27962Hz by quartz crystal, and oscillator signal is through not gate D ₃Send into 29 grades of frequency dividers after amplifying shaping, 29 grades of frequency dividers are divided into three groups, i.e. 5 grades of frequency divider D ₄, 11 grades of frequency divider D ₅With 13 grades of frequency divider D ₂₉5 grades of frequency divider D ₄Output signal frequency is 874Hz, 11 grades of frequency divider D ₅Output signal frequency is 0.43Hz, 13 grades of frequency divider D ₂9 have multistage exit, its

exit

29,28,27 ... 19 is respectively the 29th grade, 28 grades, 27 grades ... the output terminal of 19 grades of frequency dividers, its output signal cycle was respectively 320 fens, and 160 minutes, 80 minutes ... 0.3125 divide.5 grades of frequency divider D ₄With 11 grades of frequency divider D ₅Output signal be connected on three input ends or the door D ₆Two input ends on, if or the door D ₆The 3rd input end promptly to import control end be low level, or door D ₆The noisy signal output of interrupted sound is just arranged, if or door D ₆The input control end be high level, or the door D ₆To continue to export high level, and promptly not have and ring the signal output of making a noise.Or door D ₆Be exactly that this mechanism is rung the circuit that makes a noise, or door D ₆Output be exactly the output terminal of timedreminder, B ₂It is the piezoelectric ceramic piece that is connected on output terminal.Or door D ₆Input control end and output control circuit output terminal promptly the output terminal of 8 input end Sheffer stroke gates be connected.

Output control circuit comprises 8 input end Sheffer stroke gate D ₇, 8 or a D ₈～D ₁₅, 8 rest-set flip-flop D ₁₆～D ₂₃And 5 with door D ₂₄～D ₂₈The simple combinatorial logic circuit that constitutes reflects that the signal of rest-set flip-flop output state and the signal of 1 grade of reflection or what frequency divider output state pass through or door D ₈～D ₁5 receive Sheffer stroke gate D ₇Input end, the reset terminal of 8 rest-set flip-flops and the reset terminal of multistage frequency divider connect together, can be by single group normal opened contact keyswitch S ₁Reset.8 rest-set flip-flops respectively can be by 8 single group normal opened contact keyswitch S ₂～S ₉Set, S ₂～S ₉It is exactly program switch.

When clicking S ₁, 8 rest-set flip-flops are reset after (this moment, 13 grades of frequency dividers also were reset simultaneously) simultaneously, Sheffer stroke gate D ₇8 input ends all be high level, its output low level allows timer output to ring the signal that makes a noise.If 1 or several rest-set flip-flops are set Sheffer stroke gate D ₇The output high level makes and rings noisy stopping.When through time-delay after a while, after the output terminal of corresponding frequency divider becomes high level, make Sheffer stroke gate D again ₇Output becomes low level, and timer is exported again and rung the signal that makes a noise, and promptly finishes the function of regularly reminding.

Such as clicking reset switch S earlier ₁, ring the signal that makes a noise and produce, click setting switch S again ₃Rest-set flip-flop D ₁₇Be set, its output low level is passed through or door D ₉Control Sheffer stroke gate D ₇The output high level, ringing makes a noise stops, and through 5 minutes, high level appearred in the 24th grade of frequency divider output terminal, and it passes through or door D ₉Control Sheffer stroke gate D ₇Output low level is rung the signal that makes a noise and has been produced again again.

If click reset switch S earlier ₁, ring the signal that makes a noise and produce, click setting switch S again ₉, rest-set flip-flop D ₂₃Be set, its output low level is passed through or door D ₁₅Control Sheffer stroke gate D ₇The output high level, ring making a noise stops, through 5 hours, high level all appearred in the 26th grade, 27 grades, 28 grades, 28 grades frequency divider output terminals, by with door D ₂₆, D ₂₄With or the door D ₁₅Control Sheffer stroke gate D ₇Output low level is rung the signal that makes a noise and has been produced again.

The rest may be inferred, this as can be known timedreminder can have 8 grades of different locking times, promptly Yan Shi " step-length " have 8 grades available, they are 2 minutes, 5 minutes, 10 minutes, 20 minutes, 30 minutes, 1 hour, 2 hours and 5 hours, and 8 grades of time-delays can be program switch S by setting switch respectively ₂～S ₉Select, can select certain one-level delay time separately, also can select what delay time simultaneously, this moment, delay time was the summation of single-stage delay time.

Claims

A kind of programmable electronic timer, it comprises oscillator, multistage frequency divider, ring make a noise circuit and output control circuit, the output terminal of oscillator is received the input end of multistage frequency divider, 2～3 output terminals of multistage frequency divider are received the input end that rings the circuit that makes a noise, provide pumping signal for ringing the circuit that makes a noise, ring many input ends gate circuit that the circuit that makes a noise is a band buffering output stage, one of them input end is the input control end that rings the circuit that makes a noise, the output terminal that rings the circuit that makes a noise is connected to electro-acoustic transducer, other output terminals of multistage frequency divider are received the input end of output control circuit, influence the output state of output control circuit, and the output terminal of output control circuit is received the input control end that rings the circuit that makes a noise, the noisy circuit of control sound has the noisy signal output of sound or does not have the noisy signal of sound and export, whole or the big portion reset terminal of multistage frequency divider connects together, and can pass through a reset button [S ₁] reset,

It is characterized in that output control circuit is by one 8 input end Sheffer stroke gate [D ₇], 8 two input ends or door [D ₈～D ₁₅], 8 rest-set flip-flop [D ₁₆～D ₂₃] and simple combinatorial logic circuit composition, 8 input end Sheffer stroke gate [D ₇] output terminal be exactly the output terminal of output control circuit, 8 input end Sheffer stroke gate [D ₇] 8 input ends and 8 two input ends or door [D ₈～D ₁₅] output terminal link to each other 8 two input ends or door [D ₈～D ₁₅] an input end respectively with 8 rest-set flip-flop [D ₁₆～D ₂₃] output terminal link to each other 8 two input ends or door [D ₈～D ₁₅] another input end link to each other 8 rest-set flip-flop [D with some output terminals of multistage frequency divider by combinational logic circuit ₁₆～D ₂₃] reset terminal (S end) connect together, and and the reset terminal of multistage frequency divider connect together, can pass through a reset button [S ₁] reset 8 rest-set flip-flop [D ₁₆～D ₂₃] set end (R end) meet a set button [S respectively ₂～S ₉], be connected on multistage frequency divider and two input ends or door [D ₈～D ₁₅] between combinational logic circuit be to design according to " certain of multistage frequency divider what when being output as high level, and high level appears in the input end of a certain two input end or door ", thereby reach the purpose that delay time length is preset in control.