JPS5696527A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To remarkably reduce A/D conversion time, by separating the counter into upper-and lower-rank digits, rapidly closing the value to the objective by the upper-rank digit side and finely closing it to the objective at lower rank digit side. CONSTITUTION:When a logic control circuit 10 is reset with a start pulse Ps, H signal is output from the output 10a of the circuit 10, an AND gate 5 is opened, and a clock pulse Pc passes through a gate 5. In this case, a switch S1 is closed and S2, S3 are opened, the pulse Pc is fed to a counter 3a at upper rank digit side, and the count value is given to a D/A converter 4a. When the current i1 of a converter 4a increases and the voltage drop of a resistor 8 is in agreement with the set value of a comparator 1a, the state of the circuit 10 is changed, switch S1 is opened and S2, S3 are closed. Thus, the pulse Pc is fed to a counter 3b at lower-rank side. When the voltage drop of the resistor 8 by the current i2 of a D/A converter 4b is a set value 0 of a comparator 1b, the gate 5 is closed and the count value is the A/D conversion value.