CN215911433U - PERC battery back passivation structure and PERC battery comprising same - Google Patents

Abstract

The utility model provides a PERC battery back passivation structure and a PERC battery comprising the same. The utility model provides a PERC battery back passivation structure with a sandwich structure, wherein a main passivation structure is formed by sequentially laminating a first crystalline silicon oxide layer, a gallium oxide layer and a second crystalline silicon oxide layer, three layers of films are complementary, the back surface recombination rate is reduced, the back surface passivation effect is increased, and the passivation effect is improved.

Description

PERC battery back passivation structure and PERC battery comprising same

Technical Field

The utility model belongs to the technical field of photovoltaic cells, and relates to a PERC cell back passivation structure and a PERC cell comprising the same.

Background

PERC cells, i.e., passivated emitter and back cell technologies, originated in the 80's last century and can improve conversion efficiency by superimposing a passivation layer on the back of a conventional cell. The general process flow of the PERC cell comprises the following steps: texturing → diffusion → SE laser → oxidation → etching (PSG removal) → annealing → back film → front film → laser grooving → screen printing → sintering → light injection or electric injection → test sorting. The coating process is an important part of the production line process of the PERC battery. In the production process of the cell, a layer of antireflection film needs to be plated on the front surface, so that the light reflection is reduced, and the light absorption is enhanced. The back surface is coated with a passivation film, and the passivation film generally plays a role of surface passivation or bulk passivation by passivating dangling bonds on the surface of the silicon to reduce the recombination rate of the surface. Meanwhile, the high refractive index of the passivation film can enhance the reflectivity of the back surface to further improve the efficiency of the solar cell, so that the performance of the solar cell is directly influenced by the quality of the passivation film.

CN105470349A discloses a PERC solar cell and a method for manufacturing the same, wherein the PERC solar cell includes a silicon wafer, a silicon dioxide layer and a silver layer on the upper surface of the silicon wafer, a front silicon nitride passivation layer on the upper surface of the silicon dioxide layer, an aluminum oxide passivation layer on the lower surface of the silicon wafer, and a back silicon nitride passivation layer on the lower surface of the aluminum oxide passivation layer, wherein a plurality of openings are formed in the back silicon nitride passivation layer at intervals, and an aluminum layer which is etched off from the aluminum oxide passivation layer and forms aluminum-silicon alloy with the silicon wafer is filled in the openings. According to the utility model, holes are formed in the back silicon nitride passivation layer in a laser hole forming mode, the depth of each hole is controlled to penetrate through the back silicon nitride passivation layer but not through the aluminum oxide passivation layer, then aluminum paste is printed, and the aluminum paste is etched off the aluminum oxide passivation layer through a sintering process to form aluminum-silicon alloy with a silicon wafer.

CN209515679U discloses a PERC battery structure, comprising: the device comprises a substrate, a front silicon dioxide layer, an anti-reflection layer, a front silicon nitride layer, a back passivation layer and a protection structure; the front-side silicon dioxide layer is arranged on the front side of the substrate, the antireflection layer is arranged on one side, opposite to the substrate, of the front-side silicon dioxide layer, and the front-side silicon nitride layer is arranged on one side, opposite to the front-side silicon dioxide layer, of the antireflection layer.

CN110854240A discloses a PERC battery and a preparation method thereof, wherein the preparation method comprises texturing, diffusion, etching, back polishing, annealing, back coating and front coating. The back surface coating step comprises: and introducing ozone gas into the equipment provided with the annealed silicon wafer for oxidation treatment, so that a back silicon dioxide layer is formed on the back of the silicon wafer. And then continuously introducing ozone serving as an oxygen source in the same equipment, adding an aluminum source, and depositing a back aluminum oxide layer on the back silicon dioxide layer. A back side silicon nitride layer is deposited on the back side aluminum oxide layer.

At present, the commonly used deposition method of the silicon dioxide layer is a Plasma Enhanced Chemical Vapor Deposition (PECVD), silicon oxide is deposited by utilizing silane and laughing gas, the PECVD has a high growth speed, and the deposited silicon oxide film is also thick, but the structure is loose and the passivation effect is poor.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a PERC battery back passivation structure and a PERC battery comprising the same, and provides the PERC battery back passivation structure with a sandwich structure.

In order to achieve the purpose, the utility model adopts the following technical scheme:

in a first aspect, the utility model provides a back passivation structure of a PERC battery, which comprises a first crystalline silicon oxide layer, a gallium oxide layer, a second crystalline silicon oxide layer and at least two back silicon nitride layers, wherein the first crystalline silicon oxide layer, the gallium oxide layer, the second crystalline silicon oxide layer and the at least two back silicon nitride layers are sequentially stacked from the back of a silicon substrate.

The utility model provides a PERC battery back passivation structure with a sandwich structure, wherein a main passivation structure is formed by sequentially laminating a first crystalline silicon oxide layer, a gallium oxide layer and a second crystalline silicon oxide layer, three layers of films are complementary, the back surface recombination rate is reduced, the back surface passivation effect is increased, and the passivation effect is improved. Specifically, the method comprises the following steps: the first crystalline state silicon oxide layer is deposited on the surface of the silicon substrate and used for saturating dangling bonds on the surface of the silicon substrate, so that interface state density is reduced, and an excellent interface chemical passivation effect is provided.

In addition, the traditional silicon oxide layer mostly adopts amorphous silicon oxide, but the silicon-hydrogen bond combination of the amorphous silicon oxide is weaker, and the passivation effect is poorer, the crystalline silicon oxide is adopted to replace the traditional amorphous silicon oxide, although the atom distribution in the amorphous silicon oxide also has certain orderliness, only short-range orderliness is realized, and the atom distribution in the crystalline silicon oxide has long-range orderliness, so that compared with the amorphous silicon oxide layer, the crystalline silicon oxide layer has higher compactness, the passivation effect is better, and the interface state defect density can be as low as 10¹⁰cm^-2eV^-1And the comprehensive performance of the PERC battery is improved.

It should be noted that the crystalline silicon oxide defined in the present invention is a concept opposite to the amorphous silicon oxide, and the silicon oxide has a crystalline and an amorphous part, for example, the crystal (quartz) is a crystalline silicon oxide, and the oxide film thermally grown on the silicon wafer is an amorphous silicon oxide, and the atom distribution in the crystalline silicon oxide has a long-range order, and the atom distribution in the amorphous silicon oxide also has a certain order, but only a short-range order.

In addition, the back passivation structure claimed in the present invention is a partial structure in a PERC cell, and it is understood that other structures in the PERC cell are not specifically required and limited within the scope of protection defined herein, in other words, those skilled in the art can make routine replacement or creative improvement on other structures based on the prior art on the basis of the back passivation structure defined in the present invention.

As a preferable technical solution of the present invention, a connection block is disposed at a contact surface between the silicon substrate and the first crystalline silicon oxide layer, the connection block and the first crystalline silicon oxide layer are integrated into a whole, and the connection block is embedded in the silicon substrate.

In the utility model, the contact surface of the silicon substrate and the first crystalline silicon oxide layer is provided with a plurality of connecting blocks, and the contact area of the silicon substrate and the first crystalline silicon oxide layer is increased by additionally arranging the connecting blocks, so that the silicon substrate and the first crystalline silicon oxide layer are more stable, the normal use of a battery is ensured, and the service life of the battery is also ensured.

As a preferred technical solution of the present invention, a first fixed block is disposed at a contact surface between the first crystalline silicon oxide layer and the gallium oxide layer, the first fixed block and the gallium oxide layer are integrated, and the first fixed block is embedded in the first crystalline silicon oxide layer.

In the utility model, the contact surface of the first crystalline silicon oxide layer and the gallium oxide layer is provided with a plurality of first fixed blocks, and the contact area of the first crystalline silicon oxide layer and the gallium oxide layer is increased by additionally arranging the first fixed blocks, so that the first crystalline silicon oxide layer and the gallium oxide layer are more stable, the normal use of the battery is ensured, and the service life of the battery is also ensured.

As a preferred technical solution of the present invention, a second fixed block is disposed at a contact surface between the gallium oxide layer and the second crystalline silicon oxide layer, the second fixed block and the gallium oxide layer are integrated, and the second fixed block is embedded in the second crystalline silicon oxide layer.

In the utility model, the contact surface of the gallium oxide layer and the second crystalline silicon oxide layer is provided with a plurality of second fixed blocks, and the contact area of the gallium oxide layer and the second crystalline silicon oxide layer is increased by additionally arranging the second fixed blocks, so that the gallium oxide layer and the second crystalline silicon oxide layer are more stable, the normal use of the battery is ensured, and the service life of the battery is also ensured. Optionally, the first fixing block and the second fixing block are both trapezoidal in cross section.

In a preferred embodiment of the present invention, the thickness of the first crystalline silicon oxide layer is 1 to 10nm, and may be, for example, 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm or 10nm, but the thickness is not limited to the above-mentioned values, and other values not listed in the above-mentioned range are also applicable.

In a preferred embodiment of the present invention, the thickness of the gallium oxide layer is 5 to 10nm, and may be, for example, 5nm, 5.5nm, 6nm, 6.5nm, 7nm, 7.5nm, 8nm, 8.5nm, 9nm, 9.5nm or 10nm, but is not limited to the above-mentioned values, and other values not listed in the above-mentioned value range are also applicable.

In a preferred embodiment of the present invention, the thickness of the second crystalline silicon oxide layer is 1 to 10nm, and may be, for example, 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm or 10nm, but is not limited to the above-mentioned values, and other values not listed in the above-mentioned range are also applicable.

In a preferred embodiment of the present invention, the total thickness of all the back surface silicon nitride layers is 40 to 80nm, and may be, for example, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm or 80nm, but the number is not limited to the above-mentioned values, and other values not listed in the above-mentioned range are also applicable.

As a preferred technical scheme of the utility model, the thickness of each back silicon nitride layer is gradually reduced from inside to outside.

In a second aspect, the utility model provides a PERC cell comprising the PERC cell back passivation structure of the first aspect, wherein the PERC cell comprises a silicon substrate, an emitter, a front silicon oxide layer and a front silicon nitride layer are sequentially stacked on the front surface of the silicon substrate, and the PERC cell back passivation structure of the first aspect is disposed on the back surface of the silicon substrate.

The PERC battery also comprises a front electrode and a back electrode, wherein the front electrode is vertically inserted into the silicon substrate from the front side of the PERC battery, and the back electrode is vertically inserted into the silicon substrate from the back side of the PERC battery.

The present invention provides, for example, the following preparation methods for reference by the person skilled in the art, without limiting the scope of protection of the utility model:

(1) texturing the surface of the single crystal silicon substrate to form a textured surface, and cleaning the single crystal silicon substrate after texturing;

(2) carrying out phosphorus diffusion on the cleaned silicon substrate, generating phosphorus-silicon glass on the surface, and doping laser on the front surface of the silicon substrate to form a local heavily-doped region to obtain a selective emitter;

(3) removing the phosphorosilicate glass on the rest surface of the silicon substrate by etching with HF aqueous solution;

(4) depositing on the surface of the selective emitter by a thermal oxidation method to form a front silicon oxide layer;

(5) putting a silicon substrate into a film forming chamber, introducing laughing gas and silane into the film forming chamber, and depositing on the back of the silicon substrate by adopting a plasma enhanced chemical vapor deposition method to form an amorphous silicon oxide film;

(6) then annealing the silicon substrate under a hydrogen-rich atmosphere, wherein the hydrogen-rich atmosphere is a mixed gas of nitrogen and/or inert gas, and after the annealing is finished, the amorphous silicon oxide film is converted into a first crystalline silicon oxide layer;

(7) depositing on the surface of the first crystalline silicon oxide layer by ALD to form a gallium oxide layer;

(8) repeating the step (5) and the step (6), and depositing a second crystalline silicon oxide layer on the surface of the gallium oxide layer;

(9) depositing at least two back silicon nitride layers on the surface of the second crystalline silicon oxide layer by adopting PECVD;

(10) depositing on the surface of the front silicon oxide layer by adopting PECVD to form a front silicon nitride layer;

(11) and forming a front electrode and a back electrode on the front surface and the back surface of the silicon wafer respectively through screen printing and sintering.

Compared with the prior art, the utility model has the beneficial effects that:

(1) the utility model provides a PERC battery back passivation structure with a sandwich structure, wherein a main passivation structure is formed by sequentially laminating a first crystalline silicon oxide layer, a gallium oxide layer and a second crystalline silicon oxide layer, three layers of films are complementary, the back surface recombination rate is reduced, the back surface passivation effect is increased, and the passivation effect is improved. Specifically, the method comprises the following steps: the first crystalline state silicon oxide layer is deposited on the surface of the silicon substrate and used for saturating dangling bonds on the surface of the silicon substrate, so that interface state density is reduced, and an excellent interface chemical passivation effect is provided.

(2) The traditional silicon oxide layer mostly adopts amorphous silicon oxide, but the silicon-hydrogen bond combination of the amorphous silicon oxide is weaker, and the passivation effect is poorer, the utility model adopts the crystalline silicon oxide to replace the traditional amorphous silicon oxide, although the atom distribution in the amorphous silicon oxide also has certain orderliness, only short-range orderliness is realized, and the atom distribution in the crystalline silicon oxide has long-range orderliness, therefore, compared with the amorphous silicon oxide layer, the crystalline silicon oxide layer has higher compactness, the passivation effect is better, and the interface state defect density can be as low as 10¹⁰cm^-2eV^-1And the comprehensive performance of the PERC battery is improved.

Drawings

Fig. 1 is a schematic structural diagram of a PERC battery according to an embodiment of the present invention.

Wherein, 1-front electrode; 2-front side silicon nitride layer; 3-front side silicon oxide layer; 4-an emitter; a 5-silicon substrate; 6-a first crystalline silicon oxide layer; a 7-gallium oxide layer; 8-a second crystalline silicon oxide layer; 9-back side silicon nitride layer; 10-a back electrode; 11-connecting blocks; 12-a first fixed block; 13-second fixed block.

Detailed Description

The technical scheme of the utility model is further explained by the specific implementation mode in combination with the attached drawings.

In a specific embodiment, the utility model provides a back passivation structure of a PERC battery, which is shown in fig. 1 and comprises a first crystalline silicon oxide layer 6, a gallium oxide layer 7, a second crystalline silicon oxide layer 8 and at least two back silicon nitride layers 9, which are sequentially stacked from the back of a silicon substrate 5. The thickness of the first crystalline silicon oxide layer 6 is 1-10 nm, the thickness of the gallium oxide layer 7 is 5-10 nm, the thickness of the second crystalline silicon oxide layer 8 is 1-10 nm, the total thickness of all the back silicon nitride layers 9 is 40-80 nm, and the thickness of each back silicon nitride layer 9 is gradually reduced from inside to outside.

The silicon substrate 5 and the first crystalline silicon oxide layer 6 are provided with a connecting block 11 at the contact surface, the connecting block 11 and the first crystalline silicon oxide layer 6 are of an integral structure, and the connecting block 11 is embedded in the silicon substrate 5. The contact surface of the first crystalline silicon oxide layer 6 and the gallium oxide layer 7 is provided with a first fixed block 12, the first fixed block 12 and the gallium oxide layer 7 are of an integral structure, and the first fixed block 12 is embedded in the first crystalline silicon oxide layer 6. A second fixed block 13 is arranged at the contact surface of the gallium oxide layer 7 and the second crystalline silicon oxide layer 8, the second fixed block 13 and the gallium oxide layer 7 are of an integral structure, and the second fixed block 13 is embedded in the second crystalline silicon oxide layer 8.

In another embodiment, the utility model provides a PERC cell, as shown in fig. 1, comprising a silicon substrate 5, wherein the front surface of the silicon substrate 5 is sequentially laminated with an emitter 4, a front surface silicon oxide layer 3 and a front surface silicon nitride layer 2, and the back surface of the silicon substrate 5 is provided with the back passivation structure of the PERC cell as provided in the above embodiments.

The PERC cell also comprises a front electrode 1 and a back electrode 10, wherein the front electrode 1 is vertically inserted into the silicon substrate 5 from the front side of the PERC cell, and the back electrode 10 is vertically inserted into the silicon substrate 5 from the back side of the PERC cell.

Example 1

The embodiment provides a PERC battery, which is based on the PERC battery provided in an embodiment, wherein the thickness of the first crystalline silicon oxide layer 6 is 1nm, the thickness of the gallium oxide layer 7 is 5nm, the thickness of the second silicon oxide layer is 1nm, the back silicon nitride layer 9 is two layers, which are respectively denoted as a first back silicon nitride layer and a second back silicon nitride layer, the thickness of the first back silicon nitride layer is 15nm, and the thickness of the second back silicon nitride layer is 25 nm.

Example 2

The embodiment provides a PERC battery, which is based on the PERC battery provided in an embodiment, wherein the first crystalline silicon oxide layer 6 has a thickness of 3nm, the gallium oxide layer 7 has a thickness of 6nm, the second crystalline silicon oxide layer 8 has a thickness of 3nm, and the back silicon nitride layer 9 has two layers, which are respectively denoted as a first back silicon nitride layer and a second back silicon nitride layer, the first back silicon nitride layer has a thickness of 20nm, and the second back silicon nitride layer has a thickness of 30 nm.

Example 3

The embodiment provides a PERC battery, which is based on the PERC battery provided in an embodiment, wherein the first crystalline silicon oxide layer 6 has a thickness of 5nm, the gallium oxide layer 7 has a thickness of 7nm, the second crystalline silicon oxide layer 8 has a thickness of 5nm, and the back silicon nitride layer 9 has three layers, which are respectively denoted as a first back silicon nitride layer, a second back silicon nitride layer, and a third back silicon nitride layer, where the first back silicon nitride layer has a thickness of 10nm, the second back silicon nitride layer has a thickness of 20nm, and the third back silicon nitride layer has a thickness of 30 nm.

Example 4

The embodiment provides a PERC battery, which is based on the PERC battery provided in an embodiment, wherein the first crystalline silicon oxide layer 6 has a thickness of 7nm, the gallium oxide layer 7 has a thickness of 8nm, the second crystalline silicon oxide layer 8 has a thickness of 7nm, the back silicon nitride layer 9 has two layers, which are respectively denoted as a first back silicon nitride layer, a second back silicon nitride layer and a third back silicon nitride layer, the first back silicon nitride layer has a thickness of 15nm, the second back silicon nitride layer has a thickness of 25nm, and the third back silicon nitride layer has a thickness of 30 nm.

Example 5

The embodiment provides a PERC battery, which is based on the PERC battery provided in an embodiment, wherein the first crystalline silicon oxide layer 6 has a thickness of 9nm, the gallium oxide layer 7 has a thickness of 9nm, the second crystalline silicon oxide layer 8 has a thickness of 9nm, the back silicon nitride layer 9 has four layers, which are respectively denoted as a first back silicon nitride layer, a second back silicon nitride layer, a third back silicon nitride layer and a fourth back silicon nitride layer, the first back silicon nitride layer has a thickness of 5nm, the second back silicon nitride layer has a thickness of 10nm, the third back silicon nitride layer has a thickness of 20nm, and the fourth back silicon nitride layer has a thickness of 30 nm.

Example 6

The present embodiment provides a PERC battery, where the PERC battery is provided according to a specific embodiment, the first crystalline silicon oxide layer 6 has a thickness of 10nm, the gallium oxide layer 7 has a thickness of 10nm, the second crystalline silicon oxide layer 8 has a thickness of 10nm, the back silicon nitride layer 9 has four layers, which are respectively denoted as a first back silicon nitride layer, a second back silicon nitride layer, a third back silicon nitride layer, and a fourth back silicon nitride layer, the first back silicon nitride layer has a thickness of 10nm, the second back silicon nitride layer has a thickness of 15nm, the third back silicon nitride layer has a thickness of 25nm, and the fourth back silicon nitride layer has a thickness of 30 nm.

Example 7

This example provides a method of making the PERC cell of example 3, the method comprising the steps of:

(1) performing texturing treatment on the surface of the monocrystalline silicon substrate 5 at 80 ℃ by adopting a mixed solution of NaOH, water and ethanol to form a textured surface, wherein the volume ratio of the NaOH to the water to the ethanol is 10:330: 2.2; cleaning the monocrystalline silicon substrate 5 after texturing;

(2) carrying out phosphorus diffusion on the cleaned silicon substrate 5, generating phosphorus-silicon glass on the surface, and doping laser on the front surface of the silicon substrate 5 to form a local heavily-doped area to obtain a selective emitter 4;

(3) etching by using an HF aqueous solution to remove the phosphorosilicate glass on the rest surface of the silicon substrate 5, wherein the volume ratio of water to HF in the HF aqueous solution is 40: 3;

(4) depositing on the surface of the selective emitter 4 by a thermal oxidation method to form a front silicon oxide layer 3;

(5) putting the silicon substrate 5 into a film forming chamber, and introducing laughing gas and silane into the film forming chamber, wherein the introduction flow rate of the laughing gas is 5000sccm, and the introduction flow rate of the silane is 620 sccm; maintaining the pressure in the film forming chamber at 1500Pa, depositing on the back of the silicon substrate 5 by adopting a plasma enhanced chemical vapor deposition method to form an amorphous silicon oxide film, wherein the radio frequency power of the plasma is 7600W, and the deposition time is 100 s;

(6) then, annealing the silicon substrate 5 under a hydrogen-rich atmosphere, wherein the hydrogen-rich atmosphere is a mixed gas of nitrogen and helium, hydrogen accounts for 60% of the total volume of the mixed gas, the annealing temperature is 1050 ℃, the annealing time is 5min, and after the annealing is finished, the amorphous silicon oxide film is converted into a first crystalline silicon oxide layer 6 with the thickness of 5 nm;

(7) depositing a gallium oxide layer 7 with the thickness of 7nm on the surface of the first crystalline silicon oxide layer 6 by ALD;

(8) repeating the step (5) and the step (6), and depositing a second crystalline silicon oxide layer 8 with the thickness of 5nm on the surface of the gallium oxide layer 7;

(9) depositing a first back silicon nitride layer, a second back silicon nitride layer and a third back silicon nitride layer on the surface of the second crystalline silicon oxide layer 8 in sequence by adopting PECVD;

(10) depositing on the surface of the front silicon oxide layer 3 by adopting PECVD to form a front silicon nitride layer 2;

(11) the front electrode 1 and the back electrode 10 are formed on the front and back surfaces of the silicon wafer by screen printing and sintering, respectively.

The applicant declares that the above description is only a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and it should be understood by those skilled in the art that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are within the scope and disclosure of the present invention.

Claims (10)

1. The PERC battery back passivation structure is characterized by comprising a first crystalline silicon oxide layer, a gallium oxide layer, a second crystalline silicon oxide layer and at least two back silicon nitride layers, wherein the first crystalline silicon oxide layer, the gallium oxide layer, the second crystalline silicon oxide layer and the at least two back silicon nitride layers are sequentially stacked from the back of a silicon substrate.

2. The PERC cell back passivation structure of claim 1, wherein a connection pad is disposed at a contact surface of the silicon substrate and the first crystalline silicon oxide layer, the connection pad and the first crystalline silicon oxide layer are integrated, and the connection pad is embedded in the silicon substrate.

3. The PERC cell back passivation structure of claim 1, wherein a first fixed block is disposed at a contact surface of the first crystalline silicon oxide layer and the gallium oxide layer, the first fixed block and the gallium oxide layer are integrated, and the first fixed block is embedded in the first crystalline silicon oxide layer.

4. The PERC battery back passivation structure of claim 1, wherein a second fixed block is disposed at a contact surface of the gallium oxide layer and the second crystalline silicon oxide layer, the second fixed block and the gallium oxide layer are integrated, and the second fixed block is embedded inside the second crystalline silicon oxide layer.

5. The PERC cell back passivation structure of claim 1, wherein the thickness of the first crystalline silicon oxide layer is 1-10 nm.

6. The PERC cell back passivation structure of claim 1, wherein the thickness of the gallium oxide layer is 5-10 nm.

7. The PERC cell back passivation structure of claim 1, wherein the second crystalline silicon oxide layer has a thickness of 1-10 nm.

8. The PERC cell back passivation structure of claim 1, wherein the total thickness of all back side silicon nitride layers is 40-80 nm.

9. The PERC cell back passivation structure of claim 1, wherein the thickness of each of the back silicon nitride layers is graded from inside to outside.

10. A PERC cell, wherein said PERC cell comprises a silicon substrate, wherein an emitter, a front silicon oxide layer and a front silicon nitride layer are sequentially stacked on the front surface of said silicon substrate, and a back passivation structure of said PERC cell according to any one of claims 1 to 9 is disposed on the back surface of said silicon substrate;

the PERC battery also comprises a front electrode and a back electrode, wherein the front electrode is vertically inserted into the silicon substrate from the front side of the PERC battery, and the back electrode is vertically inserted into the silicon substrate from the back side of the PERC battery.

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