CN215647560U - Multilayer printed circuit board - Google Patents
Multilayer printed circuit board Download PDFInfo
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- CN215647560U CN215647560U CN202121918424.8U CN202121918424U CN215647560U CN 215647560 U CN215647560 U CN 215647560U CN 202121918424 U CN202121918424 U CN 202121918424U CN 215647560 U CN215647560 U CN 215647560U
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Abstract
The utility model discloses a multilayer printed circuit board, which comprises an insulating substrate, an upper conductive pattern layer, a first middle conductive pattern layer, a second middle conductive pattern layer and a lower conductive pattern layer, wherein the upper conductive pattern layer is electrically connected with the first middle conductive pattern layer through at least 2 first blind hole groups, the lower conductive pattern layer is electrically connected with the second middle conductive pattern layer through at least 2 second blind hole groups, and the upper conductive pattern layer is electrically connected with the lower conductive pattern layer through at least 2 through hole groups; the through hole group consists of a plurality of through holes which are distributed at intervals and sequentially penetrate through the first dielectric layer, the insulating substrate and the second dielectric layer, and the first blind hole group, the second blind hole group and the through hole groups are alternately distributed at intervals in the plane direction of the circuit board. The multilayer printed circuit board improves the density of devices, reduces the volume of the circuit board and effectively prevents mutual interference between internal signals.
Description
Technical Field
The utility model relates to a circuit main board, and belongs to the technical field of electronic information.
Background
In the prior art, as the functions of various electronic products are gradually comprehensive, multifunctional and complicated, and the design of the electronic products is gradually light, thin, short and small, higher requirements are put forward on the high-density and high-integration design of a circuit board. In order to improve the carrying capacity of the circuit board, a multilayer circuit is generally stacked on the surface of the circuit board to improve the density of the circuit, dielectric holes are formed between the multilayer circuits at interlayer interconnection positions by means of laser or mechanical drilling, and then an electrically-conducting electroplated layer is formed on the dielectric holes. However, the existing circuit board still has technical defects to be overcome.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a multilayer printed circuit board, which improves the density of devices, reduces the volume of the circuit board and effectively prevents mutual interference between internal signals.
In order to achieve the purpose, the utility model adopts the technical scheme that: a multilayer printed circuit board comprises an insulating substrate, an upper conductive pattern layer, a first middle conductive pattern layer, a second middle conductive pattern layer and a lower conductive pattern layer, wherein the first middle conductive pattern layer and the second middle conductive pattern layer are respectively positioned on the upper surface and the lower surface of the insulating substrate;
a first dielectric layer is arranged between the first middle conductive pattern layer and the upper conductive pattern layer, and a second dielectric layer is arranged between the second middle conductive pattern layer and the lower conductive pattern layer;
the upper conductive pattern layer is electrically connected with the first middle conductive pattern layer through at least 2 first blind hole groups, the lower conductive pattern layer is electrically connected with the second middle conductive pattern layer through at least 2 second blind hole groups, and the upper conductive pattern layer is electrically connected with the lower conductive pattern layer through at least 2 through hole groups;
the first blind hole group consists of a plurality of first blind holes which are distributed at intervals and penetrate through the first medium layer, the second blind hole group consists of a plurality of second blind holes which are distributed at intervals and penetrate through the second medium layer, and the through hole group consists of a plurality of through holes which are distributed at intervals and sequentially penetrate through the first medium layer, the insulating substrate and the second medium layer;
and a through hole group is arranged between the adjacent first blind hole groups, and a through hole group is arranged between the adjacent second blind hole groups, so that the first blind hole groups, the second blind hole groups and the through hole groups are alternately distributed at intervals in the plane direction of the circuit board.
The further improved scheme in the technical scheme is as follows:
1. in the above scheme, the region of the through hole between the first dielectric layer and the insulating substrate is a first trapezoid hole, and the opening of the first trapezoid hole, which is in contact with the upper conductive pattern layer, is a wide opening.
2. In the above scheme, the region of the through hole between the second dielectric layer and the insulating substrate is a second trapezoid hole, and the opening of the second trapezoid hole, which is in contact with the lower conductive pattern layer, is a wide opening.
3. In the scheme, the thickness of the first dielectric layer and the second dielectric layer is 100-200 microns.
Due to the application of the technical scheme, compared with the prior art, the utility model has the following advantages and effects:
1. the multilayer printed circuit board is provided with the upper conductive pattern layer, the first middle conductive pattern layer, the second middle conductive pattern layer and the lower conductive pattern layer which are positioned on two sides of the insulating substrate respectively, so that electronic devices can be connected on the upper surface and the lower surface, the density of the devices is further improved, the volume of the circuit board is reduced, and the miniaturization of electronic products is facilitated.
2. The first blind hole group of the multilayer printed circuit board consists of a plurality of first blind holes which are distributed at intervals and penetrate through a first medium layer, the second blind hole group consists of a plurality of second blind holes which are distributed at intervals and penetrate through a second medium layer, the through hole group consists of a plurality of through holes which are distributed at intervals and sequentially penetrate through the first medium layer, an insulating substrate and the second medium layer, and the first blind hole group, the second blind hole group and the through hole group are alternately distributed at intervals in the plane direction of the circuit board.
Drawings
FIG. 1 is a schematic view of a multilayer printed circuit board according to the present invention.
In the above drawings: 1. an insulating substrate; 2. an upper conductive pattern layer; 3. a first middle conductive pattern layer; 4. a lower conductive pattern layer; 5. a first dielectric layer; 6. a second dielectric layer; 7. a first blind hole group; 71. a first blind hole; 8. a second blind hole group; 81. a second blind hole; 9. a second middle conductive pattern layer; 10. a group of through holes; 101. a through hole; 102. a first trapezoidal hole; 103. a second trapezoidal hole.
Detailed Description
In the description of this patent, it is noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention; the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, as they may be fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The meaning of the above terms in this patent may be specifically understood by those of ordinary skill in the art.
Example 1: a multilayer printed circuit board comprises an insulating substrate 1, an upper conductive pattern layer 2, a first middle conductive pattern layer 3, a second middle conductive pattern layer 9 and a lower conductive pattern layer 4, wherein the first middle conductive pattern layer 3 and the second middle conductive pattern layer 9 are respectively positioned on the upper surface and the lower surface of the insulating substrate 1;
a first dielectric layer 5 is arranged between the first middle conductive pattern layer 3 and the upper conductive pattern layer 2, and a second dielectric layer 6 is arranged between the second middle conductive pattern layer 9 and the lower conductive pattern layer 4;
the upper conductive pattern layer 2 is electrically connected with the first middle conductive pattern layer 3 through at least 2 first blind hole groups 7, the lower conductive pattern layer 4 is electrically connected with the second middle conductive pattern layer 9 through at least 2 second blind hole groups 8, and the upper conductive pattern layer 2 is electrically connected with the lower conductive pattern layer 4 through at least 2 through hole groups 10;
the first blind hole group 7 consists of a plurality of first blind holes 71 which are distributed at intervals and penetrate through the first medium layer 5, the second blind hole group 8 consists of a plurality of second blind holes 81 which are distributed at intervals and penetrate through the second medium layer 6, and the through hole group 10 consists of a plurality of through holes 101 which are distributed at intervals and sequentially penetrate through the first medium layer 5, the insulating substrate 1 and the second medium layer 6;
a through hole group 10 is arranged between the adjacent first blind hole groups 7, and a through hole group 10 is arranged between the adjacent second blind hole groups 8, so that the first blind hole groups 7, the second blind hole groups 8 and the through hole groups 10 are alternately distributed at intervals in the plane direction of the circuit board.
The area of the through hole 101 between the first dielectric layer 5 and the insulating substrate 1 is a first trapezoid hole 102, and an opening of the first trapezoid hole 102 contacting the upper conductive pattern layer 2 is a wide opening.
The through hole 101 is a second trapezoid hole 103 in the area between the second dielectric layer 6 and the insulating substrate 1, and the opening of the second trapezoid hole 103 contacting the lower conductive pattern layer 4 is a wide opening.
The thickness of the first dielectric layer 4 and the second dielectric layer 5 is 120 micrometers.
Example 2: a multilayer printed circuit board comprises an insulating substrate 1, an upper conductive pattern layer 2, a first middle conductive pattern layer 3, a second middle conductive pattern layer 9 and a lower conductive pattern layer 4, wherein the first middle conductive pattern layer 3 and the second middle conductive pattern layer 9 are respectively positioned on the upper surface and the lower surface of the insulating substrate 1;
a first dielectric layer 5 is arranged between the first middle conductive pattern layer 3 and the upper conductive pattern layer 2, and a second dielectric layer 6 is arranged between the second middle conductive pattern layer 9 and the lower conductive pattern layer 4;
the upper conductive pattern layer 2 is electrically connected with the first middle conductive pattern layer 3 through at least 2 first blind hole groups 7, the lower conductive pattern layer 4 is electrically connected with the second middle conductive pattern layer 9 through at least 2 second blind hole groups 8, and the upper conductive pattern layer 2 is electrically connected with the lower conductive pattern layer 4 through at least 2 through hole groups 10;
the first blind hole group 7 consists of a plurality of first blind holes 71 which are distributed at intervals and penetrate through the first medium layer 5, the second blind hole group 8 consists of a plurality of second blind holes 81 which are distributed at intervals and penetrate through the second medium layer 6, and the through hole group 10 consists of a plurality of through holes 101 which are distributed at intervals and sequentially penetrate through the first medium layer 5, the insulating substrate 1 and the second medium layer 6;
a through hole group 10 is arranged between the adjacent first blind hole groups 7, and a through hole group 10 is arranged between the adjacent second blind hole groups 8, so that the first blind hole groups 7, the second blind hole groups 8 and the through hole groups 10 are alternately distributed at intervals in the plane direction of the circuit board.
The thickness of the first dielectric layer 4 and the second dielectric layer 5 is 160 μm.
When the multilayer printed circuit board is adopted, the upper surface and the lower surface of the multilayer printed circuit board can be connected with electronic devices, so that the density of the devices is further improved, the volume of the circuit board is reduced, and the miniaturization of electronic products is facilitated; in addition, the first blind hole group consists of a plurality of first blind holes which are distributed at intervals and penetrate through the first dielectric layer, the second blind hole group consists of a plurality of second blind holes which are distributed at intervals and penetrate through the second dielectric layer, the through hole group consists of a plurality of through holes which are distributed at intervals and sequentially penetrate through the first dielectric layer, the insulating substrate and the second dielectric layer, and the first blind hole group, the second blind hole group and the through hole group are alternately distributed at intervals in the plane direction of the circuit board.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (4)
1. A multilayer printed circuit board characterized by: the circuit comprises an insulating substrate (1), an upper conductive pattern layer (2), a first middle conductive pattern layer (3), a second middle conductive pattern layer (9) and a lower conductive pattern layer (4), wherein the first middle conductive pattern layer (3) and the second middle conductive pattern layer (9) are respectively positioned on the upper surface and the lower surface of the insulating substrate (1);
a first dielectric layer (5) is arranged between the first middle conductive pattern layer (3) and the upper conductive pattern layer (2), and a second dielectric layer (6) is arranged between the second middle conductive pattern layer (9) and the lower conductive pattern layer (4);
the upper conductive pattern layer (2) is electrically connected with the first middle conductive pattern layer (3) through at least 2 first blind hole groups (7), the lower conductive pattern layer (4) is electrically connected with the second middle conductive pattern layer (9) through at least 2 second blind hole groups (8), and the upper conductive pattern layer (2) is electrically connected with the lower conductive pattern layer (4) through at least 2 through hole groups (10);
the first blind hole group (7) is composed of a plurality of first blind holes (71) which are distributed at intervals and penetrate through the first medium layer (5), the second blind hole group (8) is composed of a plurality of second blind holes (81) which are distributed at intervals and penetrate through the second medium layer (6), and the through hole group (10) is composed of a plurality of through holes (101) which are distributed at intervals and penetrate through the first medium layer (5), the insulating substrate (1) and the second medium layer (6) in sequence;
a through hole group (10) is arranged between the adjacent first blind hole groups (7), and a through hole group (10) is arranged between the adjacent second blind hole groups (8), so that the first blind hole groups (7), the second blind hole groups (8) and the through hole groups (10) are alternately distributed at intervals in the plane direction of the circuit board.
2. The multilayer printed circuit board of claim 1, wherein: the through hole (101) is positioned between the first dielectric layer (5) and the insulating substrate (1) and is provided with a first trapezoidal hole (102), and an opening of the first trapezoidal hole (102) contacting with the upper conductive pattern layer (2) is wide.
3. The multilayer printed circuit board of claim 1, wherein: the area of the through hole (101) between the second dielectric layer (6) and the insulating substrate (1) is a second trapezoid hole (103), and an opening of the second trapezoid hole (103) contacting with the lower conductive pattern layer (4) is a wide opening.
4. The multilayer printed circuit board of claim 1, wherein: the thickness of the first dielectric layer (5) and the second dielectric layer (6) is 100-200 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121918424.8U CN215647560U (en) | 2021-08-16 | 2021-08-16 | Multilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121918424.8U CN215647560U (en) | 2021-08-16 | 2021-08-16 | Multilayer printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215647560U true CN215647560U (en) | 2022-01-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202121918424.8U Active CN215647560U (en) | 2021-08-16 | 2021-08-16 | Multilayer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN215647560U (en) |
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2021
- 2021-08-16 CN CN202121918424.8U patent/CN215647560U/en active Active
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